Danovitch
David Danovitch, Bromont CA
Patent application number | Description | Published |
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20110044369 | SILICON CARRIER OPTOELECTRONIC PACKAGING - An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board. | 02-24-2011 |
20110079632 | MULTISTACK SOLDER WAFER FILLING - A plurality of through-substrate holes is formed in each of at least one substrate. Each through-substrate hole extends from a top surface of the at least one substrate to the bottom surface of the at least one substrate. The at least one substrate is held by a stationary chuck or a rotating chuck. Vacuum suction is provided to a set of through-substrate holes among the plurality of through-substrate holes through a vacuum manifold attached to the bottom surface of the at least one substrate. An injection mold solder head located above the top surface of the at least one substrate injects a solder material into the set of through-substrate holes to form a plurality of through-substrate solders that extend from the top surface to the bottom surface of the at least one substrate. The vacuum suction prevents formation of air bubbles or incomplete filling in the plurality of through-substrate holes. | 04-07-2011 |
20120326290 | SILICON CARRIER OPTOELECTRONIC PACKAGING - An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board. | 12-27-2012 |
David Danovitch, Quebec CA
Patent application number | Description | Published |
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20100181665 | System and Method of Achieving Mechanical and Thermal Stability in a Multi-Chip Package - A system and method system for achieving mechanical and thermal stability in a multi-chip package. The system utilizes a lid and multiple thermal interface materials. The method includes utilizing a lid on a multi-chip package and utilizing multiple thermal interface materials on the multi-chip package. | 07-22-2010 |
20100276813 | INJECTION MOLDED SOLDERING PROCESS AND ARRANGEMENT FOR THREE-DIMENSIONAL STRUCTURES - A method of implementing an injection molded soldering process for three-dimensional structures, particularly, such as directed to three-dimensional semiconductor chip stacking. Also provide is an arrangement for implementing the injection molded soldering (IMS) process. Pursuant to an embodiment of the invention, the joining of the semiconductor chip layers with a substrate is implemented, rather than by means of currently known wire bond stacking, through the intermediary of columns of solder material formed by the IMS process, thereby providing electrical advantages imparted by the flip chip interconnect structures. In this connection, various diversely dimensioned solder column interconnects allow for simple and dependable connections to a substrate by a plurality of superimposed layers or stacked arrays of semiconductor components, such as semiconductor chips. In accordance with a further aspect, it is possible to derive a unique design for an IMS mold structure, which contains cavities for forming the columnar fill of solder, and which also incorporates further cavities acting as cutouts for dies or the positioning of other electronic packages or modules. | 11-04-2010 |
20120175766 | SYSTEM AND METHOD OF ACHIEVING MECHANICAL AND THERMAL STABILITY IN A MULTI-CHIP PACKAGE - A system and method system for achieving mechanical and thermal stability in a multi-chip package. The system utilizes a lid and multiple thermal interface materials. The method includes utilizing a lid on a multi-chip package and utilizing multiple thermal interface materials on the multi-chip package. | 07-12-2012 |
David Danovitch, Canton De Granby CA
Patent application number | Description | Published |
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20120234902 | MULTISTACK SOLDER WAFER FILLING - A plurality of through-substrate holes is formed in each of at least one substrate. Each through-substrate hole extends from a top surface of the at least one substrate to the bottom surface of the at least one substrate. The at least one substrate is held by a stationary chuck or a rotating chuck. Vacuum suction is provided to a set of through-substrate holes among the plurality of through-substrate holes through a vacuum manifold attached to the bottom surface of the at least one substrate. An injection mold solder head located above the top surface of the at least one substrate injects a solder material into the set of through-substrate holes to form a plurality of through-substrate solders that extend from the top surface to the bottom surface of the at least one substrate. The vacuum suction prevents formation of air bubbles or incomplete filling in the plurality of through-substrate holes. | 09-20-2012 |
David D. Danovitch, Canton De Granby CA
Patent application number | Description | Published |
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20080265435 | STRUCTURE AND METHOD FOR STRESS REDUCTION IN FLIP CHIP MICROELECTRONIC PACKAGES USING UNDERFILL MATERIALS WITH SPATIALLY VARYING PROPERTIES - A structure for a flip chip package assembly includes: a flip chip die with solder attach bumps; a substrate for receiving and solder attaching the flip chip die; an underfill material with spatially varying curing properties applied to fill voids between the flip chip die and the substrate, and for forming a fillet around the perimeter of the flip chip die and extending to the surface of the substrate; and wherein the portion of the underfill material forming the fillets is cured prior to curing the portion of the underfill material that fills the voids between the flip chip die and the substrate. | 10-30-2008 |
David H. Danovitch, Canton De Granby CA
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20090294090 | MOLD SHAVE APPARATUS AND INJECTION MOLDED SOLDERING PROCESS - An apparatus for the removal of excess solder or contaminant, which are encountered on the surfaces of injection mold prior to the transfer of a solder on a silicon wafer. More particularly, there is provided an apparatus for the removal of excess solder, which may be present on a mold surface, without removing any solder, which is located in cavities formed in the mold, and wherein the solder is applied through an injection molded soldering process. | 12-03-2009 |
David Hirsch Danovitch, Granby, CA US
Patent application number | Description | Published |
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20100326702 | INTEGRATED CIRCUIT ASSEMBLY - Methods and apparatus for forming an integrated circuit assembly are presented, for example, three dimensional integrated circuit assemblies. Lower height 3DIC assemblies due Use of, for example, thinned wafers, low-height solder bumps, and through silicon vias provide for low height three dimensional integrated circuit assemblies. For example, a method for forming an integrated circuit assembly comprises forming first solder bumps on a first die, and forming a first structure comprising the first die, the first solder bumps, a first flux, and a first substratum. The first die is placed upon the first substratum. The first solder bumps are between the first die and the first substratum. The first flux holds the first die substantially flat and onto the first substratum. | 12-30-2010 |