Patent application number | Description | Published |
20090172468 | METHOD FOR PROVIDING DEFERRED MAINTENANCE ON STORAGE SUBSYSTEMS - A set of disks in a plurality of disk arrays are configured to have one or more spare partitions. Upon detecting a faulty disk in a faulty array, the method involves the steps of: (a) migrating data in the faulty array containing the faulty disk to one or more spare partitions; (b) reconfiguring the faulty array to form a new array without the faulty disk; (c) migrating data from one or more spare partitions in the set of disks to the reconfigured new array; (d) monitoring to identify when overall spare capacity falls below a predetermined threshold; and when the predetermined threshold is exceeded, scheduling a service visit for replacement of the failed disks. | 07-02-2009 |
20090177918 | STORAGE REDUNDANT ARRAY OF INDEPENDENT DRIVES - A computer implemented method, apparatus, and computer usable program product for managing redundant array of independent drives. In response to a failure of a hard disk in a first RAID array, the process calculates an amount of free capacity available across a set of remaining hard disks in the first RAID array. The set of remaining hard disks comprises every hard disk associated with the first RAID array except the failed disk. In response to a determination that the amount of free capacity is sufficient to re-create the first RAID array at a same RAID level, the process reconstructs the first RAID array using an amount of space in the set of remaining drives utilized by the first RAID array and the free capacity to form a new RAID array without utilizing a spare hard disk. | 07-09-2009 |
20090254705 | BUS ATTACHED COMPRESSED RANDOM ACCESS MEMORY - A computer memory system having a three-level memory hierarchy structure is disclosed. The system includes a memory controller, a volatile memory, and a non-volatile memory. The volatile memory is divided into an uncompressed data region and a compressed data region. | 10-08-2009 |
20090287901 | SYSTEM AND METHOD FOR CONTENT REPLICATION DETECTION AND ELIMINATION IN MAIN MEMORY - A system and method for effectively increasing the amount of data that can be stored in the main memory of a computer, particularly, by a hardware enhancement of a memory controller apparatus that detects duplicate memory contents and eliminates duplicate memory contents wherein the duplication and elimination are performed by hardware without imposing any penalty on the overall performance of the system. | 11-19-2009 |
20120131248 | MANAGING COMPRESSED MEMORY USING TIERED INTERRUPTS - Systems and methods to manage memory are provided. A particular method may include initiating a memory compression operation. The method may further include initiating a first interrupt configured to affect a first process executing on a processor in response to a first detected memory level. A second initiated interrupt may be configured to affect the first process executing on the processor in response to a second detected memory level, and a third interrupt may be initiated to affect the first process executing on the processor in response to a third detected memory level. At least of the first, the second, and the third detected memory levels are affected by the memory compression operation. | 05-24-2012 |
20120204071 | WEAR-LEVELING AND BAD BLOCK MANAGEMENT OF LIMITED LIFETIME MEMORY DEVICES - Performing wear-leveling and bad block management of limited lifetime memory devices. A method for performing wear-leveling in a memory includes receiving logical memory addresses and applying a randomizing function to the logical memory addresses to generate intermediate addresses within a range of intermediate addresses. The intermediate addresses are mapped into physical addresses of a memory using an algebraic mapping. The physical addresses are within a range of physical addresses that include at least one more location than the range of intermediate addresses. The physical addresses are output for use in accessing the memory. The mapping between the intermediate addresses and the physical addresses is periodically shifted. In addition, contents of bad blocks are replaced with redundantly encoded redirection addresses. | 08-09-2012 |
20130147643 | UNPACKING A VARIABLE NUMBER OF DATA BITS - Unpacking a variable number of data bits is provided. A structure includes an input port operable to receive one or more input data units including a plurality of packed bits of data, each of the one or more input data units including a header and a payload, the header including a predetermined number of bits and identifying a format of the payload and a length of the payload, and the payload including a variable number of bits. The structure further includes a circuit operable to identify and unpack the one or more input data units based on the header and the payload of each of the one or more input data units. The structure further includes an output port operable to transmit one or more output data units including the unpacked one or more input data units, once per clock cycle. | 06-13-2013 |
20130185537 | HASH TABLE USING HASH TABLE BANKS - A hash table method and structure comprises a processor that receives a plurality of access requests for access to a storage device. The processor performs a plurality of hash processes on the access requests to generate a first number of addresses for each access request. Such addresses are within a full address range. Hash table banks are operatively connected to the processor. The hash table banks form the storage device. Each of the hash table banks has a plurality of input ports. Specifically, each of the hash table banks has less input ports than the first number of addresses for each access request. The processor provides the addresses to the hash table banks, and each of the hash table banks stores pointers corresponding to a different limited range of addresses within the full address range (each of the different limited range of addresses is less than the full address range). | 07-18-2013 |
20130254526 | EFFECT TRANSLATION AND ASSESSMENT AMONG MICROARCHITECTURE COMPONENTS - Awareness of the relationships among the operating parameters for an individual core and among cores allows dynamic and intelligent management of the multi-core system. The relationships among operating parameters and cores, which can be somewhat opaque, are established with design-time simulations, and adapted with run time data collected from operation of the multi-core system. The relationships are expressed with functions that translate between operating parameters, between different cores, and between operating parameters of different cores. These functions are embodied in circuitry built into the multi-core system. The circuitry will be referred to hereinafter as a translator unit. The translator unit traverses the complex relational dependencies among multiple operating parameters and multiple cores, and determines an outcome with respect to one or more constraints corresponding to those operating parameters and cores. | 09-26-2013 |
20130297879 | PROBABILISTIC ASSOCIATIVE CACHE - A computer cache memory organization called Probabilistic Set Associative Cache (PAC) has the hardware complexity and latency of a direct-mapped cache but functions as a set-associative cache for a fraction of the time, thus yielding better than direct mapped cache hit rates. The organization is considered a (1+P)—way set associative cache, where the chosen parameter called | 11-07-2013 |
20140047175 | IMPLEMENTING EFFICIENT CACHE TAG LOOKUP IN VERY LARGE CACHE SYSTEMS - A method and circuit for implementing a cache directory and efficient cache tag lookup in very large cache systems, and a design structure on which the subject circuit resides are provided. A tag cache includes a fast partial large (LX) cache directory maintained separately on chip apart from a main LX cache directory (LXDIR) stored off chip in dynamic random access memory (DRAM) with large cache data (LXDATA). The tag cache stores most frequently accessed LXDIR tags. The tag cache contains predefined information enabling access to LXDATA directly on tag cache hit with matching address and data present in the LX cache. Only on tag cache misses the LXDIR is accessed to reach LXDATA. | 02-13-2014 |
20140052957 | TRANSLATION TABLE AND METHOD FOR COMPRESSED DATA - A translation table has entries that each include a share bit and a delta bit, with pointers that point to a memory block that includes reuse bits. When two translation table entries reference identical fragments in a memory block, one of the translation table entries is changed to refer to the same memory block referenced in the other translation table entry, which frees up a memory block. The share bit is set to indicate a translation table entry is sharing its memory block with another translation table entry. In addition, a translation table entry may include a private delta in the form of a pointer that references a memory fragment in the memory block that is not shared with other translation table entries. When a translation table has a private delta, its delta bit is set. | 02-20-2014 |
20140052958 | TRANSLATION TABLE AND METHOD FOR COMPRESSED DATA - A translation table has entries that each include a share bit and a delta bit, with pointers that point to a memory block that includes reuse bits. When two translation table entries reference identical fragments in a memory block, one of the translation table entries is changed to refer to the same memory block referenced in the other translation table entry, which frees up a memory block. The share bit is set to indicate a translation table entry is sharing its memory block with another translation table entry. In addition, a translation table entry may include a private delta in the form of a pointer that references a memory fragment in the memory block that is not shared with other translation table entries. When a translation table has a private delta, its delta bit is set. | 02-20-2014 |
20140075150 | METHOD FOR GENERATING A DELTA FOR COMPRESSED DATA - A translation table has entries that each include a share bit and a delta bit, with pointers that point to a memory block that includes reuse bits. The share bit is set to indicate a translation table entry is sharing its memory block with another translation table entry. In addition, a translation table entry may include a private delta in the form of a pointer that references a memory fragment in the memory block that is not shared with other translation table entries, wherein the private delta references previously-stored content. When a translation table has a private delta, its delta bit is set. The private delta is generated by analyzing a data buffer for content that is similar to previously-stored content. | 03-13-2014 |
20140075152 | METHOD FOR GENERATING A DELTA FOR COMPRESSED DATA - A translation table has entries that each include a share bit and a delta bit, with pointers that point to a memory block that includes reuse bits. The share bit is set to indicate a translation table entry is sharing its memory block with another translation table entry. In addition, a translation table entry may include a private delta in the form of a pointer that references a memory fragment in the memory block that is not shared with other translation table entries, wherein the private delta references previously-stored content. When a translation table has a private delta, its delta bit is set. The private delta is generated by analyzing a data buffer for content that is similar to previously-stored content. | 03-13-2014 |
20140164828 | CONSISTENCY OF DATA IN PERSISTENT MEMORY - Consistency of data stored in persistent memory is maintained using separate commit and harden operations for a transaction. A transaction is committed with a processing device, the committing including marking an end of an atomic operation on a modified object from the transaction, creating a new copy of the modified object, and storing a mapping of the modified object to the new copy of the modified object in a recorded log. A checksum identifying the modified object is created and stored in the recorded log. The transaction is hardened by storing the modified object and the recorded log from cache into persistent memory. | 06-12-2014 |
20140195719 | INSTANTANEOUS SAVE/RESTORE OF VIRTUAL MACHINES WITH PERSISTENT MEMORY - A computer implemented method creates a snapshot of a logical volume of a computer. The computer stores a system state of the computer in persistent memory. The computer flushes a cash of the computer. The computer identifies a preceding snapshot. Responsive to identifying the preceding snapshot, the computer hardens changes occurring after the preceding snapshot. The computer then switches from a first indirection table to a second indirection table. | 07-10-2014 |
20140195721 | INSTANTANEOUS SAVE/RESTORE OF VIRTUAL MACHINES WITH PERSISTENT MEMORY - A computer implemented method creates a snapshot of a logical volume of a computer. The computer stores a system state of the computer in persistent memory. The computer flushes a cash of the computer. The computer identifies a preceding snapshot. Responsive to identifying the preceding snapshot, the computer hardens changes occurring after the preceding snapshot. The computer then switches from a first indirection table to a second indirection table. | 07-10-2014 |
20140195765 | IMPLEMENTING USER MODE FOREIGN DEVICE ATTACHMENT TO MEMORY CHANNEL - A method, system and computer program product are provided for implementing attachment of a user mode foreign device to a memory channel in a computer system. A user mode foreign device is attached to the memory channel using memory mapping of device registers and device buffers to the processor address space. The storage capacity on the device is doubly mapped in the address space creating separate control and data address spaces to allow user mode processes to control the device therefore eliminating the need for software system calls. A processor Memory Management Unit (MMU) coordinates multiple user processes accessing the device registers and buffers providing address space protection of each of interfaces, shifting device protection to the processor MMU from system software. | 07-10-2014 |
20140208315 | LIVE VIRTUAL MACHINE MIGRATION QUALITY OF SERVICE - A system and method for providing quality of service during live migration includes determining one or more quality of service (QoS) specifications for one or more virtual machines (VMs) to be live migrated. Based on the one or more QoS specifications, a QoS is applied to a live migration of the one or more VMs by controlling resources including at least one of live migration network characteristics and VM execution parameters. | 07-24-2014 |
20140208329 | LIVE VIRTUAL MACHINE MIGRATION QUALITY OF SERVICE - A system and method for providing quality of service during live migration includes determining one or more quality of service (QoS) specifications for one or more virtual machines (VMs) to be live migrated. Based on the one or more QoS specifications, a QoS is applied to a live migration of the one or more VMs by controlling resources including at least one of live migration network characteristics and VM execution parameters. | 07-24-2014 |
20140289468 | LIGHTWEIGHT PRIMARY CACHE REPLACEMENT SCHEME USING ASSOCIATED CACHE - One aspect provides a method including: responsive to a request for data and a miss in both a first cache and a second cache, retrieving the data from memory, the first cache storing at least a subset of data stored in the second cache; inferring from information pertaining to the first cache a replacement entry in the second cache; and responsive to inferring from information pertaining to the first cache a replacement entry in the second cache, replacing an entry in the second cache with the data from memory. Other aspects are described and claimed. | 09-25-2014 |
20140289477 | LIGHTWEIGHT PRIMARY CACHE REPLACEMENT SCHEME USING ASSOCIATED CACHE - One aspect provides an apparatus including: at least one processor; and a computer readable storage medium having computer readable program code embodied therewith and executable by the at least one processor, the computer readable program code including: computer readable program code configured to, responsive to a request for data and a miss in both a first cache and a second cache, retrieve the data from memory, the first cache storing at least a subset of data stored in the second cache; computer readable program code configured to infer from information available from the first cache a replacement entry in the second cache; and computer readable program code configured to, responsive to inferring from information available from the first cache a replacement entry in the second cache, replace an entry in the second cache with the data from memory. Other aspects are described and claimed. | 09-25-2014 |