Chen-Shien
Chen-Shien Chen, Hsinchu County TW
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20110068465 | STRONG INTERCONNECTION POST GEOMETRY - A flip-chip packaging assembly and integrated circuit device are disclosed. An exemplary flip-chip packaging assembly includes a first substrate; a second substrate; and joint structures disposed between the first substrate and the second substrate. Each joint structure comprises an interconnect post between the first substrate and the second substrate and a joint solder between the interconnect post and the second substrate, wherein the interconnect post exhibits a width and a first height. A pitch defines a distance between each joint structure. The first height is less than half the pitch. | 03-24-2011 |
20140042152 | VARIABLE FREQUENCY MICROWAVE DEVICE AND METHOD FOR RECTIFYING WAFER WARPAGE - A variable frequency microwave (VFM) device and a method for rectifying wafer warpage are provided. The variable frequency microwave (VFM) device includes a heater installed in the top wall of the chamber; and a cooler installed in proximity to the bottom wall of the chamber. | 02-13-2014 |
20150243620 | SUBSTRATE AND PACKAGE STRUCTURE - According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area. | 08-27-2015 |
Chen-Shien Chen, Hsinchu TW
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20110042827 | BONDING STRUCTURES AND METHODS OF FORMING BONDING STRUCTURES - A semiconductor structure includes a first substrate and a second substrate bonded over the first substrate. The first substrate includes a passivation layer formed over the first substrate. The passivation layer includes at least one first opening exposing a first bonding pad formed over the first substrate. The second substrate includes at least one second opening aligned with and facing the first opening. | 02-24-2011 |
Chen-Shien Chen, Shin Chu TW
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20090188104 | Method of Manufacturing a Coil Inductor - A method of manufacturing a coil inductor and a coil inductor are provided are provided. A plurality of conductive bottom structures are formed to be lying on a first dielectric layer. A plurality pairs of conductive side structures are then formed, wherein each pair of the conductive side structure stand on top surface of a first end and a second end of each conductive bottom structure respectively; a second dielectric layer is formed on the first dielectric layer, coating the bottom and side structures; and a plurality of conductive top structures are formed to be lying on the second dielectric layer, wherein each conductive top structure electrically connects each pair of the conductive side structures, wherein the conductive bottom structures, the conductive side structures and the conductive top structures together form a conductive coil structure. | 07-30-2009 |
Chen-Shien Chen, Zhuebi City TW
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20090160061 | Introducing a Metal Layer Between Sin and Tin to Improve CBD Contact Resistance for P-TSV - The present disclosure provide an integrated circuit. The integrated circuit includes a through-silicon-via (TSV) trench configured in a semiconductor substrate; a conductive pad formed on the semiconductor substrate, the conductive pad being adjacent the TSV trench; a silicon nitride layer disposed over the conductive pad and in the TSV trench; a titanium layer disposed on the silicon nitride layer; a titanium nitride layer disposed on the titanium layer; and a copper layer disposed on the titanium nitride layer. | 06-25-2009 |
Chen-Shien Chen, Zhubel City TW
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20090155957 | Multi-Die Wafer Level Packaging - A semiconductor die package is provided. The semiconductor die package includes a plurality of dies arranged in a stacked configuration. Through-silicon vias are formed in the lower or intermediate dies to allow electrical connections to dies stacked above. The lower die is positioned face up and has redistribution lines electrically coupling underlying semiconductor components to the through-silicon vias. The dies stacked above the lower die may be oriented face up such that the contact pads are facing away from the lower die or flipped such that the contact pads are facing the lower die. The stacked dies may be electrically coupled to the redistribution lines via wire bonding or solder balls. Additionally, the lower die may have another set of redistribution lines on an opposing side from the stacked dies to reroute the vias to a different pin-out configuration. | 06-18-2009 |
Chen-Shien Chen, Zhubei TW
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20090102021 | Through-Silicon Vias and Methods for Forming the Same - An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a substrate; a through-silicon via (TSV) extending into the substrate; a TSV pad spaced apart from the TSV; and a metal line over, and electrically connecting, the TSV and the TSV pad. | 04-23-2009 |
Chen-Shien Chen, Hsinchu City TW
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20080197473 | CHIP HOLDER WITH WAFER LEVEL REDISTRIBUTION LAYER - A chip holder formed of silicon, glass, other ceramics or other suitable materials includes a plurality of recesses for retaining semiconductor chips. The bond pads of the semiconductor chip are formed on or over an area of the chip holder that surrounds the semiconductor chip thus expanding the bonding area. The bond pads are coupled, using semiconductor wafer processing techniques, to internal bond pads formed directly on the semiconductor chip. | 08-21-2008 |
Chen-Shien Chen, Hsin-Chu TW
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20150357301 | Bump Structure and Method of Forming Same - An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent. | 12-10-2015 |