Patent application number | Description | Published |
20080256503 | POWER MANAGEMENT ARCHITECTURE AND METHOD OF MODULATING OSCILLATOR FREQUENCY BASED ON VOLTAGE SUPPLY - A method and system for modulating logic clock oscillator frequency based on voltage supply. The system comprises a logic unit having a logic operation and a device to produce self-adjusting clocks to match the logic operation. The device is configured to use supply voltage as an independent variable to optimize device parameters for voltage variations. The invention is also directed to a design structure on which a circuit resides. | 10-16-2008 |
20080285338 | DETERMINING HISTORY STATE OF DATA IN DATA RETAINING DEVICE BASED ON STATE OF PARTIALLY DEPLETED SILICON-ON-INSULATOR - A system, method and program product for determining a history state of data in a data retaining device are disclosed. A state of a partially-depleted silicon-on-insulator (PD SOI) device coupled to a data retaining device is measured to indicate a body voltage of the PD SOI device. The body voltage of the PD SOI device may indicate, among others, how long the PD SOI device has been idling, which indirectly indicates how long data in the data retaining device has not been accessed. As such, the current invention may be used efficiently with, e.g., a cache replacement algorithm in a management of the data retaining device. | 11-20-2008 |
20080290896 | System and Method for Dynamically Executing a Function in a Programmable Logic Array - A reconfigurable logic array (RLA) system that includes an RLA and a programmer for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks. The programmer contains software that partitions the RLA into a function region FR located between two storage regions SR | 11-27-2008 |
20090024859 | STRUCTURE AND METHOD TO OPTIMIZE COMPUTATIONAL EFFICIENCY IN LOW-POWER ENVIRONMENTS - A method and structure to optimize computational efficiency in a low-power environment. A design structure is embodied in a machine readable medium used in a design process. The design structure includes a component to determine an optimal point for maximizing computational efficiency in a low-power environment, and a component to selectively control operation of at least one processing unit of a plurality of processing units in accordance with the determined optimal point. The design structure further includes at least one of a component for controlling a frequency of a clock signal transmitted to the at least one processing unit in accordance with the determined optimal point, and a component for determining a present power available. | 01-22-2009 |
20090024862 | STRUCTURE AND METHOD TO OPTIMIZE COMPUTATIONAL EFFICIENCY IN LOW-POWER ENVIRONMENTS - A method and structure to optimize computational efficiency in a low-power environment. The method includes determining an optimal point for maximizing computational efficiency in a low-power environment, and selectively controlling operation of at least one processing unit of a plurality of processing units in accordance with the determined optimal point. The structure includes a plurality of processing units, a load manager controlling selective parallel operation of at least one processing unit of the plurality of processing units, and an unregulated power source. | 01-22-2009 |
20090045839 | ASIC LOGIC LIBRARY OF FLEXIBLE LOGIC BLOCKS AND METHOD TO ENABLE ENGINEERING CHANGE - A chip design methodology and an integrated circuit chip. The methodology includes providing a plurality of logic gates in a net list, wherein each of the logic gates comprises at least one spare input, synthesizing the net list, and connecting the spare inputs for performing an engineering change late in the design process. The invention is also directed to a design structure on which a circuit resides. | 02-19-2009 |
20090109741 | DETERMINING HISTORY STATE OF DATA IN DATA RETAINING DEVICE BASED ON STATE OF PARTIALLY DEPLETED SILICON-ON-INSULATOR - An integrated circuit and a design structure are disclosed. An integrated circuit may comprise: a data retaining device; a partially depleted silicon-on-insulator (PD SOI) device electrically coupled to the data retaining device; and a measurement device coupled to the PD SOI device for measuring a state of the PD SOI device indicating a body voltage thereof, the measuring device being communicatively coupled to a calculating means which determines a history state of a data in the data retaining device based on the measured state of the PD SOI device. | 04-30-2009 |
20090109781 | DETERMINING RELATIVE AMOUNT OF USAGE OF DATA RETAINING DEVICE BASED ON POTENTIAL OF CHARGE STORING DEVICE - An integrated circuit and a design structure are disclosed. An integrated circuit may comprise: a data retaining device; a charge storing device coupled to the data retaining device such that a use of the data retaining device triggers a charging of the charge storing device by a charge source; and means for measuring a potential of the charge storing device, the measuring means being communicatively coupled to a calculating mean which determines a relative amount of usage of the data retaining device based on the measured potential. | 04-30-2009 |
20090125744 | Structure for a System and Method of Predicting Power Events in an Intermittent Power Environment and Dispatching Computational Operations of an Integrated Circuit Accordingly - A design structure for a system and method of predicting power events in intermittent power environments and dispatching computational operations of an integrated circuit accordingly. A power management prediction system includes a controller executing a prediction algorithm, an arrangement of computation circuitry, a non-volatile storage device containing a power requirements log and a power history log, a clock generator, an intermittent power source, and a power monitor circuit. A method of predicting intermittent power events and dispatching computational operations includes: storing power requirements of each computational operation, monitoring the intermittent power source to generate a history log, predicting a subsequent power event based on the history log, retrieving actual power requirements of one or more computational operations, comparing the predicted power event with actual power requirements, determining whether actual power requirements are satisfied, dispatching one or more computational operations that correspond to one or more actual power events, or performing an error recovery operation. | 05-14-2009 |
20090132732 | UNIVERSAL PERIPHERAL PROCESSOR SYSTEM FOR SOC ENVIRONMENTS ON AN INTEGRATED CIRCUIT - A universal peripheral processor architecture on an integrated circuit (IC) includes first and second data buses coupled to interface logic devices for enabling communication between the first and second data buses including enabling interface of multiple signaling protocols. One or more processors communicate with the first and second data buses to manage control functions on the IC. A data path enables transfer of data between the first and second data buses, and communicates with data storage devices. A data control path enables communication between the data storage devices and the processors. | 05-21-2009 |
20090132747 | STRUCTURE FOR UNIVERSAL PERIPHERAL PROCESSOR SYSTEM FOR SOC ENVIRONMENTS ON AN INTEGRATED CIRCUIT - A design structure including universal peripheral processor architecture on an integrated circuit (IC) includes first and second data buses coupled to interface logic devices for enabling communication between the first and second data buses including enabling interface of multiple signaling protocols. One or more processors communicate with the first and second data buses to manage control functions on the IC. A data path enables transfer of data between the first and second data buses, and communicates with data storage devices. A data control path enables communication between the data storage devices and the processors. | 05-21-2009 |
20090183134 | DESIGN STRUCTURE FOR IDENTIFYING AND IMPLEMENTING FLEXIBLE LOGIC BLOCK LOGIC FOR EASY ENGINEERING CHANGES - A design structure for identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB). The design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. | 07-16-2009 |
20090183135 | Method and Device for Identifying and Implementing Flexible Logic Block Logic for Easy Engineering Changes - A chip design methodology. The methodology includes identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB). | 07-16-2009 |
20090268541 | DESIGN STRUCTURE FOR ESTIMATING AND/OR PREDICTING POWER CYCLE LENGTH, METHOD OF ESTIMATING AND/OR PREDICTING POWER CYCLE LENGTH AND CIRCUIT THEREOF - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a threshold register having a counter, a count register, and a non-volatile storage for storing a state when a value of the count register equals or exceeds a value of the threshold register. Also provided is a method of predicting and/or estimating a power cycle duration in order to save a state in non-volatile memory and a circuit. The method includes setting a threshold value; determining that the threshold value has been equaled or exceeded; and saving the state in the non-volatile memory at a first checkpoint based on the threshold value being equaled or exceeded. | 10-29-2009 |
20090287905 | PROCESSOR PIPELINE ARCHITECTURE LOGIC STATE RETENTION SYSTEMS AND METHODS - A solution for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of the two stages. A reference logic is provided, which has the same value as the output of the early stage. A logic storing and dividing device is coupled between the reference logic and a reference node of the comparator to generate a logic at the reference node, which is a fraction of the reference logic, and to retain a logic state of the information stored on the storage capacitor. Further mechanisms are provided to determine validity of data stored in the logic storing and dividing device. | 11-19-2009 |
20100017773 | Method for Minimizing Impact of Design Changes For Integrated Circuit Designs - A method is provided for updating an existing netlist to reflect a design change. A design incorporating the design change and the existing netlist are provided to a synthesis tool. The design and the existing netlist are processed with the synthesis tool reusing logic structures from the existing netlist. A result is generated by the synthesis tool including the existing netlist and a new portion of a netlist reflecting the design change. | 01-21-2010 |
20100039150 | METHOD, CIRCUIT, AND DESIGN STRUCTURE FOR CAPTURING DATA ACROSS A PSEUDO-SYNCHRONOUS INTERFACE - A method for source synchronous communication. The method includes dynamically adjusting a delay that is applied to a data signal and a remote clock signal until a delayed remote clock signal is synchronized with a local clock signal, and capturing data from a delayed data signal associated with the delay in a local domain. | 02-18-2010 |
20100040183 | METHOD, CIRCUIT, AND DESIGN STRUCTURE FOR CAPTURING DATA ACROSS A PSEUDO-SYNCHRONOUS INTERFACE - A structure for performing cross-chip communication with mesochronous clocks. The structure includes: a data delay line; a remote clock delay line; a structure that captures at least one value of a state of a delayed remote clock signal on the remote clock delay line; and a control that influences a delay associated with the data delay line and the remote clock delay line. | 02-18-2010 |
20100231306 | POWER MANAGEMENT ARCHITECTURE AND METHOD OF MODULATING OSCILLATOR FREQUENCY BASED ON VOLTAGE SUPPLY - A method and system for modulating logic clock oscillator frequency based on voltage supply. The system comprises a logic unit having a logic operation and a device to produce self-adjusting clocks to match the logic operation. The device is configured to use supply voltage as an independent variable to optimize device parameters for voltage variations. The invention is also directed to a design structure on which a circuit resides. | 09-16-2010 |
20100333058 | METHOD FOR INCREASING THE MANUFACTURING YIELD OF PROGRAMMABLE LOGIC DEVICES - A method for increasing the manufacturing yield of field programmable gate arrays (FPGAs) or other programmable logic devices (PLDs). An FPGA or other PLD is formed in several sections, each of the sections having its own power bus and input/output connections. Each section of the FPGA or other PLD is tested to identify defects in the FPGA or other PLD. The FPGA or other PLD is sorted according to whether the section has an acceptable number of defects. An assigned unique number for the FPGA or other PLD chip or part identifies it as partially good. Software for execution and configuring the FPGA or other PLD may use the unique number for programming only the identified functional sections of the FPGA or other PLD. The result is an increase in yield as partially good FPGAs or other PLDs may still be utilized. | 12-30-2010 |
20120083913 | SEMICONDUCTOR LAYER FORMING METHOD AND STRUCTURE - A method of forming and electrical structure. The method includes determining that a first semiconductor device requires an engineering change order (ECO). An additional structure layer required to implement the ECO is determined. A first insertion point location for inserting the additional structure layer within the first semiconductor device is selected. The first insertion point location is associated with a second insertion point location within a design for a second semiconductor device. The second semiconductor device is generated in accordance with the first ECO. The second semiconductor device comprises second structures. The second structures comprise same structures as first structures in the first semiconductor device. The second structures are formed in locations within the second semiconductor device that are associated with locations in the first semiconductor device comprising the first structures. The second semiconductor device comprises the additional structure layer located within the second insertion point location. | 04-05-2012 |
20120167022 | METHOD AND DEVICE FOR IDENTIFYING AND IMPLEMENTING FLEXIBLE LOGIC BLOCK LOGIC FOR EASY ENGINEERING CHANGES - A chip design methodology and an integrated circuit chip. The methodology includes identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB). | 06-28-2012 |
20130041608 | CRITICAL PATH DELAY PREDICTION - Embodiments of the invention provide a method, system, and program product for predicting a delay of a critical path. In one embodiment, the invention provides a method of predicting a delay of at least one critical path of an integrated circuit, the method comprising: determining a delay of at least one ring oscillator on the integrated circuit; and calculating a predicted delay for the at least one critical path delay based on a delay of components of the critical path at a corner condition, a wire delay of the at least one critical path, a delay of the at least one ring oscillator at a corner condition, and the determined delay of the at least one ring oscillator. | 02-14-2013 |
20130249596 | INACTIVITY TRIGGERED SELF CLOCKING LOGIC FAMILY - Localized logic regions of a circuit include a local comparator electrically connected to a local resistive voltage circuit, to a local resistive ground circuit, and to a local register structure. The local comparator supplies a clock pulse to the local register structures when the local reference voltage is below a local voltage threshold. Activity in the local combinatorial logic structure causes the local reference voltage to drop below the local reference voltage independently of changes in the global reference voltage causing the comparator to output the clock pulse (with sufficient delay to allow the logic results to be stored in the registers only after setup times have been met in the local logic devices). This eliminates the need for a clock distribution tree, thereby saving power when there is no activity in the local combinatorial logic structure. | 09-26-2013 |
20130259488 | REACTIVE METAL OPTICAL SECURITY DEVICE AND METHODS OF FABRICATION AND USE - A reactive metal optical security device for implementation in an optical network and/or system to provide a mechanism for disrupting the optical network and/or system. The security device includes a mirror comprising a reactive metal stack and configured to reflect an optical signal and receive an electrical signal. The security device further includes a semiconductor chip configured to send the electrical signal to the mirror. | 10-03-2013 |
20140028365 | RING OSCILLATOR - Aspects of the invention provide a circuit structure that automatically monitors a plurality of ring oscillators and dynamically selects the fastest or the slowest ring oscillator for feedback into the plurality of ring oscillators. In one embodiment, a circuit includes: a plurality of delay elements, each delay element associated with a ring oscillator; a first logic gate for receiving outputs of each of the delay elements; a second logic gate for receiving outputs of each of the delay elements; and a multiplexer for receiving an output of the first logic gate and an output of the second logic gate and choosing one of the outputs, wherein a selection for the multiplexer is based on an output of the multiplexer. To select the fastest ring oscillator, a second multiplexer is provided. | 01-30-2014 |
20140043757 | ELECTRO-RHEOLOGICAL MICRO-CHANNEL ANISOTROPIC COOLED INTEGRATED CIRCUITS AND METHODS THEREOF - An integrated circuit chip having micro-channels formed in multiple regions of the integrated circuit chip and a method of cooling the integrated circuit chip. The method includes for any region of the multiple regions, allowing a coolant to flow through micro-channels of the region only when a temperature of the region exceed a first specified temperature and blocking the coolant from flowing through the micro-channels of the region when a temperature of the region is below a second specified temperature. | 02-13-2014 |
20140074422 | ADAPTIVE POWER CONTROL USING TIMING CANONICALS - A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connected to the digital circuits, and a non-transitory storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-transitory storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data. | 03-13-2014 |
20140132290 | FLEXIBLE PERFORMANCE SCREEN RING OSCILLATOR WITHIN A SCAN CHAIN - Aspects of the invention provide for a flexible performance screen ring oscillator (PSRO) integrated within a scan chain. In one embodiment, a circuit structure to create the flexible PSRO includes: a plurality of programmable scan chain elements; and a forward test scan chain path through the plurality of scan chain elements; wherein each of the programmable scan chain elements includes additional circuitry for a backward path, such that the backward path and the forward test scan chain path are combined to create the PSRO. | 05-15-2014 |
20140195196 | CHIP PERFORMANCE MONITORING SYSTEM AND METHOD - Disclosed are a chip performance monitoring system, method and a computer program product, wherein a performance monitor output signal is propagated through an adjacent scan chain to avoid signal degradation incident to across-chip transmission of high frequency signals. Since the clock signal frequency used to control signal propagation through the scan chain will typically be less than twice the performance monitor output signal frequency, frequency sub-sampling with aliasing occurs. To compensate, signal propagation through the scan chain can be controlled during different time periods using different clock signals having different clock signal frequencies and, during these different time periods, different data outputs can be captured at an output node of the scan chain. The data output frequencies of these different data outputs can be measured and the performance monitor output signal frequency can be determined based on the different data output frequencies given the different clock signal frequencies. | 07-10-2014 |