Patent application number | Description | Published |
20080256403 | Soft error rate calculation method and program, integrated circuit design method and apparatus, and integrated circuit - A first mathematical expression indicating a dependence of SER on an information storage node diffusion layer area at the same information storage node voltage Vn is derived with a use of a result of measuring a relationship between SER and the information storage node diffusion layer area of a storage circuit or an information holding circuit composed of MISFET using a plurality of information storage node voltages Vn as a parameter. Then, a second mathematical expression is derived from the measurement result by substituting a relationship indicating a dependence of SER on an information storage node voltage at the same information storage node diffusion layer area Sc into the first mathematical expression. SER can be calculated by substituting a desired information storage node diffusion layer area and a desired information storage node voltage of a storage circuit or an information holding circuit into the second mathematical expression. | 10-16-2008 |
20090008721 | Semiconductor device - The semiconductor device includes first and second common source semiconductor layers respectively extending in a first direction, first and second logic gate circuits respectively composed of at least one three-dimensional P-type FET and a three-dimensional N-type FET. The sources of the three-dimensional P-type FETs in the first and second logic gate circuits are joined to the first common source semiconductor layer. The sources of the three-dimensional N-type FETs in the first and second logic gate circuits are joined to the second common source semiconductor layer. The semiconductor layers of the three-dimensional P-type and N-type FETs in the first logic gate circuit are joined in their drain side, and The semiconductor layers of the three-dimensional P-type and N-type FETs in the second logic gate circuit are joined in their drain side. The dissipation of the FinFET can be improved. | 01-08-2009 |
20090091964 | Semiconductor integrated circuit device including static random access memory having diffusion layers for supplying potential to well region - A static random access memory (SRAM) cell includes a first well region of a first conductivity type, a second well region of the first conductivity type, formed in a location different from a location where the first well region is formed, and a third well region of a second conductivity type, which is located between the first well region and the second well region. The memory cell further includes a first tap diffused layer of the first conductivity type for supplying a potential to the first well region, a second tap diffused layer of the first conductivity type for supplying the potential to the second well region, the first and second tap diffused layers being arranged substantially on a diagonal line in the layout of the SRAM cell, and a metal interconnection connected to the first and second tap diffused layers, the metal interconnection passing on the third well region in the SRAM cell. | 04-09-2009 |
20090152609 | Semiconductor integrated circuit device - A semiconductor integrated circuit device which is formed on an area comprises a first storage node which is formed on a first area having a first conductive type of the area, the first storage node having a first level, a second storage node which is formed on a second area having second conductive type of the area, the second storage node having a second level opposite to the first level and a well boundary which is sandwiched between the first area and the second area, wherein the second storage node has two diagonal lines, thereby, the first area having a first part sandwiched between the diagonal lines extended from the second storage node through the well boundary, and a second part which is the other part of the first part, wherein the first storage node is placed outside a region between the extended lines of two diagonal lines extending from the second storage node to the well boundary direction, and wherein the second storage node is placed outside a region between the extended lines of two diagonal lines extending from the first storage node to the well boundary direction. | 06-18-2009 |
20090289311 | Semiconductor integrated circuit including transistor having diffusion layer formed at outside of element isolation region for preventing soft error - A MISFET includes a drain diffusion layer of a first conductivity type, a source diffusion layer of the first conductivity type, a gate electrode, and a substrate/well of a second conductivity type. In the MISFET, first diffusion layers of the first conductivity type are provided at two or more positions at predetermined intervals with an isolation therebetween respectively. The two or more positions are facing at least two sides of the element isolation insulation around the drain diffusion layer. A second diffusion layer of the second conductivity type is provided so as to be close to or to come in contact with the source diffusion layer. | 11-26-2009 |
20100034039 | Semiconductor integrated circuit - A semiconductor integrated circuit has K (K is a natural number of 2 or more) number of memory cells coupled to a same word line, and multiple sense amplifier circuits coupled to the memory cells. The multiple sense amplifier circuits are divided into N (N is a natural number of 2 or more) number of groups. Among the N number of groups, after a first group of sense amplifier circuits is activated and carrying out a predetermined read-out operation, a second group of the sense amplifier circuits is activated and the predetermined read-out operation is carried out, and an Nth group of the sense amplifier circuits is activated sequentially to carry out the predetermined read-out operation. | 02-11-2010 |
20100034040 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit according to an exemplary embodiment of the present invention includes a plurality of memory cells connected to one word line; a plurality of sense amplifier circuits that are connected to the memory cells and divided into an N number of groups; and N number of data inversion processing circuits that respectively receive data read out from the N number of groups of sense amplifier circuits, in which after a sense amplifier circuit of a first group terminates operation, a sense amplifier circuit of a second group different from the first group operates, and each of the data inversion processing circuits performs data inversion processing based on the data read out from each of the groups of sense amplifier circuits, and outputs the data to an output terminal of each of the data inversion processing circuits. | 02-11-2010 |
20100110814 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE OPERATION METHOD - Provided is a destructive readout semiconductor memory device capable of avoiding concentration of a writeback current, in which a switch circuit ( | 05-06-2010 |
20100213520 | Semiconductor integrated circuit device and method of manufacturing the same - Provided is a semiconductor integrated circuit device including a capacitor element with an improved TDDB life. A semiconductor integrated circuit device ( | 08-26-2010 |
20100252911 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes a power supply line connected to a power supply terminal, a ground line connected to a ground terminal and a plurality of capacitors connected in parallel between the power supply line and the ground line. The plurality of capacitors include a first capacitor arranged at a first distance from one of the terminals and a second capacitor arranged at a second distance which is larger than the first distance from the one of the terminals, and the first capacitor has a larger area than the second capacitor. | 10-07-2010 |
20100320539 | Semiconductor device with electrostatic protection device - A semiconductor device has an SOI (Silicon On Insulator) structure and comprising a P-channel FET and an N-channel FET which are formed on an insulating film. The semiconductor device includes: at least two of first, second, third and fourth PN-junction elements. The first PN-junction element is formed from a P-type semiconductor layer and an N-type semiconductor layer having the same impurity concentrations as those of source/drain regions of the P-channel FET and the N-channel FET, respectively. The second PN-junction element is formed from a P-type semiconductor layer and an N-type semiconductor layer having the same impurity concentrations as those of the source/drain region and a channel region in the P-channel FET, respectively. The third PN-junction element is formed from a P-type semiconductor layer and an N-type semiconductor layer having the same impurity concentrations as those of a channel region and the source/drain region in the N-channel FET, respectively. The fourth PN-junction element is formed from a P-type semiconductor layer and an N-type semiconductor layer having the same impurity concentrations as those of the channel regions of the N-channel FET and the P-channel FET, respectively. At least two PN-junction elements are connected in series in a forward bias between two different terminals to form an electrostatic protection device. | 12-23-2010 |
20110079834 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device has: a MISFET having source/drain diffusion layers; first plugs respectively connected to the source/drain diffusion layers; a first interconnection connected to one of the source/drain diffusion layers through the first plug; a second plug electrically connected to the other Of the source/drain diffusion layers through the first plug; a second interconnection connected to the second plug; and a capacitor electrode located above a gate electrode of the MISFET. The first interconnection is formed not above the lower capacitor electrode, while the second interconnection is formed above the upper capacitor electrode. A plug connecting the first interconnection and another interconnection is not provided at an upper location of the one of the source/drain diffusion layers. The first interconnection is not provided at an upper location of the other of the source/drain diffusion layers. | 04-07-2011 |
20110175197 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes: a plurality of data holding circuits; and a plurality of wells. The plurality of data holding circuits is provided in a substrate of a first conductive type. Each of the plurality of data holding circuits includes a first well of the first conductive type and a second well of a second conductive type different from the first conductive type. The plurality of wells is arranged in two directions for the each of the plurality of data holding circuits. | 07-21-2011 |
20110199140 | Semiconductor device - Disclosed is a semiconductor device including a mode control circuit that, when a standby control signal is in an activated state, based on a timer output signal from a timer circuit, generates a MODE control output signal that changes a logic state of a functional circuit part at every prescribed time interval, and an output control circuit that receives an output signal of the functional circuit part and controls output of the output signal; based on a delay output signal generated by delaying a MODE control output signal by a delay circuit. While the functional circuit part is changing the logic state by the MODE control output signal, the output control circuit does not transfer the functional circuit part output signal to output, but holds and outputs a functional circuit part output signal immediately before the functional circuit part changes the logic state by the MODE control output signal. | 08-18-2011 |
20110316052 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In addition to a memory macro region and functional circuit regions on a substrate, a semiconductor integrated circuit device includes a dummy pattern region | 12-29-2011 |
20120153370 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor integrated circuit device, includes a first electrode including a first semiconductor layer formed on a substrate, a side surface insulating film formed on at least a part of a side surface of the first electrode, an upper surface insulating film formed on the first electrode and the side surface insulating film, a second electrode which covers the side surface insulating film and the upper surface insulating film, and a fin-type field effect transistor. The first electrode, the side surface insulating film, and the second electrode constitute a capacitor element. A thickness of the upper surface insulating film between the first electrode and the second electrode is larger than a thickness of the side surface insulating film between the first electrode and the second electrode, and the fin-type field effect transistor includes a second semiconductor layer which protrudes with respect to the plane of the substrate. | 06-21-2012 |
20120228737 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes a power supply line connected to a power supply terminal, a ground line connected to a ground terminal and a plurality of capacitors connected in parallel between the power supply line and the ground line. The plurality of capacitors include a first capacitor arranged at a first distance from one of the terminals and a second capacitor arranged at a second distance which is larger than the first distance from the one of the terminals, and the first capacitor has a larger area than the second capacitor. | 09-13-2012 |
20120241860 | SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING TRANSISTOR HAVING DIFFUSION LAYER FORMED AT OUTSIDE OF ELEMENT ISOLATION REGION FOR PREVENTING SOFT ERROR - A semiconductor integrated circuit device includes a gate electrode of at least one of a P-channel MISFET (metal-insulator-semiconductor field-effect transistor) and an N-channel MISFET provided in a direction parallel to a direction of a well isolation boundary phase between the P-channel MISFET and the N-channel MISFET, a first diffusion layer having a same conductivity type as that of a drain diffusion layer of one of a plurality of ones of the MISFET provided in two regions with a drain diffusion layer of the MISFET therebetween through an isolation respectively in a direction orthogonal to the gate electrode, and a second diffusion layer having a conductivity type different from that of the drain diffusion layer of the one of the plurality of ones of the MISFET provided between the well isolation boundary phase and one of a source diffusion layer and the drain diffusion layer. | 09-27-2012 |
20130033308 | SEMICONDUCTOR DEVICE - A semiconductor integrated circuit device includes a functional circuit part that includes a plurality of field effect transistors, a mode control circuit that receives a first control signal and that generates a second control signal that is used to change a logic state of the functional circuit part, an output control circuit that receives an output signal of the functional circuit part and controls output of the output signal, and a control circuit that receives the second control signal and that generates a third control signal to the output control circuit. During a time period when the functional circuit part changes a logic state according to the second control. signal, the output control circuit inverts the output signal of the functional circuit part according to the third control signal. | 02-07-2013 |
20130334582 | DRAM DEVICE - A DRAM device includes plural N-channel MIS transistors arranged in a matrix over a P well, and a plurality of capacitors formed corresponding to the plurality of N-channel MIS transistors, and plural word lines formed corresponding to each row of the plurality of N-channel MIS transistors, and a plurality of bit lines formed corresponding to each column of the plurality of N-channel MIS transistors, and a P | 12-19-2013 |