Choi, Icheon-Si
Chang Kyu Choi, Icheon-Si KR
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20120194215 | SEMICONDUCTOR APPARATUS AND IMPEDANCE CALIBRATION CIRCUIT FOR THE SAME - A semiconductor apparatus includes a data input/output circuit and an impedance calibration circuit. The impedance calibration circuit may be configured to output a code signal for controlling a resistance value of the data input/output circuit in response to a division voltage applied to a joining interconnection directly coupled to a ZQ pad and a preset reference voltage. | 08-02-2012 |
20120195153 | SEMICONDUCTOR SYSTEM AND SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes an odd data clock buffer group configured to maintain or shift a phase of a multi-phase source clock signal, and output a first multi-phase clock signal, an even data clock buffer group configured to maintain or shift a phase of the multi-phase source clock signal, and output a second multi-phase clock signal, an odd data output buffer group configured to drive odd data in response to the first multi-phase clock signal and output the driven data to an odd data pad group, and an even data output buffer group configured to drive even data in response to the second multi-phase clock signal and output the driven data to an even data pad group, wherein the phases of clock signals of the first and second multi-phase clock signal are different from each other. | 08-02-2012 |
20150042388 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes an enable signal generation unit configured to be inputted with a plurality of clocks which have different phases, and generate a plurality of enable signals; and a plurality of sampling units configured to output input data as sampling data in response to respective pairs of clocks of the plurality of clocks and respective ones of the plurality of enable signals. | 02-12-2015 |
Geun Min Choi, Icheon-Si KR
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20110212610 | METHODS OF FORMING DUAL GATE OF SEMICONDUCTOR DEVICE - Disclosed herein is a method for forming a dual gate of a semiconductor device. The method comprises the steps of forming a first polysilicon layer doped with p-type impurity ions and a second polysilicon layer doped with n-type impurity ions on a first region and a second region of a semiconductor substrate, respectively, and sequentially subjecting the surfaces of the first and second polysilicon layers to wet cleaning, drying, and dry cleaning. The wet cleaning is performed by using a sulfuric acid peroxide mixture (SPM), a buffered oxide etchant (BOE), and Standard Clean-1 (SC-1) as cleaning solutions. | 09-01-2011 |
20110212611 | METHODS OF FORMING DUAL GATE OF SEMICONDUCTOR DEVICE - Disclosed herein is a method for forming a dual gate of a semiconductor device. The method comprises the steps of forming a first polysilicon layer doped with p-type impurity ions and a second polysilicon layer doped with n-type impurity ions on a first region and a second region of a semiconductor substrate, respectively, and sequentially subjecting the surfaces of the first and second polysilicon layers to wet cleaning, drying, and dry cleaning. The wet cleaning is performed by using a sulfuric acid peroxide mixture (SPM), a buffered oxide etchant (BOE), and Standard Clean-1 (SC-1) as cleaning solutions. | 09-01-2011 |
Hae Rang Choi, Icheon-Si KR
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20110241726 | ON-DIE TERMINATION CIRCUIT - An on-die termination circuit includes a reference period signal generation circuit that generates a reference period signal according to a level of a reference voltage, a first period signal generation circuit that generates a first period signal according to a voltage level of a pad, a period comparison circuit that compares a period of the first period signal with a period of the reference period signal and count a plurality of driving signals, and a driver circuit that drives the pad in response to the plurality of driving signals. | 10-06-2011 |
20110267124 | CLOCK SIGNAL DUTY CORRECTION CIRCUIT - A clock signal duty correction circuit includes: a first transition timing control unit configured to generate a first control signal for controlling a rising timing of a duty correction clock signal by using a clock signal; a second transition timing control unit configured to generate a second control signal for varying a falling timing of the duty correction clock signal by using the clock signal according to a code signal; and a differential buffer unit configured to generate the duty correction clock signal, whose rising time or falling time is adjusted, in response to the first control signal and the second control signal. | 11-03-2011 |
20130041612 | INTERNAL CONTROL SIGNAL REGURATION CIRCUIT - An internal control signal regulation circuit includes a programming test unit configured to detect an internal control signal in response to an external control signal and generate a selection signal, test codes and a programming enable signal; and a code processing unit configured to receive the test codes or programming codes in response to the selection signal and regulate the internal control signal. | 02-14-2013 |
20130043901 | ON-DIE TERMINATION CIRCUIT - An on-die termination circuit includes a reference period signal generation circuit that generates a reference period signal according to a level of a reference voltage, a first period signal generation circuit that generates a first period signal according to a voltage level of a pad, a period comparison circuit that compares a period of the first period signal with a period of the reference period signal and count a plurality of driving signals, and a driver circuit that drives the pad in response to the plurality of driving signals. | 02-21-2013 |
20130342245 | RESET SIGNAL GENERATION APPARATUS - A reset signal generation apparatus includes a reset signal generation unit and a reset signal expansion unit. The reset signal generation unit enables a reset signal and an enable signal in response to a reset input signal, and disables the reset signal in response to a pulse width extension signal. The reset signal expansion unit generates the pulse width extension signal that is enabled for a predetermined time, in response to the enable signal. | 12-26-2013 |
20130342250 | DELAY CONTROL CIRCUIT AND CLOCK GENERATION CIRCUIT INCLUDING THE SAME - A clock generation circuit includes a delay line, which delays an input clock and generates a delayed clock, a delay modeling unit, which delays the delayed clock by a modeled delay value and generates a feedback clock, a phase detection unit, which compares phases of the input clock and the feedback clock and generates a phase detection signal, a filter unit, which receives the phase detection signal and generates phase information, generates an update signal when a difference between the numbers of phase detection signals with a first and a second level generated is greater than or equal to a threshold value, and generates the update signal after a lapse of a predetermined time when the difference is less than the threshold value, and a delay line control unit, which sets a delay value of the delay line in response to the update signal and the phase information. | 12-26-2013 |
20140002149 | CLOCK GENERATION CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME | 01-02-2014 |
20140002154 | DELAY CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME | 01-02-2014 |
Hong Sok Choi, Icheon-Si KR
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20120005397 | SENSE AMPLIFIER AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME - A sense amplifier is configured to transfer data on a first data I/O line to a second data I/O line or to transfer data on the second data I/O line to the first data I/O line. The first data I/O line is substantially continuously coupled to the second data I/O line during an active operation. | 01-05-2012 |
Hye-Jung Choi, Icheon-Si KR
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20140291601 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME, AND MICROPROCESSOR, PROCESSOR, SYSTEM, DATA STORAGE SYSTEM AND MEMORY SYSTEM INCLUDING THE SEMICONDUCTOR DEVICE - A semiconductor device includes first lines extending in a first direction; second lines extending in a second direction crossing with the first direction; and first resistance variable elements defined between the first lines and the second lines and each including a first substance layer and a second substance layer, wherein the first substance layer extends in the first direction and the second substance layer extends in the second direction. | 10-02-2014 |
Ik Soo Choi, Icheon-Si KR
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20090269924 | Method for Forming Fine Pattern by Spacer Patterning Technology - In a method for forming a fine pattern, a target layer to be patterned is formed on a semiconductor substrate and a polysilicon layer is formed on the target layer. A partition is then formed on the polysilicon layer with an amorphous carbon layer pattern. A spacer is attached to a sidewall of the partition. Thereafter, the spacer is divided into bar patterns by selectively removing the partition. A polysilicon layer pattern is formed by selectively etching a portion of the poly silicon layer exposed by the divided bar patterns and then a target layer pattern is formed by selectively etching a portion of the target layer exposed by the polysilicon layer pattern. | 10-29-2009 |
Jae Seung Choi, Icheon-Si KR
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20080295059 | Method for Correcting Optical Proximity Effect - A method of correcting an optical proximity effect may include the steps of: fabricating a test mask having test patterns; projecting patterns on a wafer using the test mask; measuring line widths of the patterns formed on the wafer; and executing a model calibration using the measured line widths and writing a correction recipe. The entire area of the wafer chip may be divided into a plurality of templates. An optical proximity correction may be executed on one of the templates and it may be verified that the optical proximity correction was executed properly on another template. The data for the templates that pass a verification may be merged and final data may be written using the merged data. A photomask may be fabricated using the final data. | 11-27-2008 |
20090170318 | METHOD FOR FORMING PATTERN OF SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device comprises performing a CMP process using an oxide film as an etching barrier film to maintain a polysilicon layer having a large open area. A word line pattern, a DSL pattern, and a SSL pattern that are formed by a first patterning process are not additionally blocked, and the oxide film is used as an etching barrier to obtain an accurate overlay between patterns and improve CD uniformity, thereby improving a characteristic of the device. | 07-02-2009 |
20100209825 | EXPOSURE MASK AND METHOD FOR FORMING SEMICONDUCTOR DEVICE BY USING THE SAME - The present invention is the thing about exposure mask and manufacturing method of semiconductor device using the same | 08-19-2010 |
20120100469 | EXPOSURE MASK AND METHOD FOR FORMING SEMICONDUCTOR DEVICE BY USING THE SAME - The present invention is the thing about exposure mask and manufacturing method of semiconductor device using the same | 04-26-2012 |
Joong Il Choi, Icheon-Si KR
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20080261373 | Method of fabricating semconductor device - A method of fabricating a semiconductor device includes forming a buffer insulating film over a semiconductor substrate including a conductive pattern. The buffer insulating film is etched using a storage node mask to form a buffer insulating pattern exposing the conductive pattern. The buffer insulating pattern defines a region wider than a storage node region. An etch stop film is formed over the conductive pattern and the buffer insulating pattern. An interlayer insulating film is formed over the etch stop film. The interlayer insulating film is etched using the storage node mask to expose the etch stop film. The exposed etch stop film is etched to form the storage node region exposing conductive pattern. A lower storage node is formed over the storage node region. | 10-23-2008 |
20100258906 | CAPACITOR OF SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device includes forming a buffer insulating film over a semiconductor substrate including a conductive pattern. The buffer insulating film is etched using a storage node mask to form a buffer insulating pattern exposing the conductive pattern. The buffer insulating pattern defines a region wider than a storage node region. An etch stop film is formed over the conductive pattern and the buffer insulating pattern. An interlayer insulating film is formed over the etch stop film. The interlayer insulating film is etched using the storage node mask to expose the etch stop film. The exposed etch stop film is etched to form the storage node region exposing conductive pattern. A lower storage node is formed over the storage node region. | 10-14-2010 |
Kang Sik Choi, Icheon-Si KR
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20100276739 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The semiconductor device includes a device isolation structure formed in a semiconductor substrate to define an active region, a bridge type channel structure formed in the active region, and a coaxial type gate electrode surrounding the bridge type channel structure of a gate region. The bridge type channel structure is separated from the semiconductor substrate thereunder by a predetermined distance in a vertical direction. | 11-04-2010 |
20110057261 | SEMICONDUCTOR DEVICE HAVING RECESS CHANNEL STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having a recess channel structure includes a semiconductor substrate having a recess formed in a gate forming area in an active area; an insulation layer formed in the semiconductor substrate so as to define the active area and formed so as to apply a tensile stress in a channel width direction; a stressor formed in a surface of the insulation layer and formed so as to apply a compressive stress in a channel height direction; a gate formed over the recess in the active area; and source/drain areas formed in a surface of the active area at both side of the gate. | 03-10-2011 |
20130153847 | RESISTIVE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A resistive memory device capable of improving an integration density is provided. The resistive memory device includes a semiconductor substrate, a plurality of resistive memory cells configured to be stacked on the semiconductor substrate and insulated from one another, where each of the plurality of resistive memory cells includes a switching transistor and a resistive device layer electrically connected to the switching transistor, a common source line electrically connected to the plurality of stacked resistive memory cells, and a bit line electrically connected to the plurality of stacked resistive memory cells and being insulated from the common source line. | 06-20-2013 |
20130153848 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device comprising a bit line extending in a first direction, a vertical gate cell including a gate oxide layer and a gate metal layer that are formed in a pillar shape, a lower electrode and a data storage material layer formed on the vertical gate cell, and an interconnection layer formed on the data storage material layer. | 06-20-2013 |
20130241000 | HIGH-INTEGRATION SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes a semiconductor substrate, an active region including a plurality of unit active regions and disposed over and spaced from the semiconductor substrate, a pair of word lines formed on a top surface and sides of the unit active region, a dummy word line disposed at a contact of the unit active regions and formed on top surfaces and sides of the unit active regions, a source region in the unit active region between the pair of word lines and electrically connected to the semiconductor substrate, drain regions formed in the unit active region between the pair of word lines and the dummy word line, and first storage layers formed on the drain regions and electrically connected to the drain regions. | 09-19-2013 |
20130313511 | MEMORY CELL ARRAY AND VARIABLE RESISTIVE MEMORY DEVICE INCLUDING THE SAME - A memory cell array and a resistive variable memory device including the memory cell array are provided. The memory cell array includes a memory group. The memory cell array includes a pair of word lines, an inter-pattern insulating layer interposed between the pair of word lines, and a plurality of active pillars, each having one side contacted with the inter-pattern insulating layer and other sides surrounded by the word line. | 11-28-2013 |
Seok Hwan Choi, Icheon-Si KR
Seong Sik Choi, Icheon-Si KR
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20120082324 | VIBRATION EARPHONE - The present invention relates to a vibration earphone that improves the efficiency of sound output from the earphone by outputting vibrations for the high sound frequency range through a mastoid and by simultaneously outputting vibrations for the low frequency range through a cylindrical low sound transmitting member. The vibration earphone comprises a vibration member for outputting sound through vibrations and including a face plate, a voice coil, a basket with a magnet coupled thereto, and a cover; the low sound transmitting member housing the vibration member therein, for outputting vibrations for low sound through an external wall inside an ear; and a mastoid for outputting vibrations for the high sound frequency range generated from the face plate through a projection passing through the low sound transmitting member and inserted in and coupled to a hole defined in a central portion of the face plate of the vibration member. | 04-05-2012 |
Shin-Gyu Choi, Icheon-Si KR
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20100055866 | METHOD OF FORMING TRANSISTOR IN SEMICONDUCTOR DEVICE - A method of forming a transistor in a semiconductor device includes forming device isolation structures in a substrate to define an active region. An oxide-based layer and a nitride-based layer are then formed between the active region and the device isolation structures. A predetermined gate region is etched in the active region to form a recess region. The damage layers are formed by a tilted ion implantation process using neutral elements on portions of the oxide-based layer exposed at the sidewalls of the recess region and other portions of the oxide-based layer below the recess region. The damage layers are then removed, thus causing a portion of the active region exposed at the bottom of the recess region to protrude. | 03-04-2010 |
Soo Young Choi, Icheon-Si KR
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20110037931 | Fringe-Field-Switching-Mode Liquid Crystal Display and Method of Manufacturing the Same - Provided are a fringe-field-switching (FFS)-mode liquid crystal display (LCD) and a method of manufacturing the same. The FFS-mode LCD includes a transparent common electrode, a conductive reflection structure electrically connected to the transparent common electrode, and a transparent pixel electrode formed on the conductive reflection structure and including a plurality of slits. The transparent common electrode is formed on a region including a data line and a gate line so that respective unit pixel regions can be electrically connected to one another. | 02-17-2011 |
20110109861 | Fringe Field Switching Mode Liquid Crystal Display Device and Method of Fabricating the Same - Provided is a liquid crystal display including a transparent pixel electrode and a transparent common electrode in a pixel region to drive liquid crystals. The transparent common electrode includes a plurality of slits and is configured to open at least a portion of a switching device to connect unit pixels, the slits have an angle of 5 to 10° with respect to a gate line, and a rubbing direction of a liquid crystal layer is substantially parallel to a gate direction. Therefore, it is possible to provide the liquid crystal display capable of removing factors decreasing an aperture ratio, preventing light from leaking, and further improving internal reflection. | 05-12-2011 |
Suk Choi, Icheon-Si KR
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20110244751 | FRINGE FIELD SWITCHING MODE LIQUID CRYSTAL DISPLAY AND MANUFACTURING METHOD THEREOF - Provided is a fringe field switching mode liquid crystal display. The fringe field switching mode liquid crystal display includes a transparent common electrode having a predetermined shape and formed within the pixel area to adjust light transmittance by applying a voltage to the liquid crystal layer, and a transparent pixel electrode having a plurality of slits and formed above the transparent common electrode with an insulating layer interposed between the transparent common electrode and the transparent pixel electrode. A rubbing direction for aligning the liquid crystal layer is within 5° with respect to a direction of the gate line to remove a light shielding region above the data line, one end of the transparent common electrode is arranged between the data line and the transparent pixel electrode, and a distance between the transparent common electrode and the transparent pixel electrode is regulated with respect to the data line. | 10-06-2011 |
Sun Choi, Icheon-Si KR
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20120187304 | PIXEL ARRAY AND IMAGE SENSOR INCLUDING THE SAME - A pixel array and an image sensor including the pixel array having improved sensitivity and can drive pixels with high resolution, according to embodiments. In embodiments, a pixel array may include a plurality of pixels having a pixel area and a logic area. The pixel array may include at least one of: ( | 07-26-2012 |
20140124888 | Image Sensor and Method for Manufacturing the Same - An image sensor having a pixel region, a logic region, and an analog region, that includes a photodiode region in a substrate in the pixel region, an insulating layer on the substrate containing a zero wiring layer in the pixel region, a first wiring layer in the pixel region, the logic region, and the analog region, and a second wiring layer in the logic region and the analog region, a first trench in a portion of the insulating layer in the pixel region, second trenches in a bottom of the first trench to match to the photodiode region, color filter layers in respective second trenches, and microlenses on respective color filter layers. | 05-08-2014 |
20150270308 | CMOS IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME - A complementary metal-oxide-semiconductor (CMOS) image sensor includes a substrate including a photodiode, a transistor on the substrate; a first insulating layer on the substrate; a contact connected to the transistor and passing through the first insulating layer; an etch stop layer on the first insulating layer; a second insulating layer on the etch stop layer; and a signal line extending through the etch stop layer and the second insulating layer, on the first insulating layer and connected to the contact. | 09-24-2015 |
Sung Jin Choi, Icheon-Si KR
Sung Wook Choi, Icheon-Si KR
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20140062429 | RECTIFIER CIRCUIT - A rectifier circuit capable of attenuating an offset voltage wherein the rectifier circuit includes an amplification unit configured to generate an output voltage through an output terminal in response to a reference voltage and a voltage at a feedback node, a plurality of first unit resistors connected between the output terminal and the feedback node, and a plurality of second unit resistors connected between the feedback node and a ground terminal, and wherein each of the first unit resistors and each of the second unit resistors are designed to have different resistance values. | 03-06-2014 |
Won Beom Choi, Icheon-Si KR
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20120119815 | SWITCHING CIRCUIT OF SEMICONDUCTOR APPARATUS - A switching circuit of a semiconductor apparatus includes a first switching unit configured to substantially prevent a leakage current applied from an outside and simultaneously switch a first signal with a first high voltage bias level, and a second switching unit configured to switch a second signal with a second high voltage bias according to the first high voltage bias level. The first switching unit and the second switching unit are selectively switched by a first enable signal and a second enable signal, which are applied from an outside, to generate a global bias signal. | 05-17-2012 |
Won-Ha Choi, Icheon-Si KR
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20150212879 | SEMICONDUCTOR DEVICE PERFORMING ERROR CORRECTION OPERATION - A semiconductor device may include a memory core including a data cell region and a parity cell region, a parity calculation logic configured for generating a parity from data received by the parity calculation logic, and an error correcting logic configured for outputting error-corrected data by using data that is output from the data cell region and a parity that is output from the parity cell region. | 07-30-2015 |
20150332789 | SEMICONDUCTOR MEMORY DEVICE PERFORMING SELF-REPAIR OPERATION - A semiconductor memory device includes a memory cell array including a main cell array and a repair cell array, a command controller that controls an input/output operation of the memory cell array, an address generator that stores a repair address, and generates an internal address according to an external address requested to be read or written, an ECC that performs a parity operation for data input/output to the memory cell array, an address table that associates an address, at which a fail has occurred when the fail has occurred in the ECC, with a number of times of occurrence of the fail, and a repair controller that selects a repair address according to the number of times of the occurrence of the fail stored in the address table, and controls the address generator to allow information of the selected repair address to be stored. | 11-19-2015 |
Won John Choi, Icheon-Si KR
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20150214153 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus has one or more semiconductor chips. The semiconductor apparatus may include a power supply pad; power lines disposed on one side of the power supply pad, and including a first power line and a second power line; and connection lines connecting the power supply pad and the power lines. The connection lines may include a plurality of first connection lines connecting the power supply pad and the first power line, and a plurality of second connection lines connecting the power supply pad and the second power line, and disposed between the first connection lines. One or more pair of adjacent first connection lines may have a connection part by which the pair of adjacent first connection lines are connected with each other. | 07-30-2015 |
Won Yeol Choi, Icheon-Si KR
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20120213008 | NONVOLATILE MEMORY DEVICE AND PROGRAM VERIFY METHOD THEREOF - A program verify method of the nonvolatile memory device includes supplying a first program verify voltage to a word line coupled to memory cells of a memory cell array, sensing a voltage of a bit line coupled to the memory cells in response to a first sense signal, supplying a second program verify voltage higher than the first program verify voltage to the word line, and sensing a voltage of the bit line in response to a second sense signal having a lower voltage level than the first sense signal. | 08-23-2012 |
Woon-Joon Choi, Icheon-Si KR
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20140269039 | ELECTRONIC DEVICE AND VARIABLE RESISTANCE ELEMENT - A variable resistance element includes: first and second magnetic layers having a lanthanide series element alloyed in a nickel-iron compound; and a tunnel barrier layer interposed between the first and second magnetic layers. | 09-18-2014 |
Yong-Soo Choi, Icheon-Si KR
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20090124082 | SLURRY FOR POLISHING RUTHENIUM AND METHOD FOR POLISHING USING THE SAME - A slurry for polishing a ruthenium layer comprises distilled water, sodium periodate (NaIO | 05-14-2009 |
Young Geun Choi, Icheon-Si KR
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20110023741 | FUSE INFORMATION DETECTION CIRCUIT - A fuse information detection circuit includes a fuse unit comprising a plurality of fuse sets and configured to output a plurality of fuse state signals, in parallel, at different levels according to whether fuses of the plurality of fuse sets are cut, a signal alignment unit configured to receive and store the plurality of fuse state signals and sequentially output the plurality of fuse state signals whenever a read pulse is inputted, and a fuse information signal generation unit configured to generate a fuse information signal by counting output of the signal alignment unit whenever the read pulse is inputted. | 02-03-2011 |
20130176806 | POWER-UP SIGNAL GENERATION CIRCUIT - A power-up signal generation circuit includes a first driving section configured to generate a pre-power-up signal by driving a first node to a first pull-up drivability or driving the first node to a first pull-down drivability in response to an internal voltage when not in an active mode, and a second driving section configured to generate the pre-power-up signal by driving the first node to a second pull-up drivability or driving the first node to a second pull-down drivability in response to the internal voltage in the active mode. The first pull-up drivability is larger than the second pull-up drivability, and the first pull-down drivability is smaller than the second pull-down drivability. | 07-11-2013 |