| Patent application number | Description | Published |
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| 20080256162 | X87 FUSED MULTIPLY-ADD INSTRUCTION - An x87 fused multiply-add (FMA) instruction in the instruction set of an x86 architecture microprocessor is disclosed. The FMA instruction implicitly specifies the two factor operands as the top two operands of the x87 FPU register stack and explicitly specifies the third addend operand as a third x87 FPU register stack register. The microprocessor multiplies the first two operands and adds the product to the third operand to generate a result. The result is stored into the third register and the first two operands are popped off the stack. In an alternate embodiment, the third operand is also implicitly specified as being stored in the register that is two registers below the top of stack register; the result is also stored therein. The instruction opcode value is in the x87 opcode range. | 10-16-2008 |
| 20080256336 | MICROPROCESSOR WITH PRIVATE MICROCODE RAM - A microprocessor includes a private RAM (PRAM), for use by microcode, which is non-user-accessible and within its own distinct address space from the system memory address space. The PRAM is denser and slower than user-accessible registers of the microprocessor macroarchitecture, thereby enabling it to provide significantly more storage for microcode. The microinstruction set includes a microinstruction for loading data from the PRAM into the user-accessible registers, and a microinstruction for storing data from user-accessible registers to the PRAM. The microcode may also use the two microinstructions to load/store between the PRAM and non-user-accessible registers of the microarchitecture. Examples of PRAM uses include: computational temporary storage area; storage of x86 VMX VMCS in response to VMREAD and VMWRITE macroinstructions; instantiation of non-user-accessible storage, such as the x86 SMBASE register; and instantiation of x86 MSRs that tolerate the additional access latency of the PRAM, such as the IA32_SYSENTER_CS MSR. | 10-16-2008 |
| 20090031090 | APPARATUS AND METHOD FOR FAST ONE-TO-MANY MICROCODE PATCH - A microcode patch apparatus including a patch array, a mux, and a RAM. The patch array receives a microcode ROM address and determines that the microcode ROM address matches one of a plurality of entries within the patch array. The patch array outputs a corresponding branch instruction and asserts a hit signal. The branch instruction prescribes a microcode branch target address. The mux receives the branch instruction from the patch array and a micro instruction corresponding to the microcode ROM address from a microcode ROM. The mux provides the micro instruction or the corresponding branch instruction to an instruction register based upon the state of the hit signal. The RAM stores a plurality of patch instructions that are to be executed in place of the micro instruction. The first one of the plurality of patch instructions is stored at a location in the RAM corresponding to the microcode branch target address. | 01-29-2009 |
| 20090031103 | MECHANISM FOR IMPLEMENTING A MICROCODE PATCH DURING FABRICATION - A patch apparatus in a microprocessor is provided. The patch apparatus includes a plurality of fuse banks and an array controller. The plurality of fuse banks is configured to store associated patch records that are employed to patch microcode or circuits in the microprocessor. The array controller is coupled to the plurality of fuse banks, and is configured to read the associated patch records, and is configured to provide the associated patch records to a patch loader, where the patch loader provides patches corresponding to the associated patch records, as prescribed, to designated target patch mechanisms in the microprocessor. The patch loader provides the patches to the designated target patch mechanisms following transition of a microprocessor reset signal and prior to execution of instructions stored in a BIOS ROM. | 01-29-2009 |
| 20090031107 | ON-CHIP MEMORY PROVIDING FOR MICROCODE PATCH OVERLAY AND CONSTANT UPDATE FUNCTIONS - A patch mechanism in a microprocessor is provided. The patch mechanism includes an expansion RAM and a patch loader. The expansion RAM stores a plurality of patches, where a first one or more of the plurality of patches are to be executed by the microprocessor in place of a corresponding one or more micro instructions which are stored in a microcode ROM, and where a second one or more of the plurality of patches are employed to patch a corresponding one or more machine states in the microprocessor. The patch loader is coupled to the expansion RAM, and is configured to retrieve the plurality of patches from a source external to the microprocessor, and is configured to load the plurality of patches into the expansion RAM. | 01-29-2009 |
| 20090031108 | CONFIGURABLE FUSE MECHANISM FOR IMPLEMENTING MICROCODE PATCHES - A patch apparatus includes fuse banks, one or more configuration fuse banks, and an array controller. The fuse banks are configured to store associated patch records that are employed to patch microcode or machine state circuits in the microprocessor or to store associated control data entities that are employed to program control circuits in the microprocessor. The configuration fuse banks are encoded to indicate whether each of the plurality of fuse banks is programmed with one of the associated patch records or with one of the associated control data entities. The array controller reads the fuse banks, and provides the associated patch records to a patch loader or the associated control data entities to control circuits in the microprocessor. The patch loader provides patches corresponding to the associated patch records, as prescribed, to designated target patch mechanisms in the microprocessor. The patch loader provides the patches to the designated target patch mechanisms following transition of a microprocessor reset signal and prior to execution of instructions stored in a BIOS ROM. | 01-29-2009 |
| 20090031109 | APPARATUS AND METHOD FOR FAST MICROCODE PATCH FROM MEMORY - A microcode patch apparatus including a patch array, a mux, and a RAM. The patch array receives a microcode ROM address and determines that the microcode ROM address matches one of a plurality of entries within the patch array. The patch array outputs a corresponding branch instruction and asserts a hit signal. The branch instruction prescribes a microcode branch target address. The mux receives the branch instruction from the patch array and a micro instruction corresponding to the microcode ROM address from a microcode ROM. The mux provides the micro instruction or the corresponding branch instruction to an instruction register based upon the state of the hit signal. The RAM stores a plurality of patch instructions that are to be executed in place of the micro instruction. The first one of the plurality of patch instructions is stored at a location in the RAM corresponding to the microcode branch target address. | 01-29-2009 |
| 20090031110 | MICROCODE PATCH EXPANSION MECHANISM - A microcode patch expansion mechanism includes a patch RAM, an expansion RAM, and a controller. The patch RAM stores a first plurality of patch instructions. The first plurality is to be executed by the microprocessor in place of one or more micro instructions which are stored in a microcode ROM. The expansion RAM stores a second plurality of patch instructions. The number of the second plurality is greater than the number of the first plurality. The second plurality is to be executed by the microprocessor in place of a second one or more micro instructions which are stored in the microcode ROM. The controller executes an EXPRAM micro instruction directing that one or more of the second plurality of patch instructions be loaded into the patch RAM, and loads the one or more of the second plurality of patch instructions into the patch RAM. | 01-29-2009 |
| 20090031121 | APPARATUS AND METHOD FOR REAL-TIME MICROCODE PATCH - An apparatus for performing microcode patches that is both fast and flexible. In one embodiment, an apparatus for performing a real-time microcode patch is provided. The apparatus includes a patch array and a mux. The patch array receives a microcode ROM address and determines that the microcode ROM address matches one of a plurality of entries within the patch array. When the microcode ROM address matches, the patch array outputs a corresponding patch instruction and to assert a hit signal. The mux receives the patch instruction from the patch array and a micro instruction corresponding to the microcode ROM address from a microcode ROM. The mux provides the micro instruction or the corresponding patch instruction to an instruction register based upon the state of the hit signal. | 01-29-2009 |
| 20090290712 | ON-DIE CRYPTOGRAPHIC APPARATUS IN A SECURE MICROPROCESSOR - An apparatus providing for a secure execution environment, including a secure non-volatile memory and a microprocessor. The secure non-volatile memory stores a secure application program. The secure application program is encrypted according to a cryptographic algorithm. The microprocessor is coupled to the secure non-volatile memory via a private bus and to a system memory via a system bus. The microprocessor executes non-secure application programs and the secure application program. The non-secure application programs are accessed from the system memory via the system bus. Transactions over the private bus are isolated from the system bus and corresponding system bus resources within the microprocessor. The microprocessor has a cryptographic unit, disposed within execution logic. The cryptographic unit is configured to encrypt the secure application program for storage in the secure non-volatile memory, and is configured to decrypt the secure application program for execution by the microprocessor. | 11-26-2009 |
| 20090292847 | MICROPROCESSOR APPARATUS PROVIDING FOR SECURE INTERRUPTS AND EXCEPTIONS - An apparatus for executing secure code, having a microprocessor coupled to a secure non-volatile memory via a private bus a system memory via a system bus. The microprocessor executes non-secure application programs and a secure application program. The microprocessor accomplishes private bus transactions over the private bus to access the secure application program within the secure non-volatile memory. The private bus transactions are hidden from system bus resources and devices coupled to the system bus. The microprocessor includes normal interrupt logic and secure execution mode interrupt logic. The normal interrupt logic provides non-secure interrupts for interrupting the non-secure application programs when the microprocessor is operating in a non-secure mode. The secure execution mode interrupt logic provides secure interrupts when the microprocessor is operating in a secure mode, where the secure execution mode interrupt logic cannot be observed or accessed by the system bus resources or the non-secure application programs. | 11-26-2009 |
| 20090292853 | APPARATUS AND METHOD FOR PRECLUDING EXECUTION OF CERTAIN INSTRUCTIONS IN A SECURE EXECUTION MODE MICROPROCESSOR - An apparatus providing for a secure execution environment is presented. The apparatus includes a microprocessor and a secure non-volatile memory. The microprocessor is configured to execute non-secure application programs and a secure application program, where the non-secure application programs are accessed from a system memory via a system bus, and where the secure application program is executed in a secure execution mode. The microprocessor has secure execution mode logic that is configured to monitor instructions within the secure application program, and that is configured to preclude execution of certain instructions. The secure non-volatile memory is coupled to the microprocessor via a private bus, and is configured to store the secure application program, where transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor. | 11-26-2009 |
| 20090292893 | MICROPROCESSOR HAVING SECURE NON-VOLATILE STORAGE ACCESS - An apparatus providing for a secure execution environment. The apparatus includes a microprocessor and a secure non-volatile memory. The microprocessor is configured to execute non-secure application programs and a secure application program, where the non-secure application programs are accessed from a system memory via a system bus. The secure non-volatile memory is coupled to the microprocessor via a private bus. The secure non-volatile memory is configured to store the secure application program, where transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor. | 11-26-2009 |
| 20090292894 | MICROPROCESSOR HAVING INTERNAL SECURE MEMORY - An apparatus providing for a secure execution environment. The apparatus includes a microprocessor that is configured to execute non-secure application programs and a secure application program, where the non-secure application programs are accessed from a system memory via a system bus. The microprocessor has a non-secure memory and a secure volatile memory. The non-secure memory is configured to store portions of the non-secure application programs for execution by the microprocessor, where the non-secure memory is observable and accessible by the non-secure application programs and by system bus resources within the microprocessor. The secure volatile memory is configured to store the secure application program for execution by the microprocessor, where the secure volatile memory is isolated from the non-secure application programs and the system bus resources within the microprocessor. | 11-26-2009 |
| 20090292901 | MICROPROCESSOR APPARATUS AND METHOD FOR PERSISTENT ENABLEMENT OF A SECURE EXECUTION MODE - An apparatus providing for a secure execution environment including a microprocessor and a secure non-volatile memory. The microprocessor executes non-secure application programs and a secure application program. The secure application program is executed exclusively within a secure execution mode within the microprocessor. The non-secure application programs are accessed from a system memory via a system bus. The microprocessor has a non-volatile enabled indicator register that is configured indicate whether the microprocessor is within the secure execution mode or a non-secure execution mode, where contents of the non-volatile enabled indicator register persist through power removal and reapplication to the microprocessor. The secure non-volatile memory is coupled to the microprocessor via a private bus and is configured to store the secure application program, where transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor. | 11-26-2009 |
| 20090292902 | APPARATUS AND METHOD FOR MANAGING A MICROPROCESSOR PROVIDING FOR A SECURE EXECUTION MODE - An apparatus providing for a secure execution environment including a microprocessor and a secure non-volatile memory. The microprocessor executes non-secure application programs and a secure application program. The non-secure application programs are accessed from a system memory via a system bus. The secure application program executes in a secure execution mode. The microprocessor has secure execution mode logic that monitors conditions corresponding to the microprocessor associated with tampering, and causes the microprocessor to transition to a degraded operating mode from the secure execution mode following detection of a first one or more of the conditions. The degraded operating mode exclusively provides for execution of BIOS instructions. The secure non-volatile memory is coupled to the microprocessor via a private bus, stores the secure application program. Transactions over the private bus are isolated from the system bus and corresponding system bus resources within the microprocessor. | 11-26-2009 |
| 20090292903 | MICROPROCESSOR PROVIDING ISOLATED TIMERS AND COUNTERS FOR EXECUTION OF SECURE CODE - An apparatus providing for a secure execution environment is presented. The apparatus includes a microprocessor and a secure non-volatile memory. The a microprocessor is configured to execute non-secure application programs and a secure application program, where the non-secure application programs are accessed from a system memory via a system bus. The microprocessor has a plurality of timers which are visible and accessible only by the secure application program when executing in a secure execution mode. The secure non-volatile memory is coupled to the microprocessor via a private bus and is configured to store the secure application program. Transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor. | 11-26-2009 |
| 20090292904 | APPARATUS AND METHOD FOR DISABLING A MICROPROCESSOR THAT PROVIDES FOR A SECURE EXECUTION MODE - An apparatus providing for a secure execution environment including a microprocessor and a secure non-volatile memory. The microprocessor executes non-secure application programs and a secure application program, where the non-secure application programs are accessed from a system memory via a system bus, and where the secure application program is executed in a secure execution mode. The microprocessor has secure watchdog logic that monitors environmental attributes corresponding to the microprocessor and to the secure application program, and that is configured to transfer program control to one of a plurality of event handlers within the secure application program. The secure non-volatile memory is coupled to the microprocessor via a private bus. The secure non-volatile memory is configured to store the secure application program, where transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor. | 11-26-2009 |
| 20090292929 | INITIALIZATION OF A MICROPROCESSOR PROVIDING FOR EXECUTION OF SECURE CODE - An apparatus including a microprocessor and a secure non-volatile memory. The microprocessor executes non-secure application programs and a secure application program. The microprocessor has secure execution mode initialization logic and an authorized public key. The secure execution mode initialization logic provides for initialization of a secure execution mode within the microprocessor. The secure execution mode initialization logic employs an asymmetric key algorithm to decrypt an enable parameter directing entry into the secure execution mode. The authorized public key is used to decrypt the enable parameter, the enable parameter having been encrypted according to the asymmetric key algorithm using an authorized private key that corresponds to the authorized public key. The secure non-volatile memory stores the secure application program, where transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor. | 11-26-2009 |
| 20090292931 | APPARATUS AND METHOD FOR ISOLATING A SECURE EXECUTION MODE IN A MICROPROCESSOR - An apparatus providing for a secure execution environment, including a microprocessor and a secure non-volatile memory. The microprocessor executes non-secure application programs and a secure application program, where the non-secure application programs are accessed from a system memory via a system bus. The microprocessor has secure execution mode logic that is configured to provide for a secure execution mode within the microprocessor for execution of the secure application program. The secure execution mode logic records the state of the microprocessor in a non-volatile indicator register upon entry into the secure execution mode and upon exit from the secure execution mode. The secure non-volatile memory is coupled to the microprocessor via a private bus and is configured to store the secure application program. Transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor. | 11-26-2009 |
| 20090293129 | TERMINATION OF SECURE EXECUTION MODE IN A MICROPROCESSOR PROVIDING FOR EXECUTION OF SECURE CODE - An apparatus providing for a secure execution environment including a microprocessor and a secure non-volatile memory. The microprocessor is configured to execute non-secure application programs and a secure application program, where the non-secure application programs are accessed from a system memory via a system bus. The microprocessor has secure execution mode logic that is configured to detect execution of a secure execution mode return event, and that is configured to terminate a secure execution mode within the microprocessor, where the secure execution mode exclusively supports execution of the secure application program. The secure non-volatile memory is coupled to the microprocessor via a private bus and is configured to store the secure application program prior to termination of the secure execution mode, where transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor. | 11-26-2009 |
| 20090293130 | MICROPROCESSOR HAVING A SECURE EXECUTION MODE WITH PROVISIONS FOR MONITORING, INDICATING, AND MANAGING SECURITY LEVELS - An apparatus providing for a secure execution environment including a microprocessor and a secure non-volatile memory. The microprocessor executes non-secure application programs and a secure application program. The non-secure application programs are accessed from a system memory via a system bus, and the secure application program is executed in a secure execution mode. The microprocessor has a watchdog manager that monitors environments of the microprocessor by noting and evaluating data communicated by a plurality of monitors, and that classifies the data to indicate a security level associated with execution of the secure application program, and that directs secure execution mode logic to perform responsive actions in accordance with the security level. The secure non-volatile memory is coupled to the microprocessor via a private bus, and stores the secure application program. Transactions over the private bus are isolated from the system bus and corresponding system bus resources within the microprocessor. | 11-26-2009 |
| 20090293132 | MICROPROCESSOR APPARATUS FOR SECURE ON-DIE REAL-TIME CLOCK - An apparatus providing for a secure execution environment. The apparatus includes a microprocessor and an external crystal. The microprocessor is configured to execute non-secure application programs and a secure application program, where the non-secure application programs are accessed from a system memory via a system bus and the secure application program is accessed from a secure non-volatile memory via a private bus coupled to the microprocessor. The microprocessor has a secure real time clock that is configured to provide a persistent time, where the secure real time clock is only visible and accessible by the secure application program when the microprocessor is executing in a secure mode. The external crystal is coupled to the secure real time clock within the microprocessor and is configured to cause an oscillator within the secure real time clock to generate an oscillating output voltage that is proportional to the frequency of the external crystal. | 11-26-2009 |
| 20090296511 | MICROPROCESSOR WITH PROGRAM-ACCESSIBLE RE-WRITABLE NON-VOLATILE STATE EMBODIED IN BLOWABLE FUSES OF THE MICROPROCESSOR - A microprocessor includes re-writeable non-volatile state (RNS) addressable by an instruction executed by the microprocessor that instructs the microprocessor to write a new value to the RNS. A plurality of fuses are each readable to determine whether the fuse is blown or unblown, in response to the microprocessor decoding the instruction. A Boolean logic unit performs Boolean operations on the values read from the plurality of fuses to determine a current RNS value. A fuse blowing device blows at least one unblown fuse to change the current RNS value to the new value when the new value is different than the current value. The microprocessor can read the plurality of fuses, perform the Boolean operations, and blow at least one unblown fuse to change the current value of the RNS to a new value multiple times in response to a program running on the microprocessor executing the instruction multiple times. | 12-03-2009 |
| 20100011198 | MICROPROCESSOR WITH MULTIPLE OPERATING MODES DYNAMICALLY CONFIGURABLE BY A DEVICE DRIVER BASED ON CURRENTLY RUNNING APPLICATIONS - A computing system includes a microprocessor that receives values for configuring operating modes thereof. A device driver monitors which software applications currently running on the microprocessor are in a predetermined list and responsively dynamically writes the values to the microprocessor to configure its operating modes. Examples of the operating modes the device driver may configure relate to the following: data prefetching; branch prediction; instruction cache eviction; instruction execution suspension; sizes of cache memories, reorder buffer, store/load/fill queues; hashing algorithms related to data forwarding and branch target address cache indexing; number of instruction translation, formatting, and issuing per clock cycle; load delay mechanism; speculative page tablewalks; instruction merging; out-of-order execution extent; caching of non-temporal hinted data; and serial or parallel access of an L2 cache and processor bus in response to an instruction cache miss. | 01-14-2010 |
| 20100064117 | APPARATUS AND METHOD FOR UPDATING SET OF LIMITED ACCESS MODEL SPECIFIC REGISTERS IN A MICROPROCESSOR - A microprocessor having model specific registers (MSRs) includes, for each of the MSRs, an associated default value that indicates whether the MSR is protected or non-protected and an associated fuse that, if blown, toggles the associated default value from protected to non-protected or non-protected to protected. In one embodiment, microcode that does the following in response to the microprocessor encountering an instruction that accesses a specified MSR: determines whether the fuse associated with the specified MSR is blown or unblown, uses the default value associated with the MSR as an indicator of whether the MSR is protected if the associated fuse is unblown; toggles the associated default value to generate the indicator if the associated fuse is blown; protects access to the MSR if the indicator indicates the MSR is protected; and refrains from protecting access to the MSR if the indicator indicates the MSR is non-protected. | 03-11-2010 |
| 20100064122 | FAST STRING MOVES - A microprocessor REP MOVS macroinstruction specifies the word length of the string in the IA-32 ECX register. The microprocessor includes a memory, configured to store a first and second sequence of microinstructions. The first sequence conditionally transfers control to a microinstruction within the first sequence based on the ECX register. The second sequence does not conditionally transfer control based on the ECX register. The microprocessor includes an instruction translator, coupled to the memory. In response to a macroinstruction that moves an immediate value into the ECX register, the instruction translator sets a flag and saves the immediate value. In response to a macroinstruction that modifies the ECX register in a different manner, the translator clears the flag. In response to a REP MOVS macroinstruction, the instruction translator transfers control to the first sequence if the flag is clear; and transfers control to the second sequence if the flag is set. | 03-11-2010 |
| 20100070741 | MICROPROCESSOR WITH FUSED STORE ADDRESS/STORE DATA MICROINSTRUCTION - A microprocessor includes an instruction translator that translates a store macroinstruction into exactly one fused store microinstruction. The store macroinstruction in the microprocessor's macroarchitecture macroinstruction set instructs the microprocessor to store data from a general purpose register of the microprocessor to a memory location. The fused store microinstruction is an instruction in the microprocessor's microarchitecture microinstruction set. A reorder buffer (ROB) receives the fused store microinstruction from the instruction translator into exactly one of its plurality of entries. An instruction dispatcher dispatches for execution a store address microinstruction and a store data microinstruction to different respective execution units of the microprocessor in response to receiving the fused store microinstruction. Neither the store address microinstruction nor the store data microinstruction occupy any of the ROB entries. The ROB retires the fused store microinstruction after being notified that both the store address microinstruction and the store data microinstruction have been executed. | 03-18-2010 |
| 20100180104 | APPARATUS AND METHOD FOR PATCHING MICROCODE IN A MICROPROCESSOR USING PRIVATE RAM OF THE MICROPROCESSOR - A microprocessor has a microcode memory for storing original microcode instructions to implement user program instructions, and an interface to an external memory for storing a microcode patch. The microcode patch includes substitute microcode instructions and validation information. The microprocessor includes a private random access memory (PRAM), addressable by the original and substitute microcode instructions but not addressable by user program instructions. The microprocessor also includes patch hardware, which conditionally receives the substitute microcode instructions. The microprocessor executes the substitute microcode instructions when applied to the patch hardware instead of corresponding original microcode instructions. The microprocessor is configured to load the microcode patch from external memory into PRAM, determine whether the microcode patch is valid, apply substitute microcode instructions from PRAM to the patch hardware if the microcode patch is valid, and refrain from applying the substitute microcode instructions to the patch hardware, if the microcode patch is invalid. | 07-15-2010 |
| 20100205399 | PERFORMANCE COUNTER FOR MICROCODE INSTRUCTION EXECUTION - An apparatus for counting microcode instruction execution in a microprocessor includes a first register, a second register, a comparator, and a counter. The first register stores an address of a microcode instruction. The microcode instruction is stored in a microcode memory of the microprocessor. The second register stores an address of the next microcode instruction to be retired by a retire unit of the microprocessor. The comparator compares the addresses stored in the first and second registers to indicate a match between them. The counter counts the number of times the comparator indicates a match between the addresses stored in the first register and the second register. The first register is user-programmable and the counter is user-readable. A mask register may be included to create a range of microcode memory addresses so that executions of microcode instructions within the range are counted. | 08-12-2010 |
| 20100205401 | PIPELINED MICROPROCESSOR WITH FAST NON-SELECTIVE CORRECT CONDITIONAL BRANCH INSTRUCTION RESOLUTION - A microprocessor includes a register that stores a state and a fetch unit that fetches instructions of a program. The program includes a first instruction followed non-immediately by a second instruction. The first instruction instructs the microprocessor to update the state in the register. The second instruction is a conditional branch instruction that specifies a branch condition based on the register state. The fetch unit dispatches the first instruction for execution but refrains from dispatching the second instruction for execution. Execution units receive the first instruction from the fetch unit and responsively update the register state. The fetch unit non-selectively correctly resolves the conditional branch instruction based on the register state when the execution units have updated the register state. The fetch unit also non-selectively refrains from sending the conditional branch instruction to the execution units to be resolved regardless of whether the execution units have updated the register state. | 08-12-2010 |
| 20100205402 | PIPELINED MICROPROCESSOR WITH NORMAL AND FAST CONDITIONAL BRANCH INSTRUCTIONS - A microprocessor includes a first branch condition state and a second branch condition state. The microprocessor also includes a conditional branch instruction of a first type that instructs the microprocessor to wait to correctly resolve the conditional branch instruction of the first type based on the first branch condition state until other instructions within the microprocessor that update the first branch condition state and that are older than the conditional branch instruction of the first type have updated the first branch condition state. A conditional branch instruction of a second type instructs the microprocessor to correctly resolve the conditional branch instruction of the second type based on the second branch condition state without regard to whether other instructions within the microprocessor that update the second branch condition state and that are older than the conditional branch instruction of the second type have yet updated the second branch condition state. | 08-12-2010 |
| 20100205403 | PIPELINED MICROPROCESSOR WITH FAST CONDITIONAL BRANCH INSTRUCTIONS BASED ON STATIC EXCEPTION STATE - A microprocessor includes a memory that stores an exception handler to handle an exception condition. The exception handler is a non-user program private to the microprocessor and includes a conditional branch instruction. A first fetch unit fetches instructions of a user program that includes a user program instruction that causes the exception condition. An execution unit executes the user program instructions fetched by the first fetch unit and executes instructions of the exception handler. The execution unit also saves a state in response to detecting the exception condition caused by the user program instruction. A second fetch unit fetches the exception handler instructions from the memory and resolves the conditional branch instruction based on the saved state without sending the conditional branch instruction to the execution unit to resolve the conditional branch instruction. | 08-12-2010 |
| 20100205404 | PIPELINED MICROPROCESSOR WITH FAST CONDITIONAL BRANCH INSTRUCTIONS BASED ON STATIC MICROCODE-IMPLEMENTED INSTRUCTION STATE - A microprocessor includes a memory that stores instructions of a non-user program to implement a user program instruction of the user-visible instruction set of the microprocessor. The non-user program includes a conditional branch instruction. A first fetch unit fetches instructions of the user program that includes the instruction that is implemented by the non-user program. An instruction decoder decodes the user program instructions and saves a state in response to decoding the user program instruction that is implemented by the non-user program. An execution unit executes the user program instructions fetched by the first fetch unit and executes instructions of the non-user program other than the conditional branch instruction. A second fetch unit fetches the non-user program instructions from the memory and resolves the conditional branch instruction based on the saved state without sending the conditional branch instruction to the execution unit to resolve the conditional branch instruction. | 08-12-2010 |
| 20100205407 | PIPELINED MICROPROCESSOR WITH FAST NON-SELECTIVE CORRECT CONDITIONAL BRANCH INSTRUCTION RESOLUTION - A microprocessor includes a pipeline of stages for processing instructions and first and second types of conditional branch instruction includable by a program. The microprocessor makes a prediction of conditional branch instructions of the first type and flushes the pipeline of instructions if the prediction is subsequently determined to be incorrect, thereby incurring a branch misprediction penalty related to processing of conditional branch instructions of the first type. The microprocessor always correctly resolves conditional branch instructions of the second type without making a prediction of conditional branch instructions of the second type, thereby avoiding ever incurring a branch misprediction penalty related to processing of conditional branch instructions of the second type. | 08-12-2010 |
| 20100205415 | PIPELINED MICROPROCESSOR WITH FAST CONDITIONAL BRANCH INSTRUCTIONS BASED ON STATIC SERIALIZING INSTRUCTION STATE - A microprocessor includes a control register that stores a control value that affects operation of the microprocessor. An instruction set architecture includes a conditional branch instruction that specifies a branch condition based on the control value stored in the control register, and a serializing instruction that updates the control value in the control register. The microprocessor completes all modifications to flags, registers, and memory by instructions previous to the serializing instruction and to drain all buffered writes to memory before it fetches and executes the next instruction after the serializing instruction. Execution units update the control value in the control register in response to the serializing instruction. A fetch unit fetches, decodes, and unconditionally correctly resolves and retires the conditional branch instruction based on the control value stored in the control register rather than dispatching the conditional branch instruction to the execution units to be resolved. | 08-12-2010 |
| 20100228950 | MICROPROCESSOR WITH FAST EXECUTION OF CALL AND RETURN INSTRUCTIONS - A microprocessor includes an instruction set architecture, comprising a call instruction type, a return instruction type, and other instruction types. Execution units correctly execute program instructions of the other instruction types. A call/return stack has a plurality of entries arranged in a last-in-first-out manner. The call/return stack is architectural state of the microprocessor not modifiable by program instructions of the other instruction types. The call/return stack is architectural state of the microprocessor indirectly modifiable by program instructions of the call and return instruction types. The microprocessor also includes a fetch unit that fetches program instructions and sends the program instructions of the other instruction types to the execution units to be correctly executed. The fetch unit correctly executes program instructions of the call and return instruction types without sending the program instructions of the call and return instruction types to the execution units to be correctly executed. | 09-09-2010 |
| 20100228952 | APPARATUS AND METHOD FOR FAST CORRECT RESOLUTION OF CALL AND RETURN INSTRUCTIONS USING MULTIPLE CALL/RETURN STACKS IN THE PRESENCE OF SPECULATIVE CONDITIONAL INSTRUCTION EXECUTION IN A PIPELINED MICROPROCESSOR - A microprocessor having a plurality of call/return stacks (CRS) correctly resolves a call or return instruction rather than issuing the instruction to execution units of the microprocessor to be resolved. The microprocessor fetches a call or return instruction and determines whether the instruction is the first call or return instruction fetched after fetching a conditional branch instruction that has yet to be resolved. The microprocessor copies the contents of a current CRS to another CRS and designates the other CRS as the current CRS, if the state exists. The microprocessor pushes the address of the next sequential instruction following the call instruction onto the current CRS and fetches an instruction at the call instruction target address if the instruction is a call instruction. The microprocessor pops a second return address from the current CRS and fetches an instruction at the second return address, if the instruction is a return instruction. | 09-09-2010 |
| 20100229062 | DETECTION AND CORRECTION OF FUSE RE-GROWTH IN A MICROPROCESSOR - A microprocessor includes control hardware that receives and stores control values and provides the control values to circuits of the microprocessor for controlling operation of the microprocessor. The microprocessor also includes a first plurality of fuses selectively blown collectively with a predetermined value, and a second plurality of fuses selectively blown collectively with an error correction value computed from the predetermined value collectively blown into the first plurality of fuses. In response to being reset, the microprocessor reads the first and second plurality of fuses, detects an error in the value read from the first plurality of fuses using the value read from the second plurality of fuses, corrects the value read from the first plurality of fuses back to the predetermined value using the value read from the second plurality of fuses, and uses the corrected predetermined value to write the control values into the control hardware. | 09-09-2010 |
| 20100235645 | APPARATUS AND METHOD FOR LIMITING ACCESS TO MODEL SPECIFIC REGISTERS IN A MICROPROCESSOR - A microprocessor having a control register to which the manufacturer of the microprocessor may limit access. The microprocessor includes a manufacturing identifier that uniquely identifies the microprocessor and that is externally readable from the microprocessor by a user. The microprocessor also includes a secret key, manufactured internally within the microprocessor and externally invisible. The microprocessor also includes an encryption engine, coupled to the secret key, configured to decrypt a user-supplied password using the secret key to generate a decrypted result in response to a user instruction instructing the microprocessor to access the control register. The user-supplied password is unique to the microprocessor. The microprocessor also includes an execution unit, coupled to the manufacturing identifier and the encryption engine, configured to allow the instruction access to the control register if the manufacturing identifier is included in the decrypted result, and to otherwise deny the instruction access to the control register. | 09-16-2010 |
| 20100299504 | MICROPROCESSOR WITH MICROINSTRUCTION-SPECIFIABLE NON-ARCHITECTURAL CONDITION CODE FLAG REGISTER - A microprocessor includes an architectural register and a non-architectural register, each having a plurality of condition code flags. A first instruction of the microarchitectural instruction set of the microprocessor instructs the microprocessor to update the plurality of condition code flags based on a result of the first instruction. The first instruction includes a field for indicating whether to update the plurality of condition code flags of the architectural or non-architectural register. A second instruction of the microarchitectural instruction set instructs the microprocessor to conditionally perform an operation based on one of the plurality of condition code flags. The second instruction includes a field for indicating whether to use the one of the plurality of condition code flags of the architectural or non-architectural register to determine whether to perform the operation. | 11-25-2010 |
| 20100306475 | DATA CACHE WITH MODIFIED BIT ARRAY - A cache memory system includes a first array of storage elements each configured to store a cache line, a second array of storage elements corresponding to the first array of storage elements each configured to store a first partial status of the cache line in the corresponding storage element of the first array, and a third array of storage elements corresponding to the first array of storage elements each configured to store a second partial status of the cache line in the corresponding storage element of the first array. The second partial status indicates whether or not the cache line has been modified. When the cache memory system modifies the cache line within a storage element of the first array, it writes only the second partial status in the corresponding storage element of the third array to indicate that the cache line has been modified but refrains from writing the first partial status in the corresponding storage element of the second array. The cache memory system reads both the first partial status and the second partial status to determine the full status. | 12-02-2010 |
| 20100306478 | DATA CACHE WITH MODIFIED BIT ARRAY - A microprocessor includes first and second functional units and a data cache having a data array having a write port, a modified bit array having a read port and a write port, and a tag array having a read port, each array having the corresponding predetermined organization. The first functional unit writes data to a cache line of the data array. The first functional unit sets a modified bit in the modified bit array to indicate that the corresponding cache line in the data array has been modified. The second functional unit reads the modified bit from the modified bit array to determine whether or not the cache line has been modified. The second functional unit reads a partial status of the corresponding cache line from the tag array. The partial status does not indicate whether the cache line has been modified. The tag array does not include a port by which the first functional unit may update the partial status of the corresponding cache line. | 12-02-2010 |
| 20100306503 | GUARANTEED PREFETCH INSTRUCTION - A microprocessor includes a cache memory, an instruction set having first and second prefetch instructions each configured to instruct the microprocessor to prefetch a cache line of data from a system memory into the cache memory, and a memory subsystem configured to execute the first and second prefetch instructions. For the first prefetch instruction the memory subsystem is configured to forego prefetching the cache line of data from the system memory into the cache memory in response to a predetermined set of conditions. For the second prefetch instruction the memory subsystem is configured to complete prefetching the cache line of data from the system memory into the cache memory in response to the predetermined set of conditions. | 12-02-2010 |
| 20110004644 | DYNAMIC FLOATING POINT REGISTER PRECISION CONTROL - Apparatus and methods are provided to perform floating point operations that are adaptive to the precision formats of input operands. The apparatus includes adaptive conversion logic and a tagged register file. The adaptive conversion logic receives the input operands, where each of the input operands is of a corresponding precision. The adaptive conversion logic also records the corresponding precision for use in subsequent floating point operations. The tagged register file is coupled to the adaptive conversion logic. The tagged register file stores the each of the input operands, and stores the corresponding precision and furthermore associates the corresponding precision with the each of the input operands. The subsequent floating point operations are performed at a precision level according to the corresponding precision. | 01-06-2011 |
| 20110010530 | MICROPROCESSOR WITH INTEROPERABILITY BETWEEN SERVICE PROCESSOR AND MICROCODE-BASED DEBUGGER - A microprocessor integrated circuit includes first and second processors, an internal memory accessible by the first and second processors, and a bus interface unit configured to interface to a bus external to the microprocessor for providing access to a memory external to the microprocessor. The bus interface unit, external bus, and external memory are accessible by the second processor but are inaccessible by the first processor. The first processor writes debug information to the internal memory. The first processor detects an event and provides a notification of the event to the second processor. The second processor, coupled to the bus interface unit, executes microcode in response to the event notification received from the first processor. The microcode reads the debug information from the internal memory and writes the debug information to the external memory via the bus interface unit and external bus for use in debugging the second processor. | 01-13-2011 |
| 20110010531 | DEBUGGABLE MICROPROCESSOR - A microprocessor integrated circuit includes first and second processors. The first processor is configured to detect that the second processor has not retired an instruction for a predetermined amount of clock cycles and to responsively reset the second processor. The microprocessor integrated circuit also includes microcode. The second processor is configured to execute the microcode in response to a reset of the second processor. The microcode is configured to read debug information within the microprocessor integrated circuit and to output the debug information external to the microprocessor integrated circuit in response to determining that the reset was performed by the first processor. | 01-13-2011 |
| 20110035599 | APPARATUS AND METHOD FOR GENERATING UNPREDICTABLE PROCESSOR-UNIQUE SERIAL NUMBER FOR USE AS AN ENCRYPTION KEY - A microprocessor includes a manufacturing ID that is stored in the microprocessor during manufacture thereof in a non-volatile manner. The manufacturing ID is unique to the microprocessor. The microprocessor also includes a secret encryption key that is stored internally within the microprocessor and unreadable externally from the microprocessor. The microprocessor also includes an AES encryption engine, coupled to receive the manufacturing ID and the secret encryption key, configured to encrypt the manufacturing ID using the secret encryption key to generate an unpredictable key that is unique to the microprocessor. | 02-10-2011 |
| 20110035616 | DETECTION OF UNCORRECTABLE RE-GROWN FUSES IN A MICROPROCESSOR - A microprocessor includes a first plurality of fuses, a predetermined number of which are selectively blown. Control values are provided from the first plurality of fuses to circuits of the microprocessor to control operation of the microprocessor. The microprocessor also includes a second plurality of fuses, blown with the predetermined number of the first plurality of fuses that are blown. In response to being reset, the microprocessor is configured to: read the first plurality of fuses and count a number of them that are blown; read the predetermined number from the second plurality of fuses; compare the counted number with the predetermined number read from the second plurality of fuses; and prevent itself from fetching and executing user program instructions if the number counted from reading the first plurality of fuses does not equal the predetermined number read from the second plurality of fuses. | 02-10-2011 |
| 20110035617 | USER-INITIATABLE METHOD FOR DETECTING RE-GROWN FUSES WITHIN A MICROPROCESSOR - A microprocessor includes a first plurality of fuses, selectively blown with a predetermined value for provision to circuits of the microprocessor to control operation of the microprocessor. The microprocessor also includes a second plurality of fuses, selectively blown with error detection information used to detect an error in the first plurality of fuses such that a blown fuse of the microprocessor returned a non-blown binary value. In response to a user program instruction, the microprocessor is configured to determine whether there is an error in the first plurality of fuses such that a blown fuse returned a non-blown binary value using the error detection information from the second plurality of fuses. | 02-10-2011 |
| 20110035622 | DETECTION AND CORRECTION OF FUSE RE-GROWTH IN A MICROPROCESSOR - A microprocessor includes a first plurality of fuses selectively blown with control values, a second plurality of fuses selectively blown collectively with an error correction value computed from the control values, control hardware that receives the control values and provides them to circuits of the microprocessor for controlling operation thereof. A state machine, serially coupled to the control hardware and to the fuses, serially scans the control values from the first fuses to the control hardware and serially scans the control values and the error correction value to a first register. The microprocessor reads the control values and error correction value from the first register, detects and corrects an error in the control values using the error correction value, writes the corrected control values to a second register, and causes the state machine to serially scan the corrected control values from the second register to the control hardware. | 02-10-2011 |
| 20110055530 | FAST REP STOS USING GRABLINE OPERATIONS - A microprocessor includes a cache memory and a grabline instruction. The grabline instruction specifies a memory address that implicates a cache line of the memory. The grabline instruction instructs the microprocessor to initiate a zero-beat read-invalidate transaction on the bus to obtain ownership of the cache line. The microprocessor foregoes initiating the transaction on the bus when executing the grabline instruction if the microprocessor determines that a store to the cache line would cause an exception. | 03-03-2011 |
| 20110060785 | FAST FLOATING POINT RESULT FORWARDING USING NON-ARCHITECTED DATA FORMAT - A microprocessor having an instruction set architecture (ISA) that specifies at least one architected data format (ADF) for floating-point operands. The microprocessor includes a plurality of floating-point units, each comprising an arithmetic unit configured to receive non-ADF source operands and to perform a floating-point operation on the non-ADF source operands to generate a non-ADF result. The microprocessor also includes forwarding buses, configured to forward the non-ADF result generated by each arithmetic unit of the plurality of floating-point units to each of the plurality of floating-point units for selective use as one of the non-ADF source operands. | 03-10-2011 |
| 20110060892 | SPECULATIVE FORWARDING OF NON-ARCHITECTED DATA FORMAT FLOATING POINT RESULTS - A microprocessor having an instruction set architecture (ISA) that specifies at least one architected data format (ADF) for floating-point operands includes first and second floating-point units. The first floating-point unit is configured to speculatively forward a non-ADF result generated by the first floating-point unit to the second floating-point unit. The non-ADF result is associated with a first instruction. The second floating-point unit is configured to use the speculatively forwarded non-ADF result associated with the first instruction as a source operand to generate a result of a second instruction. The second floating-point unit is further configured to convert the non-ADF result to an ADF result and to determine whether the non-ADF result creates an exception condition when converted to the ADF result. The microprocessor is configured to cancel the second instruction, in response to determining that the non-ADF result creates an exception condition when converted to the ADF result. | 03-10-2011 |
| 20110060943 | APPARATUS AND METHOD FOR DETECTION AND CORRECTION OF DENORMAL SPECULATIVE FLOATING POINT OPERAND - A microprocessor includes a plurality of execution units configured to receive instructions and operands thereof and to execute the instructions. An instruction scheduler issues the instructions to the execution units and selects sources of the instruction operands. At least one of the execution units detects one of the operands of one of the instructions is a denormal operand, generates an indication that the instruction needs to be replayed in response to detecting the denormal operand, and provides the denormal operand to the instruction scheduler in response to detecting the denormal operand, rather than normalizing the denormal operand. The instruction scheduler normalizes the denormal operand, in response to the indication, and causes the normalized operand, rather than the denormal operand, to be provided to the execution unit when the instruction is replayed. | 03-10-2011 |
| 20110142228 | APPARATUS AND METHOD FOR EMPLOYING CONFIGURABLE HASH ALGORITHMS - A method for performing hash operations including: receiving a hash instruction that is part of an application program, where the hash instruction prescribes one of the hash operations and one of a plurality of hash algorithms; translating the hash instruction into a first plurality of micro instructions and a second plurality of micro instructions; and via a hash unit disposed within execution logic, executing the one of the hash operations. The executing includes first executing the first plurality of micro instructions within the hash unit to produce output data; second executing the second plurality of micro instructions within an x86 integer unit in parallel with the first executing to test a bit in a flags register, to update text pointer registers, and to process interrupts during execution of the hash operation; and storing a corresponding intermediate hash value to memory prior to allowing a pending interrupt to proceed. | 06-16-2011 |
| 20110142229 | APPARATUS AND METHOD FOR PERFORMING TRANSPARENT HASH FUNCTIONS - A method for performing hash operations including: receiving a hash instruction that prescribes one of the hash operations and one of a plurality of hash algorithms; translating the hash instruction into a first plurality of micro instructions and a second plurality of micro instructions; and via a hash unit, executing the one of the hash operations. The executing includes indicating whether the one of the hash operations has been interrupted by an interrupting event; first executing the first plurality of micro instructions within the hash unit to produce output data; second executing the second plurality of micro instructions within an x86 integer unit in parallel with the first executing to test a bit in a flags register, to update text pointer registers, and to process interrupts during execution of the hash operation; and storing a corresponding intermediate hash value to memory prior to allowing a pending interrupt to proceed. | 06-16-2011 |
| 20110185153 | SIMULTANEOUS EXECUTION RESUMPTION OF MULTIPLE PROCESSOR CORES AFTER CORE STATE INFORMATION DUMP TO FACILITATE DEBUGGING VIA MULTI-CORE PROCESSOR SIMULATOR USING THE STATE INFORMATION - A multi-core microprocessor includes first and second processing cores and a bus coupling the first and second processing cores. The bus conveys messages between the first and second processing cores. The cores are configured such that: the first core stops executing user instructions and interrupts the second core via the bus, in response to detecting a predetermined event; the second core stops executing user instructions, in response to being interrupted by the first core; each core outputs its state after it stops executing user instructions; and each core waits to begin fetching and executing user instructions until it receives a notification from the other core via the bus that the other core is ready to begin fetching and executing user instructions. In one embodiment, the predetermined event comprises detecting that the first core has retired a predetermined number of instructions. In one embodiment, microcode waits for the notification. | 07-28-2011 |
| 20110185155 | MICROPROCESSOR THAT PERFORMS FAST REPEAT STRING LOADS - A microprocessor invokes microcode in response to encountering a repeat load string instruction. The microcode includes a series of guaranteed prefetch (GPREFETCH) instructions to fetch into a cache memory of the microprocessor a series of cache lines implicated by a string of data bytes specified by the instruction. A memory subsystem of the microprocessor guarantees within architectural limits that the cache line specified by each GPREFETCH instruction will be fetched into the cache. The memory subsystem completes each GPREFETCH instruction once it determines that no conditions exist that would prevent fetching the cache line specified by the GPREFETCH instruction and once it allocates a fill queue buffer to receive the cache line. A retire unit frees a reorder buffer entry allocated to each GPREFETCH instruction in response to completion of the GPREFETCH instruction regardless of whether the cache line specified by the GPREFETCH instruction has been fetched into the cache. | 07-28-2011 |
| 20110202775 | ATOMIC HASH INSTRUCTION - A method for performing a hash operation, including providing an atomic hash instruction that directs a microprocessor to perform a the hash operation and to indicate whether the hash operation has been interrupted by an interrupting event; translating the atomic hash instruction into first and second micro instructions; via a hash unit, first executing the first micro instructions to accomplish the hash operation according to the hash mode; and via an integer unit, second executing the second micro instructions in parallel with the first executing to test a bit in a flags register, to update text pointer registers, and to process interrupts during execution of the hash operation. The atomic hash instruction has an opcode field, configured to prescribe the hash operation, and a hash mode field, configured to prescribe that the microprocessor accomplish the hash operation according to a one of a plurality of hash modes. | 08-18-2011 |
| 20110202796 | MICROPROCESSOR WITH SYSTEM-ROBUST SELF-RESET CAPABILITY - A microprocessor includes a bus interface unit that interfaces the microprocessor to a bus that includes a signal that, when asserted, instructs all bus agents to refrain from initiating bus transactions. Microcode causes the bus interface unit to assert the signal in response to detecting an event and resets the microprocessor, but does not reset a portion of the bus interface unit that asserts the signal on the bus. After the reset, the microcode causes the bus interface unit to deassert the signal on the bus. Additionally, the microcode sets a flag and saves the microprocessor state to memory before resetting itself, but does not reset the interrupt controller. After the reset, the microcode reloads the state of the microprocessor from the memory. However, if the microcode determines that the flag is set, it forgoes reloading the state of the interrupt controller. | 08-18-2011 |
| 20110264897 | MICROPROCESSOR THAT FUSES LOAD-ALU-STORE AND JCC MACROINSTRUCTIONS - A microprocessor receives first and second program-adjacent macroinstructions of the microprocessor instruction set architecture. The first macroinstruction loads an operand from a location in memory, performs an arithmetic/logic operation using the loaded operand to generate a result, and stores the result back to the memory location. The second macroinstruction jumps to a target address if condition codes satisfy a specified condition and otherwise executes the next sequential instruction. An instruction translator simultaneously translates the first and second program-adjacent macroinstructions into first, second, and third micro-operations for execution by execution units. The first micro-operation calculates the memory location address and loads the operand therefrom. The second micro-operation performs the arithmetic/logic operation using the loaded operand to generate the result, updates the condition codes based on the result, and jumps to the target address if the updated condition codes satisfy the condition. The third micro-operation stores the result to the memory location. | 10-27-2011 |
| 20110296202 | SWITCH KEY INSTRUCTION IN A MICROPROCESSOR THAT FETCHES AND DECRYPTS ENCRYPTED INSTRUCTIONS - A fetch unit fetches a sequence of blocks of encrypted instructions of an encrypted program from an instruction cache at a corresponding sequence of fetch address values. While fetching each block of the sequence, the fetch unit generates a decryption key as a function of key values and the corresponding fetch address value, and decrypts the encrypted instructions using the generated decryption key by XORing them together. A switch key instruction instructs the microprocessor to update the key values in the fetch unit while the fetch unit is fetching the sequence of blocks. The fetch unit inherently provides an effective decryption key length that depends upon the function and amount of key values used. Including one or more switch key instructions within the encrypted program increases the effective decryption key length up to the encrypted program length. | 12-01-2011 |
| 20110296203 | BRANCH AND SWITCH KEY INSTRUCTION IN A MICROPROCESSOR THAT FETCHES AND DECRYPTS ENCRYPTED INSTRUCTIONS - A microprocessor includes a fetch unit that fetches and decrypts an (atomic) branch and switch key instruction using first decryption key data. If the branch direction is not taken, the fetch unit fetches and decrypts the next sequential instruction after the branch and switch key instruction using the first decryption key data. If the direction is taken, the fetch unit fetches and decrypts a target instruction of the branch and switch key instruction using second decryption key data that is different from the first decryption key data. The instruction points to the decryption key data; alternatively, the microprocessor consults a mapping of target address ranges to decryption key data. An encryption program replaces conventional inter-program-chunk branch instructions with branch and switch key instructions before encrypting the program using information that divides the program into a sequence of chunks each chunk being a sequence of instructions and having distinct associated encryption key data. | 12-01-2011 |
| 20110296204 | MICROPROCESSOR THAT FACILITATES TASK SWITCHING BETWEEN ENCRYPTED AND UNENCRYPTED PROGRAMS - A microprocessor includes an architected register having a bit (may be x86 EFLAGS register reserved bit) set by the microprocessor. A fetch unit fetches encrypted instructions from an instruction cache and decrypts them (via XOR) prior to executing them, in response to the microprocessor setting the bit. The microprocessor saves the bit value to a stack in memory and then clears the bit in response to receiving an interrupt. The fetch unit fetches unencrypted instructions from the instruction cache and executes them without decrypting them after the microprocessor clears the bit. The microprocessor restores the saved value from the stack in memory to the bit in the architected register (and in one embodiment, also restores decryption key values) in response to executing a return from interrupt instruction. The fetch unit resumes fetching and decrypting the encrypted instructions in response to determining that the restored value of the bit is set. | 12-01-2011 |
| 20110296205 | MICROPROCESSOR THAT FACILITATES TASK SWITCHING BETWEEN MULTIPLE ENCRYPTED PROGRAMS HAVING DIFFERENT ASSOCIATED DECRYPTION KEY VALUES - A microprocessor includes a storage element having a plurality of locations each storing decryption key data associated with an encrypted program. A control register field (may be x86 EFLAGS register reserved field) specifies a storage element location associated with a currently executing encrypted program. The microprocessor restores from memory to the control register a previously saved value of the field in response to executing a return from interrupt instruction. A fetch unit fetches encrypted instructions of the currently executing encrypted program and decrypts them using the decryption key data stored the storage element location specified by the restored field value. A kill bit associated with each storage element location may be employed if the location is clobbered because more encrypted programs are multitasked than available locations in the storage element, in which case an exception is generated to re-load the clobbered decryption key data in response to the return from interrupt instruction. | 12-01-2011 |
| 20110296206 | BRANCH TARGET ADDRESS CACHE FOR PREDICTING INSTRUCTION DECRYPTION KEYS IN A MICROPROCESSOR THAT FETCHES AND DECRYPTS ENCRYPTED INSTRUCTIONS - A branch target address cache (BTAC) caches history information associated with branch and switch key instructions previously executed by a microprocessor. The history information includes a target address and an identifier (index into a register file) for identifying key values associated with each of the previous branch and switch key instructions. A fetch unit receives from the BTAC a prediction that the fetch unit fetched a previous branch and switch key instruction and receives the target address and identifier associated with the fetched branch and switch key instruction. The fetch unit also fetches encrypted instruction data at the associated target address and decrypts (via XOR) the fetched encrypted instruction data based on the key values identified by the identifier, in response to receiving the prediction. If the BTAC predicts correctly, a pipeline flush normally associated with the branch and switch key instruction is avoided. | 12-01-2011 |
| 20110316583 | APPARATUS AND METHOD FOR OVERRIDE ACCESS TO A SECURED PROGRAMMABLE FUSE ARRAY - An apparatus in an integrated circuit for re-enabling the use of precluded extended JTAG operations. The apparatus includes a JTAG control chain, a feature fuse, a machine specific register, and an access controller. The JTAG control chain is configured to enable/disable the extended JTAG operations. The feature fuse is configured to indicate whether the extended JTAG features are to be disabled. The machine specific register is configured to store a value therein. The access controller is coupled to the feature fuse, the machine specific register, and the JTAG control chain, and is configured to determine that the feature fuse is blown, and is configured to direct the JTAG control chain to enable the precluded extended JTAG operations if the value matches an override value within the access controller during a period that the value is stored within the machine specific register. | 12-29-2011 |
| 20110316613 | MICROPROCESSOR APPARATUS AND METHOD FOR SECURING A PROGRAMMABLE FUSE ARRAY - An apparatus in an integrated circuit for precluding the use of extended JTAG operations. The apparatus has a JTAG control chain, a feature fuse, and an access controller. The JTAG control chain is configured to enable/disable the extended JTAG operations. The feature fuse is configured to indicate whether the extended JTAG features are to be disabled. The access controller is coupled to the feature fuse and the JTAG control chain. The access controller determines if the feature fuse is blown, and directs the JTAG control chain to disable the extended JTAG operations. | 12-29-2011 |
| 20110316614 | APPARATUS AND METHOD FOR TAMPER PROTECTION OF A MICROPROCESSOR FUSE ARRAY - An apparatus in an integrated circuit for precluding the use of extended JTAG operations. The apparatus has a JTAG control chain, a feature fuse, a level sensor, and an access controller. The JTAG control chain is configured to enable/disable the extended JTAG operations. The feature fuse is configured to indicate whether the extended JTAG features are to be disabled. The level sensor is configured to monitor an external voltage signal, and configured to indicate that the external voltage signal is at an illegal level. The access controller is coupled to the feature fuse, the level sensor, and the JTAG control chain, and is configured to determine if the feature fuse is blown, and is configured to direct the JTAG control chain to disable the extended JTAG operations if the external voltage signal is at an illegal level regardless of whether the feature fuse is blown. | 12-29-2011 |
| 20120005514 | MULTICORE PROCESSOR POWER CREDIT MANAGEMENT IN WHICH MULTIPLE PROCESSING CORES USE SHARED MEMORY TO COMMUNICATE INDIVIDUAL ENERGY CONSUMPTION - A microprocessor includes two or more processing cores each configured to compute a first value in response to detecting a power event. The first value represents an amount of energy the core consumed during a time interval leading up to the event. The length of the time interval is predetermined. Each core reads from the memory one or more second values that represent an amount of energy the other cores consume during approximately the time interval. The second values were previously computed and written to the memory by the other cores. Each core adjusts its operating frequency based on the first and second values. The predetermined frequency may be: a frequency at which all the cores can operate over the predetermined length of time without the microprocessor consuming more than the predetermined amount of energy, or alternatively the maximum frequency at which system software may request the cores to operate. | 01-05-2012 |
| 20120047369 | REVOKEABLE MSR PASSWORD PROTECTION - A microprocessor includes an MSR and fuses. The microprocessor encounters an instruction requesting access to the MSR and specifying the MSR address, performs a function of the specified MSR address and a value read from the fuses to generate a first result, encrypts the first result with a secret key to generate a second result, compares the second result with an instruction-specified password, and allows the instruction to access the MSR if the second result matches the password and otherwise denies access MSR. Manufacturing subsequent instances of the microprocessor with a different fuse value effectively revokes the password. Alternatively, a control register of the microprocessor may be written by system software to override the fuse value and thereby revoke the password. The function may be XOR or concatenation, the encryption may be AES, and the secret key is externally invisible. | 02-23-2012 |
| 20120047377 | MULTICORE PROCESSOR POWER CREDIT MANAGEMENT BY DIRECTLY MEASURING PROCESSOR ENERGY CONSUMPTION - A microprocessor includes an input that receives an indication of the amount of instantaneous power being supplied to the microprocessor by an external power source. The microprocessor includes a plurality of processing cores that each receive the indication from the input and responsively determine an amount of energy consumed by the microprocessor during a preceding period. The period is a predetermined length of time. Each processing core operates at a frequency above a predetermined frequency in response to determining that the amount of energy consumed by the microprocessor during the preceding period is less than a predetermined amount of energy. The predetermined frequency may be: a frequency at which all the cores can operate over the predetermined length of time without the microprocessor consuming more than the predetermined amount of energy, or alternatively the maximum frequency at which system software may request the two or more processing cores to operate. | 02-23-2012 |
| 20120047385 | MULTICORE PROCESSOR POWER CREDIT MANAGEMENT TO ALLOW ALL PROCESSING CORES TO OPERATE AT ELEVATED FREQUENCY - A microprocessor includes two or more processing cores each configured to determine, at each of succeeding instances in time, an amount of energy consumed by the microprocessor during a period preceding the instance in time. The period is predetermined. Each core also operates at a frequency above a predetermined frequency in response to determining the amount of energy consumed is less than a predetermined amount of energy. All of the cores may operate above the predetermined frequency simultaneously until one of the cores determines the microprocessor has consumed more than the predetermined amount of energy during the period preceding the instance in time. The predetermined frequency may be: a frequency at which all the cores can operate over the predetermined period without the microprocessor consuming more than the predetermined amount of energy, or alternatively the maximum frequency at which system software may request the cores to operate. | 02-23-2012 |
| 20120096282 | MICROPROCESSOR THAT FETCHES AND DECRYPTS ENCRYPTED INSTRUCTIONS IN SAME TIME AS PLAIN TEXT INSTRUCTIONS - A fetch unit (a) fetches a block of instruction data from an instruction cache of the microprocessor; (b) performs an XOR on the block with a data entity to generate plain text instruction data; and (c) provides the plain text instruction data to an instruction decode unit. In a first instance the block comprises encrypted instruction data and the data entity is a decryption key. In a second instance the block comprises unencrypted instruction data and the data entity is Boolean zeroes. The time required to perform (a), (b), and (c) is the same in the first and second instances regardless of whether the block is encrypted or unencrypted. A decryption key generator selects first and second keys from a plurality of keys, rotates the first key, and adds/subtracts the rotated first key to/from the second key, all based on portions of the fetch address, to generate the decryption key. | 04-19-2012 |
| 20120161328 | RETICLE SET MODIFICATION TO PRODUCE MULTI-CORE DIES - A first reticle set designed for manufacturing dies with a limited number of cores is modified into a second reticle set suitable for manufacturing at least some dies with at least twice as many cores. The first reticle set defines scribe lines to separate the originally defined dies. At least one scribe line is removed from pairs of adjacent but originally distinctly defined dies. Inter-core communication wires are defined to connect the adjacent cores, which are configured to enable the adjacent cores to communicate during operation without connecting to any physical input/output landing pads of the resulting more numerously cored die, which will not carry signals through the inter-core communication wires off the P-core die. The inter-core communication wires may be used for power management coordination purposes or to bypass the external processor bus. | 06-28-2012 |
| 20120166763 | DYNAMIC MULTI-CORE MICROPROCESSOR CONFIGURATION DISCOVERY - A core configuration discovery method and corresponding microprocessor are provided that does not rely on off-core logic or queries by system BIOS. Reset microcode is provided in the microprocessor's cores. Upon reset, the microcode queries and/or receives from other cores configuration-revealing information and collects the configuration-revealing information to determine a composite core configuration for the microprocessor. The composite core configuration may reveal the number of enabled cores, identify the enabled cores, reveal a hierarchical coordination system of the multi-core processor, such as a nodal map of the cores for certain inter-core communication processes or restricted activities, identify various domains and domain masters within such a system, and/or identify resources, such as voltage sources, clock sources, and caches, shared by various domains of the microprocessor. The composite core configuration may be used for power state management, reconfiguration, and other purposes. | 06-28-2012 |
| 20120166764 | DYNAMIC AND SELECTIVE CORE DISABLEMENT AND RECONFIGURATION IN A MULTI-CORE PROCESSOR - Dynamically reconfigurable multi-core microprocessors and associated methods are provided. A multi-core microprocessor is provided that supports the ability of system software to disable, or kill, selected cores in such a way that they do not cause drag on the processor bus shared with the other cores. Another multi-core microprocessor is provided that supports reconfiguration of an inter-core coordination system of the microprocessor, wherein cores may be selectively designated as masters for purposes of driving signals onto an inter-core communication wire. | 06-28-2012 |
| 20120166832 | DISTRIBUTED MANAGEMENT OF A SHARED POWER SOURCE TO A MULTI-CORE MICROPROCESSOR - Microprocessors are provided with decentralized logic and associated methods for indicating power related operating states, such as desired voltages and frequency ratios, to shared microprocessor power resources such as a voltage regulator module (VRM) and phase locked loops (PLLs). Each core is configured to generate a value to indicate a desired operating state of the core. Each core is also configured to receive a corresponding value from each other core sharing the applicable resource, and to calculate a composite value compatible with the minimal needs of each core sharing the applicable resource. Each core is further configured to conditionally drive the composite value off core to the applicable resource based on whether the core is designated as a master core for purposes of controlling or coordinating the applicable resource. The composite value is supplied to the applicable shared resource without using any active logic outside the plurality of cores. | 06-28-2012 |
| 20120166837 | DECENTRALIZED POWER MANAGEMENT DISTRIBUTED AMONG MULTIPLE PROCESSOR CORES - A multi-core processor provides a configurable resource shared by two or more cores, wherein configurations of the resource affect the power, speed, or efficiency with which the cores sharing the resource are able to operate. Internal core power state management logic configures each core to participate in a de-centralized inter-core power state discovery process to discover a composite target power state for the shared resource that is a most restrictive or power-conserving state that will not interfere with any of the corresponding target power states of each core sharing the resource. The internal core power state management logic determines whether the core is a master core authorized to configure the resource, and if so, configures that resource in the discovered composite power state. The de-centralized power state discovery process is carried out between the cores on sideband, non-system bus wires, without the assistance of centralized non-core logic. | 06-28-2012 |
| 20120166845 | POWER STATE SYNCHRONIZATION IN A MULTI-CORE PROCESSOR - A multi-core processor includes microcode distributed in each core enabling each core to participate in a de-centralized inter-core state discovery process. In a related microcode-implemented method, states of a multi-core processor are discovered by at least two cores participating in a de-centralized inter-core state discovery process. The inter-core state discovery process is carried out through a combination of microcode executing on each participating core and signals exchanged between the cores through sideband non-system-bus communication wires. The discovery process is unmediated by any centralized non-core logic. Applicable discoverable states include target and composite power states, whether and how many cores are enabled, the availability and distribution of various resources, and hierarchical structures and coordination systems for the cores. The inter-core state discovery process may be carried out in accordance with various hierarchical coordination systems involving chained inter-core communications. | 06-28-2012 |
| 20120185681 | TRACER CONFIGURATION AND ENABLEMENT BY RESET MICROCODE - A microprocessor is provided with a reset logic flag and corresponding reset microcode that selectively enables the reset microcode to set up and enable debug logic before the microprocessor subsequently fetches and executes user instructions. When the reset logic flag is set to a debug mode, the reset microcode configures and enables the microprocessor's debug logic before the microprocessor subsequently fetches and executes user instructions. When the reset logic flag is set to a normal mode, the reset microcode refrains from configuring and enabling the microprocessor's debug logic. The reset logic flag is indicated by an alterable fuse or a debugger-programmable scan register. Debug configuration initialization values are also provided by several alternative structures, including the reset microcode itself, alterable fuses, and debugger-programmable scan registers. Corresponding methods are also provided for configuring the debug logic of a microprocessor. | 07-19-2012 |
| 20120260042 | LOAD MULTIPLE AND STORE MULTIPLE INSTRUCTIONS IN A MICROPROCESSOR THAT EMULATES BANKED REGISTERS - A microprocessor supports an instruction set architecture that specifies: processor modes, architectural registers associated with each mode, and a load multiple instruction that instructs the microprocessor to load data from memory into specified ones of the registers. Direct storage holds data associated with a first portion of the registers and is coupled to an execution unit to provide the data thereto. Indirect storage holds data associated with a second portion of the registers and cannot directly provide the data to the execution unit. Which architectural registers are in the first and second portions varies dynamically based upon the current processor mode. If a specified register is currently in the first portion, the microprocessor loads data from memory into the direct storage, whereas if in the second portion, the microprocessor loads data from memory into the direct storage and then stores the data from the direct storage to the indirect storage. | 10-11-2012 |
| 20120260064 | HETEROGENEOUS ISA MICROPROCESSOR WITH SHARED HARDWARE ISA REGISTERS - A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs includes a mode indicator that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program and a plurality of hardware registers. When the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, the plurality of hardware registers store x86 ISA architectural state; when the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, the plurality of hardware registers store ARM ISA architectural state. | 10-11-2012 |
| 20120260065 | MULTI-CORE MICROPROCESSOR THAT PERFORMS X86 ISA AND ARM ISA MACHINE LANGUAGE PROGRAM INSTRUCTIONS BY HARDWARE TRANSLATION INTO MICROINSTRUCTIONS EXECUTED BY COMMON EXECUTION PIPELINE - A microprocessor includes a plurality of processing cores each including a hardware instruction translator that translates instructions of x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs into microinstructions defined by a microinstruction set of the microprocessor. The microinstructions are encoded in a distinct manner from the manner in which the instructions of the x86 and ARM instruction sets are defined. Each core includes an execution pipeline that executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions. Each core uses and associated indicator to determine whether it will boot as an x86 ISA core or an ARM ISA core when reset. The indicators are configurable to indicate that at least one of the cores will boot as an x86 ISA core and at least one other of the cores will boot as an ARM ISA core. | 10-11-2012 |
| 20120260066 | HETEROGENEOUS ISA MICROPROCESSOR THAT PRESERVES NON-ISA-SPECIFIC CONFIGURATION STATE WHEN RESET TO DIFFERENT ISA - A microprocessor capable of operating as both an x86 ISA and an ARM ISA microprocessor includes first, second, and third storage that stores x86 ISA-specific, ARM ISA-specific, and non-ISA-specific state, respectively. When reset, the microprocessor initializes the first storage to default values specified by the x86 ISA, initializes the second storage to default values specified by the ARM ISA, initializes the third storage to predetermined values, and begins fetching instructions of a first ISA. The first ISA is the x86 ISA or the ARM ISA and a second ISA is the other ISA. The microprocessor updates the third storage in response to the first ISA instructions. In response to a subsequent one of the first ISA instructions that instructs the microprocessor to reset to the second ISA, the microprocessor refrains from modifying the non-ISA-specific state stored in the third storage and begins fetching instructions of the second ISA. | 10-11-2012 |
| 20120260067 | MICROPROCESSOR THAT PERFORMS X86 ISA AND ARM ISA MACHINE LANGUAGE PROGRAM INSTRUCTIONS BY HARDWARE TRANSLATION INTO MICROINSTRUCTIONS EXECUTED BY COMMON EXECUTION PIPELINE - A microprocessor includes a hardware instruction translator that translates x86 ISA and ARM ISA machine language program instructions into microinstructions, which are encoded in a distinct manner from the x86 and ARM instructions. An execution pipeline executes the microinstructions to generate x86/ARM-defined results. The microinstructions are distinct from the results generated by the execution of the microinstructions by the execution pipeline. The translator directly provides the microinstructions to the execution pipeline for execution. Each time the microprocessor performs one of the x86 ISA and ARM ISA instructions, the translator translates it into the microinstructions. An indicator indicates either x86 or ARM as a boot ISA. After reset, the microprocessor initializes its architectural state, fetches its first instructions from a reset address, and translates them all as defined by the boot ISA. An instruction cache caches the x86 and ARM instructions and provides them to the translator. | 10-11-2012 |
| 20120260068 | APPARATUS AND METHOD FOR HANDLING OF MODIFIED IMMEDIATE CONSTANT DURING INSTRUCTION TRANSLATION - An ISA-defined instruction includes an immediate field having a first and second portions specifying first and second values, which instructs the microprocessor to perform an operation using a constant value as one of its source operands. The constant value is the first value rotated/shifted by a number of bits based on the second value. An instruction translator translates the instruction into one or more microinstructions. An execution pipeline executes the microinstructions generated by the instruction translator. The instruction translator, rather than the execution pipeline, generates the constant value for the execution pipeline as a source operand of at least one of the microinstructions for execution by the execution pipeline. Alternatively, if the immediate field value is not within a predetermined subset of values known by the instruction translator, the instruction translator generates, rather than the constant, a second microinstruction for execution by the execution pipeline to generate the constant. | 10-11-2012 |
| 20120260071 | CONDITIONAL ALU INSTRUCTION CONDITION SATISFACTION PROPAGATION BETWEEN MICROINSTRUCTIONS IN READ-PORT LIMITED REGISTER FILE MICROPROCESSOR - An architectural instruction instructs a microprocessor to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if architectural condition flags satisfy a condition specified in the architectural instruction. A hardware instruction translator translates the architectural instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the operation on the source operands to generate the result, determines whether the architectural condition flags satisfy the condition, and updates a non-architectural indicator to indicate whether the architectural condition flags satisfy the condition. To execute the first microinstruction, if the non-architectural indicator updated by the first microinstruction indicates the architectural condition flags satisfy the condition, it updates the destination register with the result; otherwise, it updates the destination register with the current value of the destination register. | 10-11-2012 |
| 20120260073 | EMULATION OF EXECUTION MODE BANKED REGISTERS - A microprocessor includes processor modes comprising a user mode and a plurality of exception modes. An execution unit performs arithmetic operations on operands specified by program instructions. A first set of storage elements holds a first subset of the operands and provides them to the execution unit coupled thereto. A second set of storage elements associated with each of the modes hold a second subset of the operands and are incapable of directly providing the second operand subset to the execution unit. To enter a new mode from a current mode, logic saves the first operand subset held in the first set of storage elements to the second set of storage elements associated with the current mode and restores to the first set of storage elements the second operand subset held in the second set of storage elements associated with the new mode. | 10-11-2012 |
| 20120260074 | EFFICIENT CONDITIONAL ALU INSTRUCTION IN READ-PORT LIMITED REGISTER FILE MICROPROCESSOR - A microprocessor having performs an architectural instruction that instructs it to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if its architectural condition flags satisfy a condition specified in the architectural instruction. A hardware instruction translator translates the instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the operation on the source operands to generate the result. To execute the second microinstruction, it writes the destination register with the result generated by the first microinstruction if the architectural condition flags satisfy the condition, and writes the destination register with the current value of the destination register if the architectural condition flags do not satisfy the condition. | 10-11-2012 |
| 20120260075 | CONDITIONAL ALU INSTRUCTION PRE-SHIFT-GENERATED CARRY FLAG PROPAGATION BETWEEN MICROINSTRUCTIONS IN READ-PORT LIMITED REGISTER FILE MICROPROCESSOR - A microprocessor includes a hardware instruction translator that translates an architectural instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the shift operation on the first source operand to generate the first result and a carry flag value and updates a non-architectural carry flag with the generated carry flag value. To execute the second microinstruction, it performs the second operation on the first result and the second operand to generate the second result and new condition flag values based on the second result. If a architectural condition flags satisfy the condition, it updates the architectural carry flag with the non-architectural carry flag value and updates at least one of the other architectural condition flags with the corresponding generated new condition flag values; otherwise, it updates the architectural condition flags with the current value of the architectural condition flags. | 10-11-2012 |
| 20130067199 | CONTROL REGISTER MAPPING IN HETEROGENEOUS INSTRUCTION SET ARCHITECTURE PROCESSOR - A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs. The microprocessor includes a mode indicator that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program. The microprocessor also includes a plurality of model-specific registers (MSRs) that control aspects of the operation of the microprocessor. When the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, each of the plurality of MSRs is accessible via an x86 ISA RDMSR/WRMSR instruction that specifies an address of the MSR. When the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, each of the plurality of MSRs is accessible via an ARM ISA MRRC/MCRR instruction that specifies the address of the MSR. | 03-14-2013 |
| 20130067202 | CONDITIONAL NON-BRANCH INSTRUCTION PREDICTION - A microprocessor processes conditional non-branch instructions that specify a condition and instruct the microprocessor to perform an operation if the condition is satisfied and otherwise to not perform the operation. A predictor provides a prediction about a conditional non-branch instruction. An instruction translator translates the conditional non-branch instruction into a no-operation microinstruction when the prediction predicts the condition will not be satisfied, and into a set of one or more microinstructions to unconditionally perform the operation when the prediction predicts the condition will be satisfied. An execution pipeline executes the no-operation microinstruction or the set of microinstructions. The predictor translates into a second set of one or more microinstructions to conditionally perform the operation when the prediction does not make a prediction. In the case of a misprediction, the translator re-translates the conditional non-branch instruction into the second set of microinstructions. | 03-14-2013 |
| 20130311755 | RUNNING STATE POWER SAVING VIA REDUCED INSTRUCTIONS PER CLOCK OPERATION - A microprocessor includes functional units and control registers writeable to cause the functional units to institute actions that reduce the instructions-per-clock rate of the microprocessor to reduce power consumption when the microprocessor is operating in its lowest performance running state. Examples of the actions include in-order vs. out-of-order execution, serial vs. parallel cache access and single vs. multiple instruction issue, retire, translation and/or formatting per clock cycle. The actions may be instituted only if additional conditions exist, such as residing in the lowest performance running state for a minimum time, not running in a higher performance state for more than a maximum time, a user did not disable the feature, the microprocessor supports multiple running states and the operating system supports multiple running states. | 11-21-2013 |
| 20140013089 | CONDITIONAL LOAD INSTRUCTIONS IN AN OUT-OF-ORDER EXECUTION MICROPROCESSOR - A microprocessor instruction translator translates a conditional load instruction into at least two microinstructions. An out-of-order execution pipeline executes the microinstructions. To execute a first microinstruction, an execution unit receives source operands from the source registers of a register file and responsively generates a first result using the source operands. To execute a second the microinstruction, an execution unit receives a previous value of the destination register and the first result and responsively reads data from a memory location specified by the first result and provides a second result that is the data if a condition is satisfied and that is the previous destination register value if not. The previous value of the destination register comprises a result produced by execution of a microinstruction that is the most recent in-order previous writer of the destination register with respect to the second microinstruction. | 01-09-2014 |
| 20140059358 | REVOKEABLE MSR PASSWORD PROTECTION - A microprocessor includes a model specific register (MSR) having an address, fuses manufactured with a first predetermined value, and a control register. The microprocessor initially loads the first predetermined value from fuses into the control register. The microprocessor also receives a second predetermined value into the control register from system software of a computer system comprising the microprocessor subsequent to initially loading the first predetermined value into the control register. The microprocessor prohibits access to the MSR by an instruction that provides a first password generated by encrypting a function of the first predetermined value and the MSR address with a secret key manufactured into the first instance of the microprocessor and enables access to the MSR by an instruction that provides a second password generated by encrypting the function of the second predetermined value and the MSR address with the secret key. | 02-27-2014 |
| 20140122843 | CONDITIONAL STORE INSTRUCTIONS IN AN OUT-OF-ORDER EXECUTION MICROPROCESSOR - An instruction translator translates a conditional store instruction (specifying data register, base register, and offset register of the register file) into at least two microinstructions. An out-of-order execution pipeline executes the microinstructions. To execute a first microinstruction, an execution unit receives a base value and an offset from the register file and generates a first result as a function of the base value and offset. The first result specifies the memory location address. To execute a second microinstruction, an execution unit receives the first result and writes the first result to an allocated entry in the store queue if the condition flags satisfy the condition (the store queue subsequently writes the data to the memory location specified by the address), and otherwise kills the allocated store queue entry so that the store queue does not write the data to the memory location specified by the address. | 05-01-2014 |
| 20140122847 | MICROPROCESSOR THAT TRANSLATES CONDITIONAL LOAD/STORE INSTRUCTIONS INTO VARIABLE NUMBER OF MICROINSTRUCTIONS - An instruction translator receives a conditional load/store instruction that specifies a condition, destination/data register, base register, offset source, and memory addressing mode. The instruction instructs the microprocessor to load data from a memory location into the destination register (conditional load) or store data to the memory location from the data register (conditional store) only if the condition flags satisfy the condition. The offset source specifies whether the offset is an immediate value or a value in an offset register. The addressing mode specifies whether the base register is updated when the condition flags satisfy the condition. The instruction translator translates the conditional load instruction into a number of microinstructions, which varies as a function of the offset source, addressing mode, and whether the conditional instruction is a conditional load or store instruction. An out-of-order execution pipeline executes the microinstructions to generate results specified by the instruction. | 05-01-2014 |
| 20140164816 | DISTRIBUTED MANAGEMENT OF A SHARED CLOCK SOURCE TO A MULTI-CORE MICROPROCESSOR - Microprocessors are provided with decentralized logic and associated methods for indicating power related operating states, such as desired voltages and frequency ratios, to shared microprocessor power resources such as a voltage regulator module (VRM) and phase locked loops (PLLs). Each core is configured to generate a value to indicate a desired operating state of the core. Each core is also configured to receive a corresponding value from each other core sharing the applicable resource, and to calculate a composite value compatible with the minimal needs of each core sharing the applicable resource. Each core is further configured to conditionally drive the composite value off core to the applicable resource based on whether the core is designated as a master core for purposes of controlling or coordinating the applicable resource. The composite value is supplied to the applicable shared resource without using any active logic outside the plurality of cores. | 06-12-2014 |
| 20140173301 | POWER STATE SYNCHRONIZATION IN A MULTI-CORE PROCESSOR - A multi-core processor includes microcode distributed in each core enabling each core to participate in a de-centralized inter-core state discovery process. In a related microcode-implemented method, states of a multi-core processor are discovered by at least two cores participating in a de-centralized inter-core state discovery process. The inter-core state discovery process is carried out through a combination of microcode executing on each participating core and signals exchanged between the cores through sideband non-system-bus communication wires. The discovery process is unmediated by any centralized non-core logic. Applicable discoverable states include target and composite power states, whether and how many cores are enabled, the availability and distribution of various resources, and hierarchical structures and coordination systems for the cores. The inter-core state discovery process may be carried out in accordance with various hierarchical coordination systems involving chained inter-core communications. | 06-19-2014 |
| 20140195820 | APPARATUS FOR GENERATING A DECRYPTION KEY FOR USE TO DECRYPT A BLOCK OF ENCRYPTED INSTRUCTION DATA BEING FETCHED FROM AN INSTRUCTION CACHE IN A MICROPROCESSOR - An apparatus for generating a decryption key for use to decrypt a block of encrypted instruction data being fetched from an instruction cache in a microprocessor at a fetch address includes a first multiplexer that selects a first key value from a plurality of key values based on a first portion of the fetch address. A second multiplexer selects a second key value from the plurality of key values based on the first portion of the fetch address. A rotater rotates the first key value based on a second portion of the fetch address. An arithmetic unit selectively adds or subtracts the rotated first key value to or from the second key value based on a third portion of the fetch address to generate the decryption key. | 07-10-2014 |
| 20140195821 | METHOD FOR ENCRYPTING A PROGRAM FOR SUBSEQUENT EXECUTION BY A MICROPROCESSOR CONFIGURED TO DECRYPT AND EXECUTE THE ENCRYPTED PROGRAM - A method for encrypting a program for subsequent execution by a microprocessor configured to decrypt and execute the encrypted program includes receiving an object file specifying an unencrypted program that includes conventional branch instructions whose target address may be determined pre-run time. The method also includes analyzing the program to obtain chunk information that divides the program into a sequence of chunks each comprising a sequence of instructions and that includes encryption key data associated with each of the chunks. The encryption key data associated with each of the chunks is distinct. The method also includes replacing each of the conventional branch instructions that specifies a target address that is within a different chunk than the chunk in which the conventional branch instruction resides with a branch and switch key instruction. The method also includes encrypting the program based on the chunk information. | 07-10-2014 |
| 20140195822 | MICROPROCESSOR THAT SECURELY DECRYPTS AND EXECUTES ENCRYPTED INSTRUCTIONS - A microprocessor is provided with a method for decrypting encrypted instruction data into plain text instruction data and securely executing the same. The microprocessor includes a master key register file comprising a plurality of master keys. Selection logic circuitry in the microprocessor selects a combination of at least two of the plurality of master keys. Key expansion circuitry in the microprocessor performs mathematical operations on the selected master keys to generate a decryption key having a long effective key length. Instruction decryption circuitry performs an efficient mathematical operation on the encrypted instruction data and the decryption key to decrypt the encrypted instruction data into plain text instruction data. | 07-10-2014 |
| 20140195823 | MICROPROCESSOR THAT FACILITATES TASK SWITCHING BETWEEN ENCRYPTED AND UNENCRYPTED PROGRAMS - A microprocessor includes an architected register having a bit. The microprocessor sets the bit. The microprocessor also includes a fetch unit that fetches encrypted instructions from an instruction cache and decrypts them prior to executing them, in response to the microprocessor setting the bit. The microprocessor saves the value of the bit to a stack in memory and then clears the bit, in response to receiving an interrupt. The fetch unit fetches unencrypted instructions from the instruction cache and executes them without decrypting them, after the microprocessor clears the bit. The microprocessor restores the saved value from the stack in memory to the bit in the architected register, in response to executing a return from interrupt instruction. The fetch unit resumes fetching and decrypting the encrypted instructions, in response to determining that the restored value of the bit is set. | 07-10-2014 |
| 20140297993 | UNCORE MICROCODE ROM - A microprocessor includes a plurality of processing cores each comprises a corresponding memory physically located inside the core and readable by the core but not readable by the other cores (“core memory”). The microprocessor also includes a memory physically located outside all of the cores and readable by all of the cores (“uncore memory”). For each core, the uncore memory and corresponding core memory collectively provide M words of storage for microcode instructions fetchable by the core as follows: the uncore memory provides J of the M words of microcode instruction storage, and the corresponding core memory provides K of the M words of microcode instruction storage. J, K and M are counting numbers, and M=J+K. The memories are non-architecturally-visible and accessed using a fetch address provided by a non-architectural program counter, and the microcode instructions are non-architectural instructions that implement architectural instructions. | 10-02-2014 |
| 20140298060 | ASYMMETRIC MULTI-CORE PROCESSOR WITH NATIVE SWITCHING MECHANISM - A processor includes first and second processing cores configured to support first and second respective subsets of features of its instruction set architecture (ISA) feature set. The first subset is less than all the features of the ISA feature set. The first and second subsets are different but their union is all the features of the ISA feature set. The first core detects a thread, while being executed by the first core rather than by the second core, attempted to employ a feature not in the first subset and, in response, to indicate a switch from the first core to the second core to execute the thread. The unsupported feature may be an unsupported instruction or operating mode. A switch may also be made if the lower performance/power core is being over-utilized or the higher performance/power core is being under-utilized. | 10-02-2014 |
| 20140351561 | MICROPROCESSOR THAT FUSES IF-THEN INSTRUCTIONS - A microprocessor includes an instruction translation unit that extracts condition information from the IT instruction and fuses the IT instruction with the first IT block instruction. For each instruction of the IT block, the instruction translation unit: determines a respective condition for the IT block instruction using the condition information extracted from the IT instruction and translates the IT block instruction into a microinstruction. The microinstruction includes the respective condition. Execution units conditionally execute the microinstruction based on the respective condition. For each IT block instruction, the instruction translation unit determines a respective state value using the extracted condition information. The state value comprises the lower eight bits of the IT instruction having the lower five bits left-shifted by N-1 bits, where N indicates a position of the IT block instruction in the IT block. | 11-27-2014 |
| 20150046680 | DYNAMIC AND SELECTIVE CORE DISABLEMENT AND RECONFIGURATION IN A MULTI-CORE PROCESSOR - A method for dynamically reconfiguring one or more cores of a multi-core microprocessor comprising a plurality of cores and sideband communication wires, extrinsic to a system bus connected to a chipset, which facilitate non-system-bus inter-core communications. At least some of the cores are operable to be reconfigurably designated with or without master credentials for purposes of structuring sideband-based inter-core communications. The method includes determining an initial configuration of cores of the microprocessor, which configuration designates at least one core, but not all of the cores, as a master core, and reconfiguring the cores according to a modified configuration, which modified configuration removes a master designation from a core initially so designated, and assigns a master designation to a core not initially so designated. Each core is configured to conditionally drive a sideband communication wire to which it is connected based upon its designation, or lack thereof, as a master core. | 02-12-2015 |
| 20150054543 | APPARATUS AND METHOD FOR RAPID FUSE BANK ACCESS IN A MULTI-CORE PROCESSOR - An apparatus includes a fuse array, a random access memory (RAM), and a plurality of cores. The fuse array is disposed on a die, where the fuse array has a plurality of semiconductor fuses programmed with compressed configuration data. The RAM is disposed separately on the die. The plurality of cores is disposed separately on the die, where each of the plurality of cores is coupled to the fuse array and the RAM, and where the each of the plurality of cores accesses either the fuse array or the RAM upon power-up/reset as indicated by contents of a load data register to obtain the compressed configuration data. | 02-26-2015 |
| 20150055395 | EXTENDED FUSE REPROGRAMMABILITY MECHANISM - An apparatus includes a semiconductor fuse array, disposed on a die, into which is programmed configuration data. The semiconductor fuse array has a first plurality of semiconductor fuses and a second plurality of semiconductor fuses. The first plurality of semiconductor fuses is configured to store the configuration data in an encoded and compressed format. The second plurality of semiconductor fuses is configured to store first fuse correction data that indicates locations and values corresponding to a first one or more fuses within the first plurality of fuses whose states are to be changed from that which was previously stored. | 02-26-2015 |
| 20150055427 | MULTI-CORE MICROPROCESSOR CONFIGURATION DATA COMPRESSION AND DECOMPRESSION SYSTEM - An apparatus has a fuse array, a device programmer, and a plurality of cores. The fuse array is disposed on a die, where the fuse array comprises a plurality of semiconductor fuses. The device programmer is coupled to the fuse array and is configured to access the configuration data, to compress the configuration data to yield compressed configuration data, and to program the fuse array with the compressed configuration data. The plurality of cores is disposed separately on the die and is coupled to the fuse array, where each of the plurality of cores accesses and decompresses all of the compressed configuration data upon power-up/reset, for initialization of elements within the each of the plurality of cores. | 02-26-2015 |
| 20150055428 | MICROPROCESSOR MECHANISM FOR DECOMPRESSION OF CACHE CORRECTION DATA - An apparatus has a fuse array, a cache memory, and cores. The fuse array is disposed on a die, into which is programmed the configuration data. The fuse array includes a first plurality of fuses and a second plurality of fuses. The first plurality of fuses stores compressed cache correction data. The second plurality of fuses stores compressed fuse correction data that indicates locations and values corresponding to one or more fuses within the first plurality of fuses whose states are to be changed from that which was previously stored. The cores are disposed on the die, where each of the cores accesses the fuse array upon power-up/reset. The each of the cores includes a cache fuses decompressor that changes the states according to the locations and the values, decompresses the compressed cache correction data, and distributes decompressed cached correction data to initialize the cache memory. | 02-26-2015 |
| 20150055429 | APPARATUS AND METHOD FOR COMPRESSION AND DECOMPRESSION OF MICROPROCESSOR CONFIGURATION DATA - An apparatus is contemplated for storing and providing configuration data to a microprocessor. The apparatus has a core, disposed on a die, and a fuse array, disposed on the die and coupled to the core, where the fuse array comprises a plurality of semiconductor fuses programmed with compressed configuration data for the core, where the compressed configuration data is generated by compression of data within a virtual fuse array that corresponds to the core, and where the core accesses and decompresses the compressed configuration data upon power-up/reset, for initialization of elements within the core. | 02-26-2015 |
| 20150058563 | MULTI-CORE FUSE DECOMPRESSION MECHANISM - An apparatus is contemplated for storing and decompressing configuration data in a multi-core microprocessor. The apparatus includes a shared fuse array and a plurality of microprocessor cores. The shared fuse array is disposed on a die and comprises a plurality of semiconductor fuses programmed with compressed configuration data. The plurality of microprocessor cores is also disposed on the die, where each of the plurality of microprocessor cores is coupled to the shared fuse array and is configured to access all of the compressed configuration data during power-up/reset, for initialization of elements within the each of the plurality of cores. The each of the plurality of cores have a reset controller that is configured to decompress the all of the compressed configuration data, and to distribute decompressed configuration data to initialize the elements. | 02-26-2015 |
| 20150058564 | APPARATUS AND METHOD FOR EXTENDED CACHE CORRECTION - An apparatus includes a semiconductor fuse array, a cache memory, and a plurality of cores. The semiconductor fuse array is disposed on a die, into which is programmed the configuration data. The semiconductor fuse array has a first plurality of semiconductor fuses that is configured to store compressed cache correction data. The a cache memory is disposed on the die. The plurality of cores is disposed on the die, where each of the plurality of cores is coupled to the semiconductor fuse array and the cache memory, and is configured to access the semiconductor fuse array upon power-up/reset, to decompress the compressed cache correction data, and to distribute decompressed cached correction data to initialize the cache memory. | 02-26-2015 |
| 20150058565 | APPARATUS AND METHOD FOR COMPRESSION OF CONFIGURATION DATA - An apparatus includes a device programmer, coupled to a plurality of semiconductor fuses disposed on a die, configured to program the plurality of semiconductor fuses with compressed configuration data for a plurality of cores disposed separately on the die. The device programmer has a virtual fuse array and a compressor. The virtual fuse array is configured to store the configuration data for the plurality of cores. The configuration data includes a plurality of data types. The compressor is coupled to the virtual fuse array and is configured to read the virtual fuse array, and is configured to compress the configuration data by employing a plurality of compression algorithms to generate the compressed configuration data, where the plurality of compression algorithms correspond to the plurality of data types. | 02-26-2015 |
| 20150058598 | APPARATUS AND METHOD FOR CONFIGURABLE REDUNDANT FUSE BANKS - An apparatus is contemplated for storing and providing configuration data to an integrated circuit device, the apparatus has a fuse array and a plurality of cores. The fuse array is disposed on a die. The fuse array has a first plurality of semiconductor fuses and a second plurality of semiconductor fuses. The plurality of cores is disposed on the die, where each of the plurality of cores is coupled to the fuse array. The each of the plurality of cores includes array control, configured to access the first and second pluralities of fuses, and configured to process first states of the first plurality of semiconductor fuses and second states of the second plurality of semiconductor fuses according to contents of a configuration data register. | 02-26-2015 |
| 20150058609 | APPARATUS AND METHOD FOR STORAGE AND DECOMPRESSION OF CONFIGURATION DATA - An apparatus includes a plurality of cores and a fuse array. The plurality of cores is disposed on a die. The fuse array is disposed on the die and is coupled to each of the plurality of cores, where the fuse array includes a plurality of semiconductor fuses that are programmed with compressed configuration data for the each of the plurality of cores, and where the each of the plurality of cores accesses and decompresses all of the compressed configuration data upon power-up/reset, for initialization of elements within the each of the plurality of cores. | 02-26-2015 |
| 20150058610 | CORE-SPECIFIC FUSE MECHANISM FOR A MULTI-CORE DIE - An apparatus including a plurality of cores and a fuse array. The plurality of cores is disposed on a die. The fuse array is disposed on the die and is coupled to each of the plurality of cores, where the fuse array includes a first plurality of semiconductor fuses and a second plurality of semiconductor fuses. The first plurality of semiconductor fuses is programmed with compressed configuration data for the each of the plurality of cores. The second plurality of semiconductor fuses is programmed with core designation data that associates some of the compressed configuration data with one of the plurality of cores, where the one of the plurality of cores accesses and decompresses the some of the compressed configuration data upon power-up/reset, for initialization of elements within the one of the plurality of cores. | 02-26-2015 |
| 20150058695 | CORRECTABLE CONFIGURATION DATA COMPRESSION AND DECOMPRESSION SYSTEM - An apparatus has a shared fuse array and a plurality of microprocessor cores. The shared fuse array is disposed on a die, the shared fuse array having a plurality of semiconductor fuses programmed with compressed configuration data and error checking and correction (ECC) codes. The plurality of microprocessor cores is disposed on the die, where each of the plurality of microprocessor cores is coupled to the shared fuse array and is configured to access all of the compressed configuration data during power-up/reset, for initialization of elements within the each of the plurality of cores. The each of the plurality of cores includes a reset controller that is configured to access the compressed configuration data and the ECC codes, to correct errors resulting in corrected compressed configuration data, to decompress all of the corrected compressed configuration data, and to distribute decompressed configuration data to initialize the elements. | 02-26-2015 |
| 20150067214 | SINGLE-CORE WAKEUP MULTI-CORE SYNCHRONIZATION MECHANISM - A microprocessor includes a plurality of cores, a shared cache memory, and a control unit that individually puts each core to sleep by stopping its clock signal. Each core executes a sleep instruction and responsively makes a respective request of the control unit to put the core to sleep, which the control unit responsively does, and detects when all the cores have made the respective request and responsively wakes up only the last requesting cores. The last core writes back and invalidates the shared cache memory and indicates it has been invalidated and makes a request to the control unit to put the last core back to sleep. The control unit puts the last core back to sleep and continuously keeps the other cores asleep while the last core writes back and invalidates the shared cache memory, indicates the shared cache memory was invalidated, and is put back to sleep. | 03-05-2015 |
| 20150067215 | MULTI-CORE SYNCHRONIZATION MECHANISM WITH INTERRUPTS ON SYNC CONDITION - A microprocessor includes a plurality of processing cores, each comprising a respective interrupt request input and a control unit configured to receive a respective synchronization request from each of the plurality of processing cores. The control unit is configured to generate an interrupt request to all of the plurality of processing cores on their respective interrupt request inputs in response to detecting that the control unit has received the respective synchronization request from all of the plurality of processing cores. | 03-05-2015 |
| 20150067219 | DYNAMIC DESIGNATION OF THE BOOTSTRAP PROCESSOR IN A MULTI-CORE MICROPROCESSOR - A microprocessor includes an indicator and a plurality of processing cores. Each of the plurality of processing cores is configured to sample the indicator. When the indicator indicates a first predetermined value, the plurality of processing cores are configured to collectively designate a default one of the plurality of processing cores to be a bootstrap processor. When the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to collectively designate one of the plurality of processing cores other than the default processing core to be the bootstrap processor. | 03-05-2015 |
| 20150067250 | MULTI-CORE HARDWARE SEMAPHORE - A microprocessor includes a plurality of processing cores, a resource shared by the plurality of processing cores, and a hardware semaphore readable and writeable by each of the plurality of processing cores within a non-architectural address space. Each of the plurality of processing cores is configured to write to the hardware semaphore to request ownership of the shared resource and to read from the hardware semaphore to determine whether or not the ownership was obtained. Each of the plurality of processing cores is configured to write to the hardware semaphore to relinquish ownership of the shared resource. | 03-05-2015 |
| 20150067263 | SERVICE PROCESSOR PATCH MECHANISM - A microprocessor includes a plurality of processing cores, a service processing unit and a memory accessible by both the service processing unit and the plurality of processing cores. At least one of the plurality of processing cores is configured to write a patch to the memory. The patch comprises one or more instructions to be fetched from the memory and executed by the service processing unit after written to the memory by the at least one of the plurality of processing cores. | 03-05-2015 |
| 20150067301 | MICROPROCESSOR WITH BOOT INDICATOR THAT INDICATES A BOOT ISA OF THE MICROPROCESSOR AS EITHER THE X86 ISA OR THE ARM ISA - A microprocessor includes a plurality of registers that holds an architectural state of the microprocessor and an indicator that indicates a boot instruction set architecture (ISA) of the microprocessor as either the x86 ISA or the Advanced RISC Machines (ARM) ISA. The microprocessor also includes a hardware instruction translator that translates x86 ISA instructions and ARM ISA instructions into microinstructions. The hardware instruction translator translates, as instructions of the boot ISA, the initial ISA instructions that the microprocessor fetches from architectural memory space after receiving a reset signal. The microprocessor also includes an execution pipeline, coupled to the hardware instruction translator. The execution pipeline executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions. In response to the reset signal, the microprocessor initializes its architectural state in the plurality of registers as defined by the boot ISA prior to fetching the initial ISA instructions. | 03-05-2015 |
| 20150067306 | INTER-CORE COMMUNICATION VIA UNCORE RAM - A microprocessor includes a plurality of processing cores and an uncore random access memory (RAM) readable and writable by each of the plurality of processing cores. Each core of the plurality of processing cores comprises microcode run by the core that implements architectural instructions of an instruction set architecture of the microprocessor. The microcode is configured to both read and write the uncore RAM to accomplish inter-core communication between the plurality of processing cores. | 03-05-2015 |
| 20150067307 | PROPAGATION OF UPDATES TO PER-CORE-INSTANTIATED ARCHITECTURALLY-VISIBLE STORAGE RESOURCE - A microprocessor a plurality of processing cores, wherein each of the plurality of processing cores instantiates a respective architecturally-visible storage resource. A first core of the plurality of processing cores is configured to encounter an architectural instruction that instructs the first core to update the respective architecturally-visible storage resource of the first core with a value specified by the architectural instruction. The first core is further configured to, in response to encountering the architectural instruction, provide the value to each of the other of the plurality of processing cores and update the respective architecturally-visible storage resource of the first core with the value. Each core of the plurality of processing cores other than the first core is configured to update the respective architecturally-visible storage resource of the core with the value provided by the first core without encountering the architectural instruction. | 03-05-2015 |
| 20150067310 | DYNAMIC RECONFIGURATION OF MULTI-CORE PROCESSOR - A microprocessor includes a plurality of processing cores and a configuration register configured to indicate whether each of the plurality of processing cores is enabled or disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a first instance to determine which of the plurality of processing cores is enabled or disabled and generate a respective configuration-related value based on the read of the configuration register in the first instance. The configuration register is updated to indicate that a previously enabled one of the plurality of processing cores is disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a second instance to determine which of the plurality of processing cores is enabled or disabled and generate the respective configuration-related value based on the read of the configuration register in the second instance. | 03-05-2015 |
| 20150067318 | SELECTIVE DESIGNATION OF MULTIPLE CORES AS BOOTSTRAP PROCESSOR IN A MULTI-CORE MICROPROCESSOR - A microprocessor includes an indicator and a plurality of processing cores. Each of the plurality of processing cores is configured to sample the indicator. When the indicator indicates a first predetermined value, the plurality of processing cores are configured to collectively designate multiple of the plurality of processing cores to be a bootstrap processor. When the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to collectively designate a single processing core of the plurality of processing cores to be the bootstrap processor. | 03-05-2015 |
| 20150067368 | CORE SYNCHRONIZATION MECHANISM IN A MULTI-DIE MULTI-CORE MICROPROCESSOR - A microprocessor includes a plurality of semiconductor dies, a bus coupling the plurality of semiconductor dies, and a plurality of processing cores. A distinct subset of the processing cores is located on each of the semiconductor dies. Each die comprises a control unit configured to selectively control a respective clock signal to each of the subset of cores of the die. For each core of the subset, in response to the core writing a value to the control unit, the control unit is configured to turn off the respective clock signal to the core and to write the value over the bus to the control unit of the other die. Collectively all of the control units are configured to simultaneously turn on the clock signals to all of the processing cores after the clock signals have been turned off to all of the processing cores. | 03-05-2015 |
| 20150067369 | MULTI-CORE SYNCHRONIZATION MECHANISM - A microprocessor includes a control unit configured to selectively control a respective clock signal to each of a plurality of processing cores. Each of the processing cores is configured to separately write a value to the control unit. For each core of the plurality of processing cores, the control unit is configured to turn off the respective clock signal to the core in response to the core writing a value to the control unit. The control unit is configured to detect a condition has occurred when all of the processing cores have written a value to the control unit and the control unit has turned off the respective clock signal to all of the processing cores. The control unit is configured to simultaneously turn on the respective clock signal to all of the processing cores in response to detecting the condition has occurred. | 03-05-2015 |
| 20150067666 | PROPAGATION OF MICROCODE PATCHES TO MULTIPLE CORES IN MULTICORE MICROPROCESSOR - A microprocessor includes a plurality of processing cores, wherein each of the plurality of processing cores executes microcode and comprises hardware to patch the microcode. A first core of the plurality of processing cores is configured to encounter an instruction that instructs the first core to apply a microcode patch. The first core of the plurality of processing cores is further configured to, in response to encountering the instruction, inform each core of the other of the plurality of processing cores of the microcode patch and apply the microcode patch to the hardware of the first core. Each core of the plurality of processing cores other than the first core is configured to apply the microcode patch to the hardware of the core, in response to being informed by the first core. | 03-05-2015 |
| 20150089204 | DYNAMICALLY RECONFIGURABLE MICROPROCESSOR - A microprocessor includes a plurality of dynamically reconfigurable functional units, a fingerprint, and a fingerprint unit. As the plurality of dynamically reconfigurable functional units execute instructions according to a first configuration setting, the fingerprint unit accumulates information about the instructions according to a mathematical operation to generate a result. The microprocessor also includes a reconfiguration unit that reconfigures the plurality of dynamically reconfigurable functional units to execute instructions according to a second configuration setting in response to an indication that the result matches the fingerprint. | 03-26-2015 |
