Shen, Hsin-Chu
Chang-Ho Shen, Hsin-Chu TW
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20130325480 | REMOTE CONTROLLER AND CONTROL METHOD THEREOF - A remote controller includes a housing, a direction sensor, a microphone, a controller, and a wireless transmitter. A control method of the remote controller includes detecting an angle between an axis of a remote controller and a vertical axis, enabling a microphone of the remote controller when the angle is within a predetermined range in order to generate a voice signal according to a voice command, and generating a first control signal according the voice signal and transmit the first control signal wirelessly. | 12-05-2013 |
20140184532 | DISPLAY SYSTEM AND CONTROL METHOD THEREOF - A display system includes a stylus pen and a touch screen module. The touch screen module includes a touch screen. A control method of the display system includes activating a command input mode of the display system by the stylus pen. An input command from the stylus pen to the touch screen is received by the touch screen after the command input mode is activated. Performer a corresponding operation corresponding to the input command on the touch screen according to which command among a plurality of predetermined commands of the display system to which the input command corresponds. | 07-03-2014 |
Cheng-Hui Shen, Hsin-Chu TW
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20110037000 | Method And Apparatus for Uniformly Implanting A Wafer With An Ion Beam - Initially, an ion beam is formed as an elongated shape incident on a wafer, where the shape has a length along a first axis longer than a diameter of the wafer, and a width along a second axis shorter than the diameter of the wafer. Then, a center of the wafer is moved along a scan path intersecting the ion beam at a movement velocity, and the wafer is rotated around at a rotation velocity simultaneously. During the simultaneous movement and rotation, the wafer is totally overlapped with the ion beam along the first axis when the wafer intersects with the ion beam, and the rotation velocity is at most a few times of the movement velocity. Both the movement velocity and the rotation velocity can be a constant or have a velocity profile relative to a position of the ion beam across the wafer. | 02-17-2011 |
20120196047 | DETERMINING RELATIVE SCAN VELOCITY TO CONTROL ION IMPLANTATION OF WORK PIECE - To select a relative velocity profile to be used in scanning an actual work piece with an ion implant beam of an ion implantation tool, the implantation of a virtual work piece is simulated. A dose distribution is calculated across the virtual work piece based on an implant beam profile and a relative velocity profile. A new relative velocity profile is then determined based on the calculated dose distribution and the relative velocity profile used in calculating the dose distribution. A new dose distribution is then calculated using the new relative velocity profile. A new relative velocity profile is determined and a corresponding new dose distribution is calculated iteratively until the new dose distribution meets one or more predetermined criteria. The new relative velocity profile is stored as the selected relative velocity profile when the new dose distribution meets the one or more predetermined criteria. | 08-02-2012 |
Chia-I Shen, Hsin-Chu TW
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20130084657 | Plasma Density Control - A first embodiment is a method for semiconductor processing. The method comprises forming a component on a wafer in a chamber; determining a non-uniformity of the plasma in the chamber, the determining being based at least in part on the component on the wafer; and providing a material on a surface of the chamber corresponding to the non-uniformity. The forming the component includes using a plasma. The material can have various shapes, compositions, thicknesses, and/or placements on the surface of the chamber. Other embodiments include a chamber having a material on a surface to control a plasma uniformity. | 04-04-2013 |
Chi-Chih Shen, Hsin-Chu TW
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20140210069 | CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - The present invention discloses a chip package and a manufacturing method thereof. The chip package includes: a semiconductor chip having an upper surface and a lower surface opposite to each other; a metal heat conductive layer formed on the lower surface, for conducting or absorbing heat generated by the semiconductor chip; and a bond pad formed on the upper surface, for electrically connecting to a circuit in the semiconductor chip. | 07-31-2014 |
Chien-Chi Shen, Hsin-Chu TW
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20090237947 | LAMP POSITION ADJUSTMENT DEVICE AND LAMP MODULE HAVING THE SAME - A lamp position adjustment device includes a bottom frame, a lamp holder, and a lamp mount. The lamp holder is disposed on the bottom frame for supporting the lamp, and the lamp mount is disposed between the lamp holder and the bottom frame. The lamp mount includes a base portion, a first side portion and a second side portion that are respectively connected to two opposite sides of the base portion, a first positioning mechanism, and a second positioning mechanism. The first positioning mechanism is disposed on the base portion to enable the lamp mount to be slidably connected to the bottom frame, and the second positioning mechanism is disposed on the first side portion and the second side portion to enable the lamp mount to be slidably connected to the lamp holder. | 09-24-2009 |
Chung-Min Shen, Hsin-Chu TW
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20140347586 | LIQUID CRYSTAL DISPLAY DEVICE - A liquid crystal display device includes a first substrate, a second substrate, and a plurality of spacers. The first substrate includes a plurality of pixel units, which include at least two gate lines, and two neighboring thin film transistors connected to two gate lines, respectively. The second substrate is opposed to the first substrate. At least one of the spacers overlaps with at least a part of the first thin film transistor and at least a part of the second thin film transistor in a top view. | 11-27-2014 |
Horng-Daw Shen, Hsin-Chu TW
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20130001722 | Co-implant for Backside Illumination Sensor - A system and method for image sensing is disclosed. An embodiment comprises a substrate with a pixel region, the substrate having a front side and a backside. A co-implant process is performed along the backside of the substrate opposing a photosensitive element positioned along the front side of the substrate. The co-implant process utilizes a first pre-amorphization implant process that creates a pre-amorphization region. A dopant is then implanted wherein the pre-amorphization region retards or reduces the diffusion or tailing of the dopants into the photosensitive region. An anti-reflective layer, a color filter, and a microlens may also be formed over the co-implant region. | 01-03-2013 |
20130249037 | Co-implant for Backside Illumination Sensor - A system and method for image sensing is disclosed. An embodiment comprises a substrate with a pixel region, the substrate having a front side and a backside. A co-implant process is performed along the backside of the substrate opposing a photosensitive element positioned along the front side of the substrate. The co-implant process utilizes a first pre-amorphization implant process that creates a pre-amorphization region. A dopant is then implanted wherein the pre-amorphization region retards or reduces the diffusion or tailing of the dopants into the photosensitive region. An anti-reflective layer, a color filter, and a microlens may also be formed over the co-implant region. | 09-26-2013 |
Hsin-An Shen, Hsin-Chu TW
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20140041918 | Looped Interconnect Structure - Disclosed herein is a system and method for mounting packages by forming one or more wire loop interconnects, optionally, with a wirebonder, and mounting the interconnects to a mounting pad on a first substrate. A first and second stud ball may each have at least one flat surface be disposed on a single mounting pad, and a wire having a bend region and forming a loop may be disposed between the stud balls. The stud balls may be formed from a deformed mouthing node formed on a wire. The loop may be mounted on a mounting pad on a first substrate and a second substrate may be mounted on the loop via a conductive material such as solder. | 02-13-2014 |
Kuo-Liang Shen, Hsin-Chu TW
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20110279440 | CIRCUIT FOR AMPLIFYING A DISPLAY SIGNAL TO BE TRANSMITTED TO A REPAIR LINE BY USING A NON-INVERTING AMPLIFIER AND LCD DEVICE USING THE SAME - A circuit for amplifying a display signal transmitted to a repair line by using a non-inverting amplifier is disclosed, which comprises a voltage follower, a non-inverting amplifier, a repair line, a thin film transistor (TFT) and a liquid crystal (LC) capacitor. The voltage follower is electrically connected to a data driver chip to thereby provide a display signal to the non-inverting amplifier. The non-inverting amplifier amplifies the display signal to thus obtain an amplified display signal, and transmits the amplified display signal to the TFT and the LC capacitor through the repair line. The amplified display signal is kept at a desired voltage level when the LC capacitor receives the amplified display signal. | 11-17-2011 |
Meng-Hung Shen, Hsin-Chu TW
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20150332962 | Structure and Method for Semiconductor Device - Provided is a semiconductor device and methods of forming the same. The semiconductor device includes a substrate having source/drain regions and a channel region between the source/drain regions; a gate structure over the substrate and adjacent to the channel region; source/drain contacts over the source/drain regions and electrically connecting to the source/drain regions; and a contact protection layer over the source/drain contacts. The gate structure includes a gate stack and a spacer. A top surface of the source/drain contacts is lower than a top surface of the spacer, which is substantially co-planar with a top surface of the contact protection layer. The contact protection layer prevents accidental shorts between the gate stack and the source/drain regions when gate vias are formed over the gate stack. Therefore, gate vias may be formed over any portion of the gate stack, even in areas that overlap the channel region from a top view. | 11-19-2015 |
Ming-Huei Shen, Hsin-Chu TW
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20150115215 | Phase Change Memory and Method of Fabricating Same - A phase change memory (“PCM”) cell is provided in accordance with some embodiments. The PCM includes a spacer defining a reaction area; a phase change material layer disposed within the reaction area; a protection layer disposed over the phase change material layer and within the reaction area defined by the spacer; and a capping layer disposed over the protection layer and the spacer. | 04-30-2015 |
Pei-Yi Shen, Hsin-Chu TW
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20130015449 | PIXEL STRUCTURE AND METHOD OF FABRICATING THE SAMEAANM Lee; Chien-ChihAACI Hsin-ChuAACO TWAAGP Lee; Chien-Chih Hsin-Chu TWAANM Shen; Pei-YiAACI Hsin-ChuAACO TWAAGP Shen; Pei-Yi Hsin-Chu TWAANM Cheng; Ching-YangAACI Hsin-ChuAACO TWAAGP Cheng; Ching-Yang Hsin-Chu TWAANM Huang; Shu-MingAACI Hsin-ChuAACO TWAAGP Huang; Shu-Ming Hsin-Chu TW - The present invention provides a pixel structure including a substrate, a patterned electrode disposed on the substrate, a first insulating layer disposed on the patterned electrode, a common electrode disposed on the first insulating layer, a second insulating layer disposed on the common electrode, and a drain disposed on the second insulating layer. The first insulating layer has a first through hole, and the second insulating layer has a second through hole. The drain includes a first portion electrically connected to the patterned electrode via the first through hole and the second through hole, and a second portion extending onto the common electrode. The common electrode is coupled with the patterned electrode to form a first storage capacitor and is coupled with the second portion to form a second storage capacitor. | 01-17-2013 |
20130323889 | METHOD OF FABRICATING PIXEL STRUCTURE - The present invention provides a pixel structure including a substrate, a patterned electrode disposed on the substrate, a first insulating layer disposed on the patterned electrode, a common electrode disposed on the first insulating layer, a second insulating layer disposed on the common electrode, and a drain disposed on the second insulating layer. The first insulating layer has a first through hole, and the second insulating layer has a second through hole. The drain includes a first portion electrically connected to the patterned electrode via the first through hole and the second through hole, and a second portion extending onto the common electrode. The common electrode is coupled with the patterned electrode to form a first storage capacitor and is coupled with the second portion to form a second storage capacitor. | 12-05-2013 |
Po-Yuan Shen, Hsin-Chu TW
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20090237608 | SPACER STRUCTURE OF A DISPLAY PANEL - A spacer structure of a display panel includes a first substrate, a second substrate, a spacer, and a spacer pad. The spacer is disposed on a side of the first substrate facing the second substrate, and the spacer pad is disposed between the second substrate and the spacer. The spacer pad has a non-linear structure lodged in the spacer, and therefore restrains the spacer from moving with respect to the second substrate in the plane parallel to the surface of the second substrate. | 09-24-2009 |
20100007843 | SPACER STRUCTURE - A spacer structure includes a first substrate, an overcoat layer, first spacers, second spacers, and a second substrate. The first spacers are disposed in a first region, and the overcoat layer has a first thickness in the first region. The second spacers are disposed in a second region, and the overcoat layer has a second thickness in the second region. The first spacers and the second spacers have the same height, and the first thickness is greater than the second thickness. Accordingly, no gap exists between each of the first spacers and the second substrate; however, a gap exists between each or the second spacers and the second substrate. | 01-14-2010 |
20150187895 | THIN FILM TRANSISTOR STRUCTURE - A thin film transistor structure includes a substrate, a gate structure, a semiconductor active layer, a drain structure and a source structure. The gate structure and the semiconductor active layer are disposed above the substrate. The drain structure and the source structure are disposed on a first surface of the semiconductor active layer. At least a gap is formed between the source structure and the drain structure. The gap is extended along the first surface of the semiconductor active layer and is located in a projection area of the gate structure. A first portion of the gap includes a first straight segment, a first curved segment and a second curved segment. The first curved segment and the second curved segment are connected to a first end and a second end of the first straight segment, respectively. The first curved segment and the second curved segment have opposite bending directions. | 07-02-2015 |
Shih-Haur Shen, Hsin-Chu TW
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20090061743 | METHOD OF SOFT PAD PREPARATION TO REDUCE REMOVAL RATE RAMP-UP EFFECT AND TO STABILIZE DEFECT RATE - A method and apparatus for pre-conditioning a new soft polishing pad and processing a substrate on a soft polishing pad is described. The method includes coupling a soft polishing pad to a platen, contacting the processing surface of the soft polishing pad with a conditioning disk, applying a pressure conditioning disk, removing the conditioning disk from contact with the processing surface of the soft polishing pad, and contacting a first substrate with the processing surface of the soft polishing pad to perform a polishing process on the first substrate. | 03-05-2009 |
Shih-Haur Walters Shen, Hsin-Chu TW
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20090057264 | HIGH THROUGHPUT LOW TOPOGRAPHY COPPER CMP PROCESS - Embodiments described herein generally provide a method for processing metals disposed on a substrate in a chemical mechanical polishing system. The apparatus advantageously facilitates efficient bulk and residual conductive material removal from a substrate. In one embodiment a method for chemical mechanical polishing (CMP) of a conductive material disposed on a substrate is provided. A substrate comprising a conductive material disposed over an underlying barrier material is positioned on a first platen containing a first polishing pad. The substrate is polished on a first platen to remove a bulk portion of the conductive material. A rate quench process is performed in order to reduce a metal ion concentration in the polishing slurry. The substrate is polished on the first platen to breakthrough the conductive material exposing a portion of the underlying barrier material. | 03-05-2009 |
20140004626 | TEMPERATURE CONTROL OF CHEMICAL MECHANICAL POLISHING | 01-02-2014 |
Shih-Ming Shen, Hsin-Chu TW
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20150311264 | DISPLAY PANEL AND PIXEL ARRAY THEREOF - A pixel array includes a plurality of pixel groups, each of which includes a plurality of brightness sub-pixel regions, a plurality of first sub-pixel regions, and a plurality of second sub-pixel regions. Each brightness sub-pixel regions has a first side, a second side, a third side, and a fourth side. The first sub-pixel regions include a first group and a second group, and the second sub-pixel regions include a third group and a fourth group. The first, the second, the third, and the fourth groups are respectively disposed at the first, the third, the second, and the fourth sides of the first brightness sub-pixel region. Extension lines of long directions of the first, the second, the third, and the fourth groups respectively interlace a vertical baseline at a first angle θ1, a second angle θ2, a third angle θ3, and a fourth angle θ4. 0°<θ1<90°, 0°<θ2<90°, 0°<θ3<90°, and 0°<θ4<90°. | 10-29-2015 |
Tzer-Min Shen, Hsin-Chu TW
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20140131812 | Source and Drain Dislocation Fabrication in FinFETs - A device includes a semiconductor fin over a substrate, a gate dielectric on sidewalls of the semiconductor fin, and a gate electrode over the gate dielectric. A source/drain region is on a side of the gate electrode. A dislocation plane is in the source/drain region. | 05-15-2014 |
Wei-Tai Shen, Hsin-Chu TW
Yi-Lun Shen, Hsin-Chu TW
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20080298088 | DC TO DC CONVERTER WITH LOAD OPEN DETECTION AND RELATED METHOD THEREOF - Disclosed is a DC to DC converter, which comprises: a transforming circuit, for transforming an input voltage to an output voltage; a comparator, for comparing a reference voltage and a feedback voltage proportional to the output voltage to generate a comparing signal; a control circuit, coupled to the transforming circuit and the comparator, for controlling the transforming circuit according to the comparing signal; and a time-counting device, coupled to the control circuit, for counting the time of a specific voltage level of the comparing signal; wherein the time-counting device informs the control circuit that a load open situation occurs if the specific voltage level of the comparing signal lasts a predetermined time, then the control circuit turns off the transforming circuit. | 12-04-2008 |
20090180219 | APPARATUS FOR DETECTING ERROR OCCURRING TO POWER CONVERTER AND DETECTING METHOD THEREOF - An apparatus is applicable to a power converter comprising a primary winding for receiving an input voltage and a secondary winding for generating an output voltage to power a load. The apparatus comprises a detecting circuit, a comparing circuit, and a determining circuit. The detecting circuit is configured to generate a feedback signal according to the output voltage. The comparing circuit is coupled to the detecting circuit and configured to compare the feedback signal and a threshold and accordingly generates an indication signal indicative of the over high output voltage. The determining circuit, which is in response to the indication signal, is configured to trigger an over voltage protection mechanism preventing the power converter from powering the load. Since the feedback signal is instantly responsive to the output voltage, the occurrence of an error can be rapidly and correctly detected, allowing rapid and correct protection for the power converter. | 07-16-2009 |
20090279329 | DIGITAL LATCH CONTROL CIRCUIT FOR OVER-VOLTAGE PROTECTION AND POWER CONVERTER USING THE CONTROL CIRCUIT - An AC/DC power supply with over-voltage protection includes a voltage converting circuit and a digital latch control circuit. The voltage converting circuit has a first-side winding, a second-side winding, and an auxiliary winding for providing a supply voltage according to the AC input voltage. The digital latch control circuit is coupled to the voltage converting circuit and utilized for latching a voltage level of the supply voltage at a first predetermined level according to an over-voltage protection (OVP) trigger signal, where the voltage converting circuit is disabled when the voltage level is latched at the first predetermined level. | 11-12-2009 |
20090284180 | DRIVING CIRCUIT FOR LIGHT EMITTING DEVICE WITH COMPENSATION MECHANISM AND DRIVING METHOD THEREOF - A light emitting device driving circuit, includes: a switch device, a comparator, a driving module, a time counting circuit and a compensation module. The switch device is turned on or off according to a control signal for controlling a driving current flowing through the light emitting device. The comparator generates a comparison result according to a reference voltage and a feedback voltage corresponding to the driving current. The driving module generates the control signal according to the comparison result. The time counting circuit controls the driving module to turn on the switch device after the switch device turns off for a predetermined time. The compensation module detects a turn on time for the switch device and a delay time between the feedback voltage reaching the reference voltage value and the control signal varying correspondingly, and adjusts the reference voltage according to the turn on time and the delay time. | 11-19-2009 |
20100237960 | FREQUENCY-JITTERING APPARATUSES, FREQUENCY-JITTERING METHODS AND POWER MANAGEMENT DEVICES - A frequency-jittering apparatuses includes an oscillator and a frequency control circuit. The oscillator generates a signal. When the magnitude of the signal exceeds a magnitude of a reference signal, the oscillator operates substantially in a first state; and when the magnitude of the signal is lower than the magnitude of the reference signal, the oscillator operates substantially in a second state different from the first one. The frequency control circuit varies the reference signal to change the frequency of the signal output from the oscillator. | 09-23-2010 |
20110032024 | Integrated Circuit and Related Method for Determining Operation Modes - An integrated circuit and a related method for determining an operation mode are disclosed. The exemplified integrated circuit includes a controller, a multi-function pin, and a mode determination circuit. The controller controls a power switch and is being set to operate in one of the operation modes including a first operation mode and a second operation mode. The multi-function pin is connected to an external resistor. The mode determination circuit detects a signal from the multi-function pin. The signal represents the resistance of the external resistor. If the resistance is within a first range, the controller is operated in the first operation mode. If the resistance is within a second range, the controller is operated in the second operation mode. | 02-10-2011 |
20120019329 | Frequency-jittering apparatuses, frequency-jittering methods and power management devices - A frequency-jittering apparatuses includes an oscillator and a frequency control circuit. The oscillator generates a signal. When the magnitude of the signal exceeds a magnitude of a reference signal, the oscillator operates substantially in a first state; and when the magnitude of the signal is lower than the magnitude of the reference signal, the oscillator operates substantially in a second state different from the first one. The frequency control circuit varies the reference signal to change the frequency of the signal output from the oscillator. | 01-26-2012 |
20120300499 | CONTROL CIRCUIT OF A SWITCHED-MODE POWER CONVERTER AND METHOD THEREOF - A method for controlling voltage crossing a power switch of a switched-mode power converter is disclosed. The method comprises the steps of: controlling a switch frequency of a power switch of a switched-mode power converter to a first frequency as activating the switched-mode power converter; and changing the switch frequency of the power switch to a second frequency after a specific amount of time; wherein the first frequency is lower than the second frequency. | 11-29-2012 |
20130094254 | METHODS AND POWER CONTROLLERS FOR PRIMARY SIDE CONTROL - Power controllers and related primary-side control methods are disclosed. A disclosed power controller has a comparator and an ON-triggering controller. The comparator compares a feedback voltage with an over-shot reference voltage. Based on an inductance-coupling effect, the feedback voltage represents a secondary-side voltage of a secondary winding. Coupled to the comparator, the ON-triggering controller operates a power switch at about a first switching frequency when the feedback voltage is lower than the over-shot reference voltage. The ON-triggering controller operates the power switch at about a second switching frequency when the feedback voltage exceeds the over-shot reference voltage. The second switching frequency is less than the first switching frequency. | 04-18-2013 |
20130301303 | POWER CONTROLLERS AND CONTROL METHODS - Disclosed include power controllers and related control methods. A disclosed power controller has a pulse generator, a sample/hold device, a comparator, and a switch controller. The pulse generator provides an enable signal, defining an enable time. The comparator has two inputs capable of being coupled to a reference signal and a feedback signal, respectively, and an output coupled to a compensation capacitor. When enabled by the enable signal, the comparator charges/discharges the compensation capacitor. The switch controller controls a power switch according to a compensation voltage of the compensation capacitor. A feedback voltage of the feedback signal is able to correspond to an output voltage of the power supply. | 11-14-2013 |
20140043081 | SAMPLE-AND-HOLD CIRCUIT FOR GENERATING A VARIABLE SAMPLE DELAY TIME OF A TRANSFORMER AND METHOD THEREOF - A sample-and-hold circuit for generating a variable sample delay time of a transformer includes a discharge detection unit, a sample delay time generation unit, and a comparator. The discharge detection unit generates a first voltage according to a first turning-on signal and a first reference current. Length of the first turning-on signal is varied with a discharge time of a present period of the transformer. The sample delay time generation unit generates a second voltage according to the first turning-on signal and a second reference current. The comparator generates a sample signal to a control circuit of the transformer according to a first voltage corresponding to a previous period of the transformer and a second voltage corresponding to the present period of the transformer. The first reference current is K times the second reference current, and 002-13-2014 | |
20140140108 | CONTROLLER FOR GENERATING JITTERS IN A CONSTANT CURRENT MODE OF A POWER CONVERTER AND METHOD THEREOF - A controller for generating jitters in a constant current mode of a power converter includes a current pin, an auxiliary pin, a constant current control unit, and a control signal generation unit. The current pin is used for receiving a primary side voltage determined according to a resistor and a primary side current flowing through the power converter. The auxiliary pin is used for receiving a voltage corresponding to an auxiliary winding of the power converter. The constant current control unit is used for generating an adjustment signal according to the primary side voltage, a discharge time corresponding to the voltage, and a reference voltage. The reference voltage has a predetermined range jitter voltage. The control signal generation unit is used for adjusting a period of a gate control signal according to the adjustment signal. | 05-22-2014 |
20150029763 | CONTROLLER FOR GENERATING JITTERS IN A QUASI RESONANT MODE AND METHOD FOR GENERATING JITTERS IN A QUASI RESONANT MODE - A controller for generating jitters in a quasi resonant mode includes a feedback pin, a voltage generation unit, a pulse generator, and a comparator. The feedback pin is used for receiving a feedback voltage from a secondary side of a power converter. The voltage generation unit is used for generating a first voltage according to the feedback voltage and a pulse. The pulse generator is used for generating the pulse when a control signal controlling a power switch of a primary side of the power converter is enabled. The comparator is used for controlling enabling and disabling of a switching signal according to the first voltage and a variable reference voltage. The variable reference voltage is monotonously swung within a predetermined range according to a digital signal. | 01-29-2015 |