Patent application number | Description | Published |
20120299013 | SEMICONDUCTOR LIGHT EMITTING STRUCTURE - A semiconductor light emitting structure including a substrate, a patterned structure, a first semiconductor layer, an active layer and a second semiconductor layer is provided. The patterned structure is protruded from or indented into a surface of the substrate, so that the surface of the substrate becomes a roughed surface. The patterned structure has an asymmetrical geometric shape. The first semiconductor layer is disposed on the roughed surface. The active layer is disposed on the first semiconductor layer. The second semiconductor is disposed on the active layer. | 11-29-2012 |
20130048941 | SOLID STATE LIGHT EMITTING SEMICONDUCTOR STRUCTURE AND EPITAXY GROWTH METHOD THEREOF - A solid state light emitting semiconductor structure and an epitaxy growth method thereof are provided. The method includes the following steps: A substrate is provided. A plurality of protrusions separated from each other are formed on the substrate. A buffer layer is formed on the protrusions, and fills or partially fills the gaps between the protrusions. A semiconductor epitaxy stacking layer is formed on the buffer layer, wherein the semiconductor epitaxy stacking layer is constituted by a first type semiconductor layer, an active layer and a second type semiconductor layer in sequence. | 02-28-2013 |
20130062634 | SOLID STATE LIGHT SOURCE MODULE AND ARRAY THEREOF - A solid state light source array including a transparent substrate and N rows of solid state light emitting element series is provided. Each row of the solid state light emitting element series includes M solid state light emitting elements connected in series, wherein N, M are integrals and N≧1, M≧2. Each of the solid state emitting elements includes a first type electrode pad and a second type electrode pad. The first and the M | 03-14-2013 |
20130095591 | MANUFACTURING METHOD OF SOLID STATE LIGHT EMITTING ELEMENT - A manufacturing method of a solid state light emitting element is provided. A plurality of protrusion structures separated to each other are formed on a first substrate. A buffer layer is formed on the protrusion structures and fills the gaps between protrusion structures. An epitaxial growth layer is formed on the buffer layer to form a first semiconductor stacking structure. The first semiconductor stacking structure is inverted to a second substrate, so that the first semiconductor epitaxial layer and the second substrate are connected to form a second semiconductor stacking structure. The buffer layer is etched by a first etchant solution to form a third semiconductor stacking structure. A second etchant solution is used to permeate through the gaps between the protrusion structures, so that the protrusion structures are etched completely. The first substrate is removed from the third semiconductor stacking structure to form a fourth semiconductor stacking structure. | 04-18-2013 |
20130328010 | LIGHT-EMITTING DIODE AND METHOD FOR MANUFACTURING THE SAME - A high brightness light-emitting diode free of p-type gallium nitride (GaN) layer is provided, which includes an n-type semiconductor layer, a multi-quantum well (MQW) layer, a p-type indium gallium nitride (InGaN) layer and an indium tin oxide (ITO) layer. The grain size of the ITO layer is ranging from 5 to 1000 angstroms. A method for manufacturing the high brightness light-emitting diode is also provided. | 12-12-2013 |
20130328057 | LIGHT EMITTING DIODE AND METHOD OF FABRICATING THE SAME - Disclosed herein is a light emitting diode, the structure of the light emitting diode comprises a substrate, a first-type semiconductor layer, a structural layer, a light emitting layer, a second-type semiconductor layer, a transparent conductive layer, a first contact pad and a second contact pad in regular turn. The structural layer comprises a stacked structure having a trapezoid sidewall and nano columns extending from the trapezoid sidewall in regular arrangement. Also, a method for fabricating the light emitting diode is disclosed. | 12-12-2013 |
20130341589 | LIGHT EMITTING DIODE AND METHOD FOR MANUFACTURING THE SAME - A light emitting diode includes a substrate, a first-type semiconductor layer, a nanorod layer and a transparent planar layer. The first-type semiconductor layer is disposed over the substrate. The nanorod layer is formed on the first-type semiconductor layer. The nanorod layer includes a plurality of nanorods and each of the nanorods has a quantum well structure and a second-type semiconductor layer. The quantum well structure is in contact with the first-type semiconductor layer, and the second-type semiconductor layer is formed on the quantum well structure. The transparent planar layer is filled between the nanorods. A surface of the second-type semiconductor layer is exposed out of the transparent planar layer. | 12-26-2013 |
20140027802 | LIGHT EMITTING DIODE WITH UNDERCUT AND MANUFACTURING METHOD THEREOF - An LED with undercut includes a first semiconductor layer, an illumination layer, a second semiconductor layer, a first electrode and a second electrode. The first semiconductor layer includes a first area and a second area. A first acute angle is included between a first slanted wall and a first top surface of the first area. The illuminating layer is formed on the second area. The second semiconductor is formed on the illuminating layer. The first and second electrodes are respectively formed on the first top surface and the second semiconductor layer. The first semiconductor layer on the second area, the illuminating layer and the second semiconductor layer on the first semiconductor layer form a MESA structure. The MESA structure includes a second slanted wall adjacent to the first area. A second acute angle is included between the second slanted wall and the first top surface. | 01-30-2014 |
20140070241 | SOLID STATE LIGHT SOURCE ARRAY - A solid state light source array including a transparent substrate and N rows of solid state light emitting element series is provided. Each row of the solid state light emitting element series includes M solid state light emitting elements connected in series, wherein N, M are integers and N≧1, M≧2. Each of the solid state emitting elements includes a first type electrode pad and a second type electrode pad. The first and the M | 03-13-2014 |
20150079716 | LIGHT EMITTING DIODE AND METHOD FOR MANUFACTURING THE SAME - A light emitting diode includes a substrate, a first-type semiconductor layer, a nanorod layer and a transparent planar layer. The first-type semiconductor layer is disposed over the substrate. The nanorod layer is formed on the first-type semiconductor layer. The nanorod layer includes a plurality of nanorods and each of the nanorods has a quantum well structure and a second-type semiconductor layer. The quantum well structure is in contact with the first-type semiconductor layer, and the second-type semiconductor layer is formed on the quantum well structure. The transparent planar layer is filled between the nanorods. A surface of the second-type semiconductor layer is exposed out of the transparent planar layer. | 03-19-2015 |
20150280064 | LIGHT EMITTING DIODE AND METHOD OF FABRICATING THE SAME - Disclosed herein is a light emitting diode, the structure of the light emitting diode comprises a substrate, a first-type semiconductor layer, a structural layer, a light emitting layer, a second-type semiconductor layer, a transparent conductive layer, a first contact pad and a second contact pad in regular turn. The structural layer comprises a stacked structure having a trapezoid sidewall and nano columns extending from the trapezoid sidewall in regular arrangement. Also, a method for fabricating the light emitting diode is disclosed. | 10-01-2015 |
Patent application number | Description | Published |
20130187718 | AMPLIFIER CIRCUIT AND METHOD FOR IMPROVING THE DYNAMIC RANGE THEREOF - The invention provides an amplifier circuit. In one embodiment, the amplifier circuit includes a first class-AB amplifier and a second class-AB amplifier. The first class-AB amplifier amplifies an input signal to generate the first output signal. The second class-AB amplifier amplifies the first output signal to generate a final output signal on an output node. When the power of the input signal is greater than a threshold level, the second class-AB amplifier is in a turned-off state during a turned-on duration period of the first class-AB amplifier, and the first class-AB amplifier is in a turned-off state during a turned-on duration period of the second-class AB amplifier. | 07-25-2013 |
20130188755 | RECEIVER - A receiver includes a low noise amplifier (LNA), a passive mixer, a passive filter, a baseband processing block and a voltage controller. The LNA receives and amplifies a radio frequency (RF) signal. The passive mixer is coupled to the LNA without any AC coupling capacitance therebetween, and generates an intermediate frequency signal by down-converting the RF signal. The passive filter filters the intermediate frequency signal. The baseband processing block includes a transimpedance amplifier (TIA) and processes the filtered intermediate frequency signal. The voltage controller keeps a first node and a second node of a signal path to be around a common DC voltage, wherein the first node is located between an output terminal of the LNA and an input terminal of the passive mixer, and the second node is located between an output terminal of the passive mixer and an output terminal of the TIA. | 07-25-2013 |
20140362482 | ELECTROSTATIC DISCHARGE STRUCTURE FOR ENHANCING ROBUSTNESS OF CHARGE DEVICE MODEL AND CHIP WITH THE SAME - An ESD (Electrostatic discharge) structure for enhancing robustness of CDM (Charge Device Model) at least includes an input stage. The input stage includes an input pad, a first ESD clamp circuit, a second ESD clamp circuit, a resistor, and a transistor. The input pad is configured to receive an input signal. The first ESD clamp circuit is coupled between the input pad and a work voltage. The second ESD clamp circuit is coupled between the input pad and a ground voltage. The first clamp circuit and the second clamp circuit are capable of bypassing an electrostatic current. The transistor has a first source/drain, a second source/drain, a gate coupled to the input pad, and a bulk coupled through the resistor to the work voltage or the ground voltage. | 12-11-2014 |
Patent application number | Description | Published |
20090295419 | MEMORY CHIP AND METHOD FOR OPERATING THE SAME - A memory chip and method for operating the same are provided. The memory chip includes a number of pads. The method includes inputting a number of first test signals to the pads respectively, wherein the first test signals corresponding to two physically-adjacent pads are complementary; inputting a number of second test signals, respectively successive to the first test signals, to the pads, wherein the first test signal and the second test signal corresponding to each of the pads are complementary; and outputting expected data from the memory chip if the first test signals and the second test signals are successfully received by the memory chip. | 12-03-2009 |
20110038218 | Memory Chip and Method for Operating the Same - A memory chip and method for operating the same are provided. The memory chip includes a number of pads. The method includes inputting a number of first test signals to the pads respectively, wherein the first test signals corresponding to two physically-adjacent pads are complementary; inputting a number of second test signals, respectively successive to the first test signals, to the pads, wherein the first test signal and the second test signal corresponding to each of the pads are complementary; and outputting expected data from the memory chip if the first test signals and the second test signals are successfully received by the memory chip. | 02-17-2011 |
20110069571 | Word Line Decoder Circuit Apparatus and Method - One embodiment of the technology is an apparatus, a memory integrated circuit. The memory integrated circuit has word line address decoding circuitry. The circuit allows selection of a single word line to have an erase voltage. A decoder circuit includes an inverter and logic. The inverter has an input, and an output controlling a word line to perform the erase operation. A voltage range of the input extends between a first voltage reference and a second voltage reference. Examples of voltages references are a voltage supply and a ground. In some embodiments, this wide voltage range results from the input being free of a threshold voltage drop from preceding circuitry limiting the voltage range of the input. The logic of the decoder is circuit is controlled by a word line address to determine a value of the input of the inverter during the erase operation. | 03-24-2011 |
20110227552 | Apparatus of Supplying Power and Method Therefor - A power supply apparatus and a method for supplying power are provided. The apparatus, for use in a system having a first power signal, includes an assistance unit and a power supply device. The assistance unit outputs at least one maintaining signal according to the first power signal selectively. The power supply device outputs a second power signal, wherein the power supply device maintains the second power signal according to the at least one maintaining signal, for example, in an inactive state, such as an idle or standby state or other suitable timing. | 09-22-2011 |
20120057410 | Method and Apparatus for the Erase Suspend Operation - Various aspects of a nonvolatile memory have an improved erase suspend procedure. A bias arrangement is applied to word lines of an erase sector undergoing an erase procedure interrupted by an erase suspend procedure. As a result, another operation performed during erase suspend, such as a read operation or program operation, has more accurate results due to decreased leakage current from any over-erased nonvolatile memory cells of the erase sector. | 03-08-2012 |
Patent application number | Description | Published |
20120061059 | COOLING MECHANISM FOR STACKED DIE PACKAGE AND METHOD OF MANUFACTURING THE SAME - An apparatus for cooling a stacked die package comprises a first die provided above a substrate; a second die above the first die; a cooling fluid in fluid communication with the first die and the second die, the cooling fluid for absorbing thermal energy from the first and the second die; a housing containing the first and second dies, the housing sealing the first and second dies from an environment, wherein the housing further includes a first opening and a second opening, the first and second openings being vertically displaced from one another; a conduit having one end connected to the first opening and the other end connected to the second opening, the conduit allowing the cooling liquid to circulate from the first opening to the second opening; a first temperature sensor being arranged to provide an output that is dependent on a local temperature at the first opening; and a second temperature sensor being arranged to provide an output that is dependent on a local temperature at the second opening, wherein the outputs of the first and second temperature sensors relative to each other are indicative of a level of the cooling fluid. | 03-15-2012 |
20120063090 | COOLING MECHANISM FOR STACKED DIE PACKAGE AND METHOD OF MANUFACTURING THE SAME - An apparatus for cooling a stacked die package comprises a substrate, a first die above the substrate, a second die above the first die, and a housing containing the first and second dies. The housing seals the first and second dies from the environment. The apparatus further includes a cooling fluid in fluid communication with the first die and the second die to transfer the heat from the dies to the housing. | 03-15-2012 |
20120098123 | Molded Chip Interposer Structure and Methods - Apparatus and methods for providing a molded chip interposer structure and assembly. A molded chip structure having at least two integrated circuit dies disposed within a mold compound is provided having the die bond pads on the bottom surface; and solder bumps are formed in the openings of a dielectric layer on the bottom surface, the solder bumps forming connections to the bond pads. An interposer having a die side surface and a board side surface is provided having bump lands receiving the solder bumps of the molded chip structure on the die side of the interposer. An underfill layer is formed between the die side of the interposer and the bottom surface of the molded chip structure surrounding the solder bumps. Methods for forming the molded chip interposer structure are disclosed. | 04-26-2012 |
20130037950 | Multi-Chip Wafer Level Package - A multi-chip wafer level package comprises three stacked semiconductor dies. A first semiconductor die is embedded in a first photo-sensitive material layer. A second semiconductor die is stacked on top of the first semiconductor die wherein the second semiconductor die is face-to-face coupled to the first semiconductor die. A third semiconductor die is back-to-back attached to the second semiconductor die. Both the second semiconductor die and the third semiconductor die are embedded in a second photo-sensitive material layer. The multi-chip wafer level package further comprises a plurality of through assembly vias formed in the first photo-sensitive material layer and the second photo-sensitive material layer. | 02-14-2013 |
20130040423 | Method of Multi-Chip Wafer Level Packaging - A method of multi-chip wafer level packaging comprises forming a reconfigured wafer using a plurality of photo-sensitive material layers. A plurality of semiconductor chips and wafers are embedded in the photo-sensitive material layers. Furthermore, a variety of through assembly vias are formed in the photo-sensitive material layers. Each semiconductor chip embedded in the photo-sensitive material layers is connected to input/output pads through connection paths formed by the through assembly vias. | 02-14-2013 |
20130099377 | Molded Chip Interposer Structure and Methods - Apparatus and methods for providing a molded chip interposer structure and assembly. A molded chip structure having at least two integrated circuit dies disposed within a mold compound is provided having the die bond pads on the bottom surface; and solder bumps are formed in the openings of a dielectric layer on the bottom surface, the solder bumps forming connections to the bond pads. An interposer having a die side surface and a board side surface is provided having bump lands receiving the solder bumps of the molded chip structure on the die side of the interposer. An underfill layer is formed between the die side of the interposer and the bottom surface of the molded chip structure surrounding the solder bumps. Methods for forming the molded chip interposer structure are disclosed. | 04-25-2013 |
20130277829 | Method of Fabricating Three Dimensional Integrated Circuit - A method of fabricating a three dimensional integrated circuit comprises forming a redistribution layer on a first side of a packaging component, forming a holding chamber in the redistribution layer, attaching an integrated circuit die on the first side of the packaging component, wherein an interconnect bump of the integrated circuit die is inserted into the holding chamber, applying a reflow process to the integrated circuit die and the packaging component and forming an encapsulation layer on the packaging component. | 10-24-2013 |
20130313121 | Method of Forming Interconnects for Three Dimensional Integrated Circuit - A method of forming interconnects for three dimensional integrated circuits comprises attaching a metal layer on a first carrier, attaching a first side of a packaging component on the metal layer, wherein the packaging component comprises a plurality of through vias. The method further comprises filling the plurality of through vias with a metal material using an electrochemical plating process, wherein the metal layer functions as an electrode for the electrochemical plating process, attaching a second carrier on a second side of the packaging component, detaching the first carrier from the packaging component, forming a photoresist layer on the metal layer, patterning the photoresist layer and detaching exposed portions of the metal layer. | 11-28-2013 |
20140070348 | Methods and Apparatus for Sensor Module - Methods and apparatus for integrating a CMOS image sensor and an image signal processor (ISP) together using an interposer to form a system in package device module are disclosed. The device module may comprise an interposer with a substrate. An interposer contact is formed within the substrate. A sensor device may be bonded to a surface of the interposer, wherein a sensor contact is bonded to a first end of the interposer contact. An ISP may be connected to the interposer, by bonding an ISP contact in the ISP to a second end of the interposer contact. An underfill layer may fill a gap between the interposer and the ISP. A printed circuit board (PCB) may further be connected to the interposer by way of a solder ball connected to another interposer contact. A thermal interface material may be in contact with the ISP and the PCB. | 03-13-2014 |
20140231991 | Method of Fabricating Three Dimensional Integrated Circuit - A method of fabricating a three dimensional integrated circuit comprises forming a redistribution layer on a first side of a packaging component, forming a holding chamber in the redistribution layer, attaching an integrated circuit die on the first side of the packaging component, wherein an interconnect bump of the integrated circuit die is inserted into the holding chamber, applying a reflow process to the integrated circuit die and the packaging component and forming an encapsulation layer on the packaging component. | 08-21-2014 |
Patent application number | Description | Published |
20110035717 | Design Optimization for Circuit Migration - An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist. | 02-10-2011 |
20110072405 | Chip-Level ECO Shrink - In a method of forming an integrated circuit, a layout of a chip representation including a first intellectual property (IP) is provided. Cut lines that overlap, and extend out from, edges of the first IP, are generated. The cut lines divide the chip representation into a plurality of circuit regions. The plurality of circuit regions are shifted outward with relative to a position of the first IP to generate a space. The first IP is blown out into the space to generate a blown IP. A direct shrink is then performed. | 03-24-2011 |
20130326438 | LAYOUT MODIFICATION METHOD AND SYSTEM - A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identifies a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout. | 12-05-2013 |
20140245251 | Design Optimization for Circuit Migration - An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist. | 08-28-2014 |
20140282344 | LAYOUT BOUNDARY METHOD - Some embodiments of the present disclosure relates to a method and apparatus to achieve a layout that is compatible with a multiple-patterning process. Two or more unit cells are constructed with layouts which satisfy the properties of the multiple-patterning process, and are each decomposed into two or more colors to support the multiple-patterning process. An active layout feature is merged with a dummy wire at a shared boundary between two unit cells. In the event of a short between two active layout features at the shared boundary, an automatic post-layout method can rearrange the layout features in a vicinity of the shared boundary to separate the active layout features to achieve cell functionality while satisfying the multiple-patterning properties. | 09-18-2014 |
20140351784 | LAYOUT MODIFICATION METHOD AND SYSTEM - A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identifies a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout. | 11-27-2014 |