Patent application number | Description | Published |
20110035716 | DESIGN SUPPORT PROGRAM, DESIGN SUPPORT DEVICE, AND DESIGN SUPPORT METHOD - A design support program stored in a recording medium readable by a computer includes acquiring a first analysis result including information about an area included in circuit information of a design target circuit and a second analysis result relating to a path of the circuit information, the temperature of the area being equal to or higher than a certain temperature; determining an arbitrary cell on a non-critical path from among cells arranged in the area as a target cell for decreasing the area temperature; and outputting a result of the determination. | 02-10-2011 |
20110202895 | VERIFICATION COMPUTER PRODUCT, METHOD, AND APPARATUS - A recording medium stores a verification program that causes a computer to execute detecting from a model circuit, a first circuit representing junction of a source region and a substrate region and including a junction resistance and a junction capacitance, a second circuit parallel to the first circuit, representing junction of a drain region and the substrate region, and including a junction resistance and a junction capacitance equivalent to the junction resistance and capacitance of the first circuit, and a connection resistance connecting the circuits and a substrate electrode; calculating, using the junction resistances and connection resistance, a first coefficient indicating impact of the junction resistances and connection resistance on amplitude variation; calculating, using the junction capacitances and connection resistance, a second coefficient indicating impact of the junction capacitances and connection resistance on phase variation; correcting the junction capacitances using a sum of the coefficients; and outputting a correction result. | 08-18-2011 |
20120139602 | APPARATUS AND METHOD FOR SUPPORTING CIRCUIT DESIGN, AND SEMICONDUCTOR INTEGRATED CIRCUIT - In a circuit design support apparatus, a selection unit selects a delay circuit model from among two or more delay circuit models with wire load based on different values of physical parameters relating to wiring, on the basis of a difference value in a physical parameter between a first path and a second path, the first path being from a branch point of a clock signal line for supplying a clock signal to a register model of a semiconductor integrated circuit model to be designed up to a clock signal input terminal of the register model, the second path being from the branch point up to a data signal input terminal of the register model. An arrangement unit arranges the selected delay circuit model on a data signal line connected to the data signal input terminal. | 06-07-2012 |
20120329266 | LAYOUT METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A plurality of gate electrode patterns to be laid out in parallel are alternately set as first patterns to be formed in a first exposure step of double patterning and as second patterns to be formed in a second exposure step. Subsequently, a circuit that includes transistor pairs each formed by connecting one of the first patterns and one of the second patterns in parallel is laid out. This reduces the risk of variations in characteristics of transistors caused by double patterning. | 12-27-2012 |
Patent application number | Description | Published |
20090190470 | TRAFFIC SHAPING METHOD AND DEVICE - There are provided a distribution unit for classifying traffics into group/user/class units, a transmission point-in-time processing unit for calculating available frame rate from peak-frame-rate/minimum-frame-rate/weight set for each user, and managing a transmission schedule point-in-time, a scheduling control unit for controlling a scheduling in accordance with the transmission schedule point-in-time, a user/group/line's each peak-frame-rate control unit for performing a shaping of the traffics at each peak frame rate of the user/group/line, and a priority-control processing unit for carrying out an inter-groups priority control. | 07-30-2009 |
20100085980 | RECEIVER DEVICE, TRANSMISSION SYSTEM, AND PACKET TRANSMISSION METHOD - In a transmission system of transferring a packet input from a first device to a second device via a network, a receiver device comprises a storage module configured to successively accumulate received packets, which are transferred over a multiple transmission paths, in correlation to each of the multiple transmission paths, a packet selector configured to sequentially perform a packet selection process with respect to each of the received packets accumulated in the storage module, where after elapse of a predetermined time period since a receipt time of a first packet received by the receiver device, the packet selection process respectively reads out one packet for each of the multiple transmission paths among the received identical packets, which are accumulated in correlation to each of the multiple transmission paths, and selects one packet with higher reliability out of the read-out packets, and an output module configured to output the packet selected by the packet selector to the second device. | 04-08-2010 |
20110063978 | TRAFFIC SHAPING METHOD AND DEVICE - A packet relay device comprises a distribution processing unit classifying traffics into groups and users based on header information of packets received; a calculation unit calculating available frame rate of each user from peak frame rate, minimum frame rate, and weight information set for each user; a scheduling control unit updating a transmission schedule point-in-time calculated based on the available frame rate of each user, and judging which packet should be transmitted in accordance with the transmission schedule point-in-time updated; and a shaping unit updating a transmission schedule point-in-time calculated based on the peak frame rate of each user, and performing a shaping of packets at the peak frame rate on each user basis in accordance with the transmission schedule point-in-time updated; and a priority-control processing unit performing a strict priority control over transmission of packets of each group in correspondence with degree of priority of each group. | 03-17-2011 |