Patent application number | Description | Published |
20080255937 | SYSTEM FOR OPTIMIZING THE PERFORMANCE OF ONLINE ADVERTISEMENTS USING A NETWORK OF USERS AND ADVERTISERS - A system is described for optimizing the performance of online advertisements using a network of users and advertisers. The system may include a memory, an interface, and a processor. The memory may store a data representing a network comprised of queries linked to advertisements, a search query, a relevance value for each query, and a predicted weight for each advertisement. The interface may communicate with a plurality of users. The processor may be operatively connected to the memory and interface and may identify the network, and receive a query from a user, wherein the query exists in the network. The processor may calculate relevance values for the queries and use the queries with the highest relevance values to calculate a weight for each advertisement, the weight representing the relevance of the advertisement to the search query. The processor may then serve the advertisements with the highest weights to the user. | 10-16-2008 |
20080256034 | SYSTEM AND METHOD FOR UNDERSTANDING RELATIONSHIPS BETWEEN KEYWORDS AND ADVERTISEMENTS - An impression graph is generated comprising keywords as nodes on a first side of the impression graph and advertisement listing as nodes on a second side of the impression graph, an impression relationship between a given keyword and a given advertisement listing represented by an impression edge connection. A click graph is also generated comprising keywords as nodes on a first side of the click graph and advertisement listing as nodes on a second side of the click graph, a relationship between a given keyword and a given advertisement listing represented by a click edge connection. A mapping function is applied to calculate one or more weights for a given edge in the impression graph and the click graph and the one or more edge weights, the impression graph and the click graph are transformed into a unified bipartite graph. | 10-16-2008 |
20080256039 | SYSTEM FOR DETERMINING THE QUALITY OF QUERY SUGGESTION SYSTEMS USING A NETWORK OF USERS AND ADVERTISERS - A system is described for determining the quality of query suggestion systems using a network of users and advertisers. The system may include a memory and a processor. The memory may store data representing a plurality of query suggestion systems, a historical dataset, a plurality of residual values, and a data representing a network. The network may comprise a plurality of query items representing queries linked to a plurality of advertisement items representing advertisements via a plurality of query-advertisement link items. The processor may retrieve the historical dataset and generate the data representing the network. The processor may calculate the residual values for each query suggestion system in the plurality of query suggestion systems. The residual value may represent a value attributable to the query suggestions generated by a given query suggestion system. The processor may store the residual value of each query suggestion in the memory. | 10-16-2008 |
20080256056 | System for building a data structure representing a network of users and advertisers - A system is described for building a data structure representing a network of advertisers and users. The system may include a memory and a processor. The memory may be operatively connected to the processor and may store a historical dataset comprising of a plurality of query items and advertisement items, a plurality of query-advertisement link items, a weight, a data structure and a condition. The processor may identify the historical dataset, and link the query items to the advertisement items to generate query-advertisement link items. The processor may determine the weight of each query-advertisement link item and may store the query-advertisement link items and the weight in the data structure if the query-advertisement link item satisfies the condition. | 10-16-2008 |
20080256059 | SYSTEM FOR GENERATING QUERY SUGGESTIONS USING A NETWORK OF USERS AND ADVERTISERS - A system is described for generating query suggestions using a network of users and advertisers. The system may include a memory, an interface, and a processor. The memory may store a data representing a network comprising query items linked to advertisement items via link items, wherein each link item comprises a weight representing the strength of the relationship between each query item and advertisement item, a search query item, and a relevance value for each query item. The processor may be operatively connected to the memory and the interface and may identify the data representing the network and receive a search query item. The processor may calculate a relevance value for each additional query item in the network based on its relationship to the received search query item. The processor may then suggest the query items with the highest relevance values to the user via the interface. | 10-16-2008 |
20080256060 | SYSTEM FOR DETERMINING THE QUALITY OF QUERY SUGGESTIONS USING A NETWORK OF USERS AND ADVERTISERS - A system is described for determining the quality of query suggestions using a network of users and advertisers. The system may include a memory and a processor. The memory may store a historical dataset, a residual value, a query-advertisement link value, a query suggestion value, and a data representing a network. The network may comprise a plurality of query items linked to a plurality of advertisement items via a plurality of query-advertisement link items. The processor may generate data representing the network and may identify a query-advertisement link item in the network. The processor may calculate the residual value of the query suggestion system represented by the match type of the query-advertisement link item. The processor may calculate the query-advertisement link value. The processor may add the residual value to the query-advertisement link value to determine a query suggestion value and may store the query suggestion value in the memory. | 10-16-2008 |
20080256061 | SYSTEM FOR GENERATING QUERY SUGGESTIONS BY INTEGRATING VALUABLE QUERY SUGGESTIONS WITH EXPERIMENTAL QUERY SUGGESTIONS USING A NETWORK OF USERS AND ADVERTISERS - A system is described for generating query suggestions by integrating valuable query suggestions with experimental query suggestions using a network of users and advertisers. The system may include a memory, an interface, and a processor. The memory may store a historical dataset, a plurality of query suggestions, a plurality of query suggestion values, a query exploit set, a query explore set, and a data describing a network. The processor may identify the plurality of query suggestions in the historical dataset and generate data describing the network based on the historical dataset. The processor may calculate the query suggestion value for each query suggestion and may rank the query suggestions based on the query suggestion values. The processor may generate an exploit set comprising the top ranked query suggestions and an explore set comprising the remainder. The processor may suggest the query suggestions in the exploit set and the explore set. | 10-16-2008 |
Patent application number | Description | Published |
20100246303 | SENSE AMPLIFIERS AND EXEMPLARY APPLICATIONS - Embodiments of the invention are related to sense amplifiers. In an embodiment involving a sense amplifier used with a memory cell, signals BL, ZBL, SN and SP are pre-charged and equalized to a voltage reference, e.g., Vref, using an equalizing signal. A compensation signal, e.g., SAC, is applied to compensate for the mismatch between transistors in the sense amplifier. The word line WL is activated to connect the memory cell to a bit line, e.g., bit line ZBL. Because the memory cell shares the charge with the connected bit line ZBL, it causes a differential signal to be developed between bit lines BL and ZBL. When enough split between bit lines BL and ZBL is developed, signals SP and SAE are raised to VDD (while signal SN has been lowered to VSS) to turn on the sense amplifier and allow it to function as desire. Other embodiments and exemplary applications are also disclosed. | 09-30-2010 |
20130010561 | SENSE AMPLIFIERS AND EXEMPLARY APPLICATIONS - Embodiments of the invention are related to sense amplifiers. In an embodiment involving a sense amplifier used with a memory cell, signals BL, ZBL, SN and SP are pre-charged and equalized to a voltage reference, e.g., Vref, using an equalizing signal. A compensation signal, e.g., SAC, is applied to compensate for the mismatch between transistors in the sense amplifier. The word line WL is activated to connect the memory cell to a bit line, e.g., bit line ZBL. Because the memory cell shares the charge with the connected bit line ZBL, it causes a differential signal to be developed between bit lines BL and ZBL. When enough split between bit lines BL and ZBL is developed, signals SP and SAE are raised to VDD (while signal SN has been lowered to VSS) to turn on the sense amplifier and allow it to function as desire. Other embodiments and exemplary applications are also disclosed. | 01-10-2013 |
20140119138 | MEMORY ARCHITECTURE - A memory circuit includes a memory cell and a data circuit. In a write operation of the memory cell, the data circuit is configured to provide a first write logical value to the first output of the data circuit and to provide a second write logical value to the second output of the data circuit. The first write logical value is different from the second write logical value. In a read operation of the memory cell, the data circuit is configured to provide a same logical value to the first output and the second output of the data circuit. | 05-01-2014 |
20140241077 | TRACKING CIRCUIT - A current flowing through a voltage line and/or a data line in a column of a tracking circuit is determined. A threshold tracking time delay of the tracking circuit is determined. Based on the determined current handled by the voltage line and/or the data line and the determined threshold tracking time delay, a plurality of columns in the tracking circuit, a number of first cells in each column of the plurality of columns, and a number of second cells in the each column of the plurality of columns are determined. | 08-28-2014 |
20140241087 | SENSE AMPLIFIER - A sense amplifier comprises a cross coupled pair of inverters, a first transistor, a second transistor, and a capacitive device. The cross coupled pair of inverters includes a first end, a second end, and a third end. The first end is configured to receive a first supply voltage. The second end is coupled with a first terminal of the capacitive device and a first terminal of the first transistor. The third end is coupled with a second terminal of the capacitive device and a first terminal of the second transistor. A second terminal of the first transistor and a second terminal of the second transistor are coupled together and are configured to receive a first control signal. A third terminal of the first transistor and a third terminal of the second transistor are coupled together and are configured to receive a second supply voltage different from the first supply voltage. | 08-28-2014 |
20140269027 | AMPLIFIER - A circuit comprises a first data line, a second data line, a charging circuit, a first circuit, a second circuit, a first switching circuit, and a second switching circuit. The charging circuit and the first circuit are each coupled with the first data and the second data line. The first switching circuit is coupled between the first data line and a first node of the second circuit. The second switching circuit is coupled between the second data line and a second node of the second circuit. The data on the first node or the second node represents data in a single-ended circuit. Data on both the first node and the second node represent data in a differential circuit. | 09-18-2014 |
20150243349 | AMPLIFIER - A circuit includes a plurality of first circuits, a selection circuit, and a second circuit. The selection circuit is configured to selectively couple a first circuit of the plurality of first circuits with the second circuit. The first circuit includes a first data line and a second data line; and a pair of cross-coupled transistors of a first type coupled with the first data line and the second data line. The second circuit includes a first switching circuit and a second switching circuit; and a pair of cross coupled transistors of a second type different from the first type. The pair of cross-coupled transistors of the first circuit and the pair of cross-coupled transistors of the second circuit are configured as part of a sense amplifier when the first switching circuit and the second switching circuit are turned on. | 08-27-2015 |
Patent application number | Description | Published |
20150102839 | LOW POWER INVERTER CIRCUIT - A low power inverter circuit includes first and second transistors that receive an input signal at their gate terminals. The first and second transistors are connected by way of their source terminals to third and fourth transistors, respectively. The third and fourth transistors are connected in parallel with fifth and sixth transistors, respectively. The third and fourth transistors are continuously switched on, and the fifth and sixth transistors are controlled in such a way to reduce short circuit current flowing through the first and second transistors when the input signal transitions from one state to another. | 04-16-2015 |
20150248519 | SYSTEM FOR PARTITIONING INTEGRATED CIRCUIT DESIGN BASED ON TIMING SLACK - A method of physical design of an IC using an EDA tool includes identifying elements of the IC design that have excess positive timing slack. The excess timing slack elements are placed in a separate partition and then parameters of the characteristics of the excess timing slack elements are modified to reduce their excess timing slack, such as reducing the voltage supplied to the separate partition, thereby lowering power consumption of the IC design. | 09-03-2015 |
20150316950 | DUAL-EDGE GATED CLOCK SIGNAL GENERATOR - A clock signal generator provides a gated clock signal GCLK to trigger operation of dual-edge triggered circuits. A first detector generates, while a clock gating signal /EN is asserted, a first detector output signal that is asserted or de-asserted as a function of disjunction or conjunction respectively of the values that an input clock signal CLK and the gated clock signal GCLK had when the clock gating signal /EN transitioned. A second detector generates, while the clock gating signal /EN is de-asserted, as the value of the gated clock signal GCLK, the value CLK or its complement /CLK as a function of the first detector output signal. When the clock gating signal /EN is asserted, the second detector maintains the value that the gated clock signal GCLK had when the clock gating signal /EN transitioned from de-asserted to asserted. | 11-05-2015 |