Patent application number | Description | Published |
20080272814 | PARALLEL MULTIPLEXING DUTY CYCLE ADJUSTMENT CIRCUIT WITH PROGRAMMABLE RANGE CONTROL - A receive interface circuit includes a duty cycle adjustment circuit that adjusts the duty cycle of a reference clock signal based, at least in part, on a selected number of duty cycle adjustment units and a selected range of duty cycle adjustment. The duty cycle adjustment circuit may select as the reference clock signal one of a clock signal and at least a lower version of the clock signal in parallel with the duty cycle adjustment. | 11-06-2008 |
20080273528 | PHASE SELECT CIRCUIT WITH REDUCED HYSTERESIS EFFECT - A phase signal select circuit includes a supporting path coupled to a tri-state inverter circuit. The supporting path reduces effects of hysteresis on signal transfer. An apparatus includes at least one input node responsive to a respective one of at least one input signal. The apparatus includes at least one circuit coupled to a respective one of the at least one input node and coupled to an output node. Individual ones of the at least one circuit are configured to provide a version of the respective input signal to the output node in response to a first state of a respective select signal. The apparatus includes at least one second circuit coupled to a respective one of the at least one circuit. The at least one second circuit is configured to toggle nodes of the at least one circuit in response to a second state of the respective select signal. | 11-06-2008 |
20080297216 | TEST TECHNIQUES FOR A DELAY-LOCKED LOOP RECEIVER INTERFACE - An integrated circuit includes a variable delay circuit configured to generate at least one delayed clock signal based on a first clock signal and a first control signal. The integrated circuit includes a control circuit configured to generate a count value based on a second input signal and a second control signal. The first clock signal is a first version of the at least one delayed clock signal. At least one of the second input signal and the second control signal is a second version of the at least one delayed clock signal and the count value is indicative of a frequency characteristic of the at least one delayed clock signal. The integrated circuit is configured to monotonically vary the first control signal over a range of values and the count value is determined for individual values of the control signal. | 12-04-2008 |
20100171547 | PSEUDO BANDGAP VOLTAGE REFERENCE CIRCUIT - A pseudo bandgap voltage reference circuit includes a first transistor and a second transistor, each coupled to a supply voltage node. The circuit also includes an amplifier circuit coupled to a gate terminal of each of the first and the second transistors, a current source coupled to the supply voltage node, and a first diode coupled between the current source and a ground reference node. A first input of the amplifier circuit is coupled to a node between the current source and the first diode. In addition, a first terminal of the first transistor is coupled to a second input of the amplifier circuit in a feedback loop. Also, an output reference voltage is developed at an output node coupled to a second terminal of the second transistor. Further, an output current of the current source is independent of a current flowing through the first terminal of the first transistor. | 07-08-2010 |
20120133459 | PASSIVE FILTER AND AC COUPLER RECEIVER INTERFACE - An apparatus includes a capacitor coupled between a first node responsive to receive an input signal and a second node. The apparatus includes a first circuit coupled to the second node and a third node. The first circuit is selectively operable to separately configure at least one of a low-frequency gain of an equalizer and a pole of the equalizer. The equalizer includes the first circuit and the capacitor. The second node is responsive to receive an equalized version of an AC signal of the input signal in a first mode of the apparatus. The second node is responsive to receive a non-equalized version of the AC signal of the input signal in a second mode of the apparatus. The equalized version of the AC signal of the input signal may be a level-shifted and equalized version of the AC signal in the first mode of the apparatus. | 05-31-2012 |
20130162310 | CLOCK GENERATOR WITH INTEGRATED PHASE OFFSET PROGRAMMABILITY - A device may include first, second, and third buffer stages. The device may further include a selector circuit to selectively output one of an output of the second buffer stage or an output of the third buffer stage. The device may include an output to provide a first clock signal, where the first clock signal is an output of the first buffer stage, and the device further include an output to provide a second clock signal, where the second clock signal is an output of the selector circuit. | 06-27-2013 |
20130162357 | OSCILLATOR WITH HIGHLY-ADJUSTABLE BANG-BANG CONTROL - A device may include an oscillator to generate a clock signal based on first and second control signals. The oscillator may include a first buffer stage a second buffer stage. The first buffer stage may output a first signal that is based on an output of the second buffer stage and the first control signal. The second buffer stage may output the clock signal. The clock signal may be based on the first signal and the second control signal. | 06-27-2013 |
20140049292 | INTEGRATED CIRCUIT PACKAGE HAVING MEDIUM-INDEPENDENT SIGNALING INTERFACE COUPLED TO CONNECTOR ASSEMBLY - An integrated circuit (IC) package includes electrical contacts disposed at a first surface of the IC package, an integrated circuit implementing an electrical signaling interface, and a connector assembly accessible at a second surface of the IC package. The connector assembly is to mechanically attach to another connector assembly and includes contact terminals electrically coupled to the electrical signaling interface. The connector assembly can be configured to provide friction coupling with the other connector assembly to permit the other connector assembly to be removably attached. A system includes the IC package and an external transceiver module having a connector assembly mechanically attached to the connector assembly of the IC package. The electrical signaling interface conducts signaling with the external transceiver module in accordance with one signal format and the external transceiver module conducts signaling over a transmission medium in accordance with another signal format. | 02-20-2014 |
20140176098 | FEED-FORWARD COMPENSATION FOR LOW-DROPOUT VOLTAGE REGULATOR - A voltage regulator includes a pass element having a control input coupled to a control node and operable to generate an output voltage at an output node, a negative feedback amplifier operable to receive a reference voltage and the output voltage and generate a signal at the control node based on a difference between the reference voltage and the output voltage, and a noise cancellation circuit coupled to the control node and the output node and operable to generate a bias current at the control node based on the output voltage. | 06-26-2014 |
20150041955 | Multi-Die Fine Grain Integrated Voltage Regulation - A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more current consuming elements. A passive device may be coupled to the power consuming device. The passive device may include a plurality of passive elements formed on a semiconductor substrate. The passive elements may be arranged in an array of structures on the semiconductor substrate. The power consuming device and the passive device may be coupled using one or more terminals. The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used. | 02-12-2015 |
Patent application number | Description | Published |
20080227301 | Control of bevel etch film profile using plasma exclusion zone rings larger than the wafer diameter - A method of cleaning a bevel edge of a semiconductor substrate is provided. A semiconductor substrate is placed on a substrate support in a reaction chamber of a plasma processing apparatus. The substrate has a dielectric layer overlying a top surface and a bevel edge of the substrate, the layer extending above and below an apex of the bevel edge. A process gas is introduced into the reaction chamber and energized into a plasma. The bevel edge is cleaned with the plasma so as to remove the layer below the apex without removing all of the layer above the apex. | 09-18-2008 |
20090188627 | GAS MODULATION TO CONTROL EDGE EXCLUSION IN A BEVEL EDGE ETCHING PLASMA CHAMBER - The various embodiments provide apparatus and methods of removal of unwanted deposits near the bevel edge of substrates to improve process yield. The embodiments provide apparatus and methods with center and edge gas feeds as additional process knobs for selecting a most suitable bevel edge etching processes to push the edge exclusion zone further outward towards the edge of substrates. Further the embodiments provide apparatus and methods with tuning gas(es) to change the etching profile at the bevel edge and using a combination of center and edge gas feeds to flow process and tuning gases into the chamber. Both the usage of tuning gas and location of gas feed(s) affect the etching characteristics at bevel edge. Total gas flow, gap distance between the gas delivery plate and substrate surface, pressure, and types of process gas(es) are also found to affect bevel edge etching profiles. | 07-30-2009 |
20110253312 | GAS MODULATION TO CONTROL EDGE EXCLUSION IN A BEVEL EDGE ETCHING PLASMA CHAMBER - The various embodiments provide apparatus and methods of removal of unwanted deposits near the bevel edge of substrates to improve process yield. The embodiments provide apparatus and methods with center and edge gas feeds as additional process knobs for selecting a most suitable bevel edge etching processes to push the edge exclusion zone further outward towards the edge of substrates. Further the embodiments provide apparatus and methods with tuning gas(es) to change the etching profile at the bevel edge and using a combination of center and edge gas feeds to flow process and tuning gases into the chamber. Both the usage of tuning gas and location of gas feed(s) affect the etching characteristics at bevel edge. Total gas flow, gap distance between the gas delivery plate and substrate surface, pressure, and types of process gas(es) are also found to affect bevel edge etching profiles. | 10-20-2011 |
20120074099 | Methods for Controlling Bevel Edge Etching in a Plasma Chamber - Methods for bevel edge etching are provided. One example method is for etching a film on a bevel edge of a substrate in a plasma etching chamber. The method includes providing the substrate on a substrate support in the plasma etching chamber. The plasma etching chamber has a top edge electrode and a bottom edge electrode disposed to surround the substrate support. Then flowing an etching process gas through a plurality of edge gas feeds disposed along a periphery of the gas delivery plate. The periphery of the gas deliver plate is oriented above the substrate support and the bevel edge of the substrate, and the flowing is further directed to a space between the top edge electrode and bottom edge electrode. And, flowing a tuning gas through a center gas feed of the gas delivery plate. | 03-29-2012 |
20130264015 | CONTROL OF BEVEL ETCH FILM PROFILE USING PLASMA EXCLUSION ZONE RINGS LARGER THAN THE WAFER DIAMETER - A method of cleaning a bevel edge of a semiconductor substrate is provided. A semiconductor substrate is placed on a substrate support in a reaction chamber of a plasma processing apparatus. The substrate has a dielectric layer overlying a top surface and a bevel edge of the substrate, the layer extending above and below an apex of the bevel edge. A process gas is introduced into the reaction chamber and energized into a plasma. The bevel edge is cleaned with the plasma so as to remove the layer below the apex without removing all of the layer above the apex. | 10-10-2013 |
Patent application number | Description | Published |
20090150836 | Intelligent Pattern Signature Based on Lithography Effects - The present invention is directed to an improved method, system, and computer program product for accessing and analyzing patterns in the integrated circuit design. The method, system or computer program product includes generating an intelligent signature for a pattern. The derived pattern signature is an intelligent pattern identifier because it retains only essential information about a pattern that corresponds to lithography printable portions of the pattern. Accordingly, one pattern signature can represent a group of design patterns that are equivalents from a lithography perspective. | 06-11-2009 |
20090169114 | INTERPOLATION OF IRREGULAR DATA IN A FINITE-DIMENSIONAL METRIC SPACE IN LITHOGRAPHIC SIMULATION - A method, system, and computer program product for preprocessing a pattern in a library of patterns and querying a preprocessed library of patterns are disclosed. Embodiments for querying a preprocessed library of patterns are disclosed for determining a distance between the representation for the first pattern and the representation for the second pattern, determining whether the distance between the representation for the first pattern and the representation for the second pattern is within the range for the first pattern, and transforming the second pattern with the transformation matrix to provide information about the second pattern. Embodiments for preprocessing a pattern in a library of patterns are disclosed for determining a transformation matrix for the first pattern, determining a range for the first pattern, wherein a distance between a representation for a first pattern and a representation for a second pattern is within the range and the second pattern can be transformed with the transformation matrix to provide information about the second pattern, and associating the range and the transformation matrix with the first pattern. | 07-02-2009 |
20090199137 | SYSTEM AND METHOD FOR MULTI-EXPOSURE PATTERN DECOMPOSITION - Some embodiments provide a method and system for identifying error markers for patterns within a design layout that do not meet the manufacturing constraints. Some embodiments extend a region from the error marked region to extract a pattern for decomposition analysis. Some embodiments compare the extracted pattern to known patterns stored in a library, which also stores at least one previously computed decomposition solution for each known pattern. For an extracted pattern existing within the library, some embodiments retrieve the previously computed decomposition solution from the library. For an extracted pattern that does not exist within the library, some embodiments use one or more simulations to determine a decomposition solution for the extracted pattern. The resulting decomposition solution replaces the extracted pattern within the design layout producing a variant of the original layout that contains the decomposed solution for the pattern. | 08-06-2009 |
20090288047 | METHOD AND APPARATUS FOR USING A DATABASE TO QUICKLY IDENTIFY AND CORRECT A MANUFACTURING PROBLEM AREA IN A LAYOUT - One embodiment provides a system for using a database to quickly identify a manufacturing problem area in a layout. During operation, the system receives a first check-figure which identifies a first area in a first layout, wherein the first area is associated with a first feature. Next, the system determines a first sample using the first check-figure, wherein the first sample represents the first layout's geometry within a first ambit of the first check-figure, wherein the first sample's geometry is expected to affect the shape of the first feature. The system then performs a model-based simulation using the first sample to obtain a first simulation-result which indicates whether the first feature is expected to have manufacturing problems. Next, the system stores the first simulation-result in a database which is used to quickly determine whether a second feature is expected to have manufacturing problems. | 11-19-2009 |
20090307642 | METHOD AND SYSTEM FOR MODEL-BASED DESIGN AND LAYOUT OF AN INTEGRATED CIRCUIT - A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers. | 12-10-2009 |
20110167397 | SYSTEM AND METHOD FOR MULTI-EXPOSURE PATTERN DECOMPOSITION - Some embodiments provide a method and system for identifying error markers for patterns within a design layout that do not meet the manufacturing constraints. Some embodiments extend a region from the error marked region to extract a pattern for decomposition analysis. Some embodiments compare the extracted pattern to known patterns stored in a library, which also stores at least one previously computed decomposition solution for each known pattern. For an extracted pattern existing within the library, some embodiments retrieve the previously computed decomposition solution from the library. For an extracted pattern that does not exist within the library, some embodiments use one or more simulations to determine a decomposition solution for the extracted pattern. The resulting decomposition solution replaces the extracted pattern within the design layout producing a variant of the original layout that contains the decomposed solution for the pattern. | 07-07-2011 |
20110239168 | INTELLIGENT PATTERN SIGNATURE BASED ON LITHOGRAPHY EFFECTS - The present invention is directed to an improved method, system, and computer program product for accessing and analyzing patterns in the integrated circuit design. The method, system or computer program product includes generating an intelligent signature for a pattern. The derived pattern signature is an intelligent pattern identifier because it retains only essential information about a pattern that corresponds to lithography printable portions of the pattern. Accordingly, one pattern signature can represent a group of design patterns that are equivalents from a lithography perspective. | 09-29-2011 |
20120272200 | METHOD AND SYSTEM FOR MODEL-BASED DESIGN AND LAYOUT OF AN INTEGRATED CIRCUIT - A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers. | 10-25-2012 |
20120272201 | METHOD AND SYSTEM FOR MODEL-BASED DESIGN AND LAYOUT OF AN INTEGRATED CIRCUIT - A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers. | 10-25-2012 |
20130195368 | SCALABLE PATTERN MATCHING BETWEEN A PATTERN CLIP AND A PATTERN LIBRARY - A two-level matching technique is described. A system can generate a set of index patterns based on a set of library patterns in a pattern library. The pattern library can include patterns that are expected to have problems during manufacturing. Next, the system can use a fast matching process to check if a first-level pattern clip potentially matches one or more index patterns from the set of index patterns. If so, the system can use a detailed matching process to match a second-level pattern clip with library patterns that correspond to the one or more index patterns. Otherwise, the system can report that the first-level pattern clip does not match any library pattern in the pattern library. | 08-01-2013 |
20140089868 | AUTOMATED REPAIR METHOD AND SYSTEM FOR DOUBLE PATTERNING CONFLICTS - A method of performing double patterning (DPT) conflict repairs is described. In this method, even cycles adjacent to odd cycles in a layout can be identified (also called adjacent even/odd cycles herein). The identifying can include forming graph constructs of the layout. Route guidances for break-link operations and split-node operations can be prioritized for the adjacent even/odd cycles. A list including the route guidances for the break-link operations and the split-node operations can be generated. The list can be ordered based on the prioritizing. | 03-27-2014 |
Patent application number | Description | Published |
20080236618 | Cleaning of bonded silicon electrodes - Methods of cleaning plasma processing chamber components include contacting surfaces of the components with a cleaning solution, while avoiding damage of other surfaces or areas of the components by the cleaning solution. An exemplary plasma processing chamber component to be cleaning is an elastomer bonded electrode assembly having a silicon member with a plasma-exposed silicon surface, a backing member, and an elastomer bonding material between the silicon surface and the backing member. | 10-02-2008 |
20090321018 | PERIPHERALLY ENGAGING ELECTRODE CARRIERS AND ASSEMBLIES INCORPORATING THE SAME - In accordance with one embodiment of the present disclosure, an assembly is provided comprising a multi-component electrode and a peripherally engaging electrode carrier. The peripherally engaging electrode carrier comprises a carrier frame and a plurality of reciprocating electrode supports. The multi-component electrode is positioned in the electrode accommodating aperture of the carrier frame. The backing plate of the electrode comprises a plurality of mounting recesses formed about its periphery. The reciprocating electrode supports can be reciprocated into and out of the mounting recesses. Additional embodiments of broader and narrower scope are contemplated. | 12-31-2009 |
20090322199 | BACKSIDE MOUNTED ELECTRODE CARRIERS AND ASSEMBLIES INCORPORATING THE SAME - A carrier assembly is provided comprising a backside mounted electrode carrier and electrode mounting hardware. The backside mounted electrode carrier comprises an electrode accommodating aperture, which in turn comprises a sidewall structure that is configured to limit lateral movement of an electrode positioned in the aperture. The electrode accommodating aperture further comprises one or more sidewall projections that support the weight of an electrode positioned in the aperture. The electrode mounting hardware is configured to engage an electrode positioned in the electrode accommodating aperture from the backside of the carrier and urge the electrode against the sidewall projections so as to limit axial movement of the electrode in the electrode accommodating aperture. Additional embodiments of broader and narrower scope are contemplated. | 12-31-2009 |
20090325320 | PROCESSES FOR RECONDITIONING MULTI-COMPONENT ELECTRODES - A process for reconditioning a multi-component electrode comprising a silicon electrode bonded to an electrically conductive backing plate is provided. The process comprises: (i) removing metal ions from the multi-component electrode by soaking the multi-component electrode in a substantially alcohol-free DSP solution comprising sulfuric acid, hydrogen peroxide, and water and rinsing the multi-component electrode with de-ionized water; (ii) polishing one or more surfaces of the multi-component electrode following removal of metal ions there from; and (iii) removing contaminants from silicon surfaces of the multi-component electrode by treating the polished multi-component electrode with a mixed acid solution comprising hydrofluoric acid, nitric acid, acetic acid, and water and by rinsing the treated multi-component electrode with de-ionized water. Additional embodiments of broader and narrower scope are contemplated. | 12-31-2009 |
20100090711 | SYSTEM AND METHOD FOR TESTING AN ELECTROSTATIC CHUCK - The present invention provides a reliable, non-invasive, electrical test method for predicting satisfactory performance of electrostatic chucks (ESCs). In accordance with an aspect of the present invention, a parameter, e.g., impedance, of an ESC is measured over a frequency band to generate a parameter functions. This parameter function may be used to establish predetermined acceptable limits of the parameter within the frequency band. | 04-15-2010 |
20120013242 | BACKSIDE MOUNTED ELECTRODE CARRIERS AND ASSEMBLIES INCORPORATING THE SAME - A carrier assembly is provided comprising a backside mounted electrode carrier and electrode mounting hardware. The backside mounted electrode carrier comprises an electrode accommodating aperture, which in turn comprises a sidewall structure that is configured to limit lateral movement of an electrode positioned in the aperture. The electrode accommodating aperture further comprises one or more sidewall projections that support the weight of an electrode positioned in the aperture. The electrode mounting hardware is configured to engage an electrode positioned in the electrode accommodating aperture from the backside of the carrier and urge the electrode against the sidewall projections so as to limit axial movement of the electrode in the electrode accommodating aperture. Additional embodiments of broader and narrower scope are contemplated. | 01-19-2012 |
20120153971 | SYSTEM AND METHOD FOR TESTING AN ELECTROSTATIC CHUCK - The present invention provides a reliable, non-invasive, electrical test method for predicting satisfactory performance of electrostatic chucks (ESCs). In accordance with an aspect of the present invention, a parameter, e.g., impedance, of an ESC is measured over a frequency band to generate a parameter functions. This parameter function may be used to establish predetermined acceptable limits of the parameter within the frequency band. | 06-21-2012 |
20130102156 | COMPONENTS OF PLASMA PROCESSING CHAMBERS HAVING TEXTURED PLASMA RESISTANT COATINGS - A component of a plasma processing chamber includes a three dimensional body having a highly dense plasma resistant coating thereon wherein a plasma exposed surface of the coating has a texture which inhibits particle generation from film buildup on the plasma exposed surface. The component can be a window of an inductively coupled plasma reactor wherein the window includes a textured yttria coating. The texture can be provided by contacting the plasma exposed surface with a polishing pad having a grit size effective to provide intersecting scratches with a depth of 1 to 2 microns. | 04-25-2013 |
20130104930 | METHOD OF CLEANING ALUMINUM PLASMA CHAMBER PARTS | 05-02-2013 |
20130105083 | Systems Comprising Silicon Coated Gas Supply Conduits And Methods For Applying Coatings | 05-02-2013 |
20130160948 | Plasma Processing Devices With Corrosion Resistant Components - In one embodiment, a plasma processing device may include a plasma processing chamber, a plasma region, an energy source, and a corrosion resistant component. The plasma processing chamber can be maintained at a vacuum pressure and can confine a plasma processing gas. The energy source can transmit energy into the plasma processing chamber and transform at least a portion of the plasma processing gas into plasma within the plasma region. The corrosion resistant component can be located within the plasma processing chamber. The corrosion resistant component can be exposed to the plasma processing gas and is not coincident with the plasma region. The corrosion resistant component may include an inner layer of stainless steel that is coated with an outer layer of Tantalum (Ta). | 06-27-2013 |
20140083461 | METHOD OF REMOVING DAMAGED EPOXY FROM ELECTROSTATIC CHUCK - A method of removing an epoxy band from an electrostatic chuck includes securing the electrostatic chuck in a servicing fixture, applying a thermal source to the epoxy band to breakdown a plurality of adhesive bonds securing the epoxy band to the electrostatic chuck, forming a hole in the epoxy band and pulling the epoxy band from the electrostatic chuck. A system for removing an epoxy band from an electrostatic chuck is also described. | 03-27-2014 |
20140113453 | TUNGSTEN CARBIDE COATED METAL COMPONENT OF A PLASMA REACTOR CHAMBER AND METHOD OF COATING - A tungsten carbide coated chamber component of semiconductor processing equipment includes a metal surface, optional intermediate nickel coating, and outer tungsten carbide coating. The component is manufactured by optionally depositing a nickel coating on a metal surface of the component and depositing a tungsten carbide coating on the metal surface or nickel coating to form an outermost surface. | 04-24-2014 |
20140150819 | METHOD OF WET CLEANING ALUMINUM CHAMBER PARTS - A method of wet cleaning an aluminum part having bare aluminum surfaces and anodized aluminum surfaces. The method includes CO | 06-05-2014 |