Patent application number | Description | Published |
20090220307 | STRAKE SYSTEMS AND METHODS - There is disclosed a system comprising a structural element, at least one helical strake about the structural element, and at least one ramp to provide a transition from the structural element to the helical strake. | 09-03-2009 |
20090242207 | STRAKE SYSTEMS AND METHODS - There is disclosed a system comprising a structural element; at least one strake holder connected to the structural element; and at least one flexible helical strake connected to the at least one strake holder. | 10-01-2009 |
20100050921 | SUBSEA INSTALLATION SYSTEMS AND METHODS - There is disclosed a system comprising a vessel floating in a body of water, a line comprising a first portion connected to the vessel and a second portion in the body of water, a tool connected to the second portion of the line, the tool in the body of water below the vessel, a stationary apparatus connected to the second portion of the line, the stationary apparatus in the body of water below the vessel, and a mechanism on the vessel connected to the first portion of the line, the mechanism adapted to keep the line taut as the vessel heaves up and down. | 03-04-2010 |
20100098497 | VORTEX INDUCED VIBRATION SUPPRESSION SYSTEMS AND METHODS - A system comprising a subsea structure beneath a body of water, subject to a water current; an installation vessel floating on the body of water; a line connected to the subsea structure and the installation vessel; and one or more vortex induced vibration suppression devices connected to the line, which have been lowered from the vessel to be installed on the subsea structure. | 04-22-2010 |
20100139384 | CURRENT TANK SYSTEMS AND METHODS - There is disclosed a current tank system comprising a first current tank adapted to produce a first current in a first direction, and a second current tank adapted to produce a second current in a second direction. There is also disclosed a method of testing a sample, comprising exposing the sample to a first current in a first current tank, and exposing the sample to a second current in a second current tank. | 06-10-2010 |
20100150662 | VORTEX INDUCED VIBRATION SUPPRESSION SYSTEMS AND METHODS - A system comprising a subsea structure defining an interior of the system, the structure subject to a water current; a sleeve exterior to the subsea structure, covering at least a portion of an outside surface of the subsea structure; and a vortex induced vibration suppression device exterior to the sleeve. | 06-17-2010 |
20110038672 | SYSTEM AND METHODS TO INSTALL SUBSEA STRUCTURES - A system comprising a structure defining an interior of the system; an apparatus exterior to the structure, the apparatus adapted to reduce in size when lowered into a body of water; a strap exterior to the apparatus, the strap adapted to reduce in size as the apparatus reduces in size. | 02-17-2011 |
20120006554 | METHODS AND DEVICES OF CLEANING SUBSEA STRUCTURES - A tool for cleaning subsea structures, the tool comprising a frame comprising a stationary frame portion; and a rotating frame portion rotationally connected to the stationary frame portion; and at least one cleaning device attached to the rotating frame portion. | 01-12-2012 |
Patent application number | Description | Published |
20110130537 | PRODUCTION OF SOLID EPOXY RESIN - In an improved process for preparation of glycidyl ether resins that are solid at room temperature, sometimes referred to as solid epoxy resins”, from a reaction mixture of an aromatic hydroxyl-containing compound, an epihalohydrin and an inorganic hydroxide, add a reaction solvent that has both a ether moiety ad an alcohol moiety to the reaction mixture and use mole-equivalent ratio of moles (one mole-equivalent) epihalohydrin to hydroxyl moieties of the aromatic hydroxyl-containing compound that falls within a range of from 0.5:1 to 1:1. | 06-02-2011 |
20120130095 | PROCESS FOR PRODUCING AN OXIRANE - A multiple liquid phase composition and process for preparing an oxirane product, such as epichlorohydrin, including a reaction mixture of: (a) at least one olefin, wherein the olefin is selected from one of (i) an aliphatic olefin or substituted aliphatic olefin, with the proviso that the aliphatic olefin is not propylene, (ii) a cycloaliphatic olefin, (iii) an aromatic olefin, (iv) a cycloaromatic olefin, and (v) mixtures thereof; (b) at least one peroxide compound, (c) at least one catalyst, and (d) and a solvent mixture; wherein the solvent mixture comprises at least (i) at least one alcohol or a combination of alcohols, and (ii) at least one non-reactive co-solvent; wherein the solvents are mixed at a predetermined concentration; wherein the non-reactive co-solvent has a different boiling point than the oxirane product; and wherein the oxirane product partitions into a high affinity solvent during the reaction. The process of the present invention advantageously produces a waste stream with no significant amount of sodium chloride (NaCl). In one embodiment, the present invention includes a process for preparing epichlorohydrin from allyl chloride and hydrogen peroxide including reacting (a) an allyl chloride with (b) hydrogen peroxide, in the presence of (c) a titanium silicalite-1 (TS-1) catalyst and (d) in the presence of a predetermined amount of a mixed solvent system; wherein the mixed solvent system includes at least (i) methanol and (ii) at least one non-reactive co-solvent. | 05-24-2012 |
20120130096 | PROCESS FOR PRODUCING PROPYLENE OXIDE - A multiple liquid phase composition and process for preparing propylene oxide including a reaction mixture of: (a) propylene, (b) at least one peroxide compound, (c) at least one catalyst, such as a titanium silicalite-1 (TS-I) catalyst, and (d) and a predetermined amount of a solvent mixture; wherein the solvent mixture comprises at least (i) at least one alcohol, such as methanol, and (ii) at least one non-reactive co-solvent; wherein the solvents are mixed at a predetermined concentration; wherein the non-reactive co-solvent has a different boiling point than propylene oxide; and wherein the resulting propylene oxide product partitions into a high affinity solvent during the reaction. The process of the present invention advantageously produces a waste stream with little or no significant amount of sodium chloride (NaCl). | 05-24-2012 |
20130267720 | PROCESS FOR PREPARING DINVINYLARENE OXIDES - A process for preparing a divinylarene oxide including (a) reacting (i) at least one divinylarene; (ii) at least one peroxycarboximidic acid; (iii) at least one solvent; and (iv) at least one basic compound, under reaction conditions to form a reaction of fluent containing a divinylarene oxide product; and then (b) evaporating the reaction effluent of step (a) to form a concentrate containing the divinylarene oxide product; and wherein the concentrate separates into two liquid phases. | 10-10-2013 |
Patent application number | Description | Published |
20120191059 | CASSETTES AND METHODS OF USING SAME - The present disclosure provides cassettes and methods of using same for the delivery of fluids to a patient using fluid delivery systems. In a general embodiment, the cassettes of the present disclosure include a flexible tube, a housing having a recessed area and first and second ends for holding the flexible tube, and at least two additional components including, for example, different sensors, false reading components for sensors, anti-flow valve means, insertion guides, directional indicators, latch mechanisms, kink-prevention notches, etc. Such additional components provide the cassettes of the present disclosure with several advantages including, for example, quality control, efficiency of use, cost effectiveness, and safety of use. | 07-26-2012 |
20120266964 | CASSETTE WITH INFUSION SET CONTAINING ANTI-FREEFLOW BALL VALVE FOR PERISTALTIC INFUSION PUMP - Flow control devices and methods of using the flow control devices are provided. In a general embodiment, the present disclosure provides a cassette ( | 10-25-2012 |
20120266965 | CASSETTE WITH INFUSION SET CONTAINING SPRING-BIASED ANTI-FREEFLOW MECHANISM FOR PERISTALTIC INFUSION PUMP - Flow control devices.—In a general embodiment, the present disclosure provides a cassette ( | 10-25-2012 |
Patent application number | Description | Published |
20090170305 | METHOD FOR IMPROVING ELECTROMIGRATION LIFETIME FOR CU INTERCONNECT SYSTEMS - A method for forming a single damascene and/or dual damascene interconnect structure, comprising: performing front end processing, depositing copper, annealing the copper, performing CMP planarization, performing a post copper CMP clean process, performing a BTA rinse, performing IPA drying process, performing doping during thermal ramp up and performing remaining back end processing. | 07-02-2009 |
20100078769 | ENVIRONMENTAL DIE SEAL ENHANCEMENT FOR WAFER LEVEL CHIP SCALE PACKAGES - In a semiconductor device for use in a wafer level chip scale package (WLCSP) and a method for fabrication, an inner scribe seal is formed around a functional circuit area that does not extend all the way into the corners of the rectangular die, and an outer scribe seal follows the perimeter of the die and into the corners, with the outer scribe seal having a continuous barrier wall towards the die edges so that moisture penetration in dielectric layers of the die is minimized, and cracks and delamination are stopped near the die edges. Limiting the extent of the insulating layer or layers in the WLCSP to cover the functional circuit area also reduces the stresses caused by these layers near the die corners. Other features further enhance the strength and barrier properties of the scribe seals and the layers near the die corners, terminate cracks and delamination at various levels within the dielectric stack of the die and the die protective overcoat, and prevent damage during the WLCSP assembly process. | 04-01-2010 |
20100193918 | EMBEDDED SCRIBE LANE CRACK ARREST STRUCTURE FOR IMPROVED IC PACKAGE RELIABILITY OF PLASTIC FLIP CHIP DEVICES - A system, method, and apparatus for suppressing cracks in the wafer dicing process. A wafer includes a plurality of die attached to a frame and mounting tape, with the die separated by a plurality of scribe lanes. An existing die seal generally protects the boundary of the die but can still fail to fully protect the die from excessive cracks induced by dicing damage, particularly when dicing through brittle, low-k dielectrics. The system, method, and apparatus includes embedding a crack arrest structure (CAS) between adjacent scribe lanes. Upon a mechanical saw dicing the wafer, the CAS creates a moisture diffusion block, and can absorb or significantly diminish the energy of cracks propagating towards the individual die seals. Furthermore, the system, method, and apparatus can be implemented without the need to increase the width of the scribe lanes. | 08-05-2010 |
20110031581 | INTEGRATED CIRCUIT (IC) HAVING TSVS WITH DIELECTRIC CRACK SUPPRESSION STRUCTURES - An IC includes a substrate having a semiconductor top surface, a plurality of metal interconnect levels having inter-level dielectric (ILD) layers therebetween on the top surface, and a bottom surface. A plurality of through substrate vias (TSVs) extend from a TSV terminating metal interconnect level downward to the bottom surface. The plurality of TSVs include an electrically conductive filler material surrounded by a dielectric liner that define a projected volume. The projected volume includes a projected area over the electrically conductive filler material and a projected height extending upwards from the TSV terminating metal interconnect level to a metal interconnect level above, and a projected sidewall surface along sidewalls of the projected volume. A crack suppression structure (CSS) protects TSVs and includes a lateral CSS portion that is positioned lateral to the projected volume and encloses at least 80% of the projected sidewall surface. | 02-10-2011 |
20110049717 | INTEGRATED CIRCUITS HAVING TSVS INCLUDING METAL GETTERING DIELECTRIC LINERS - An IC includes a substrate having a semiconductor top surface and a bottom surface, wherein the semiconductor top surface includes one or more active circuit components and a plurality of through silicon vias (TSVs) extending through the substrate. The plurality of TSVs include an outer dielectric liner. The dielectric liner includes at least one halogen or a Group 15 element metal gettering agent in an average concentration from 1 to 10 atomic %. A metal diffusion barrier layer is on the dielectric liner and a metal filler is on the metal barrier layer. The metal gettering agent getters metal filler that escapes the metal barrier layer. | 03-03-2011 |
20110079916 | ELECTRONIC ASSEMBLIES INCLUDING MECHANICALLY SECURED PROTRUDING BONDING CONDUCTOR JOINTS - An electronic assembly includes an IC die including a semiconductor top surface having active circuitry thereon and a bottom surface, and at least one protruding bonding feature having sidewall surfaces and a leading edge surface extending outward from the IC die. A workpiece has a workpiece surface including at least one electrical connector and at least one framed hollow receptacle coupled to the electrical connector. The receptacle is formed from metal and includes sidewall portions and a bent top that defines a cavity. The bent top includes bent peripheral shelf regions that point downward into the cavity and towards the sidewall portions. The protruding bonding feature is inserted within the cavity of the receptacle and contacts the bent peripheral shelf regions along a contact area to form a metallic joint, wherein the contact area is at least primarily along the sidewall surfaces. | 04-07-2011 |
20110186990 | PROTRUDING TSV TIPS FOR ENHANCED HEAT DISSIPATION FOR IC DEVICES - An integrated circuit (IC) device includes a substrate having a top surface including substrate pads, and a through substrate via (TSV) die including a semiconductor substrate including a topside semiconductor surface having active circuitry and a bottomside surface. The topside semiconductor surface includes bonding connectors that are coupled to the substrate pads on the top surface of the substrate. A plurality of TSVs include an inner metal core that extends from the topside semiconductor surface to protruding TSV tips which extend out from the bottomside surface. At least one of the plurality of TSVs are dummy TSVs that have their protruding TSV tips exclusive of any electrically connection thereto that provide additional surface area that enhances heat dissipation from the bottomside of the TSV die. | 08-04-2011 |
20110187000 | Integrated Circuits Having TSVS Including Metal Gettering Dielectric Liners - An IC includes a substrate having a semiconductor top surface and a bottom surface, wherein the semiconductor top surface includes one or more active circuit components and a plurality of through silicon vias (TSVs) extending through the substrate. The plurality of TSVs include an outer dielectric liner. The dielectric liner includes at least one halogen or a Group 15 element metal gettering agent in an average concentration from 1 to 10 atomic %. A metal diffusion barrier layer is on the dielectric liner and a metal filler is on the metal barrier layer. The metal gettering agent getters metal filler that escapes the metal barrier layer. | 08-04-2011 |
20110291263 | IC HAVING DIELECTRIC POLYMERIC COATED PROTRUDING FEATURES HAVING WET ETCHED EXPOSED TIPS - A method of fabricating IC die includes providing a substrate having a topside semiconductor surface including active circuitry and a bottomside surface. The IC die includes at least one protruding feature coupled to the active circuitry that protrudes from the bottomside surface or the topside semiconductor surface. The topside semiconductor surface and/or bottomside surface and the protruding feature are coated with a dielectric polymer. A portion of the dielectric polymer is removed from the protruding feature using a solvent to expose a tip portion of the protruding feature for electrical connection thereto. With a solvent that does not corrode or oxidize the exposed protruding feature tips, the need for a conventional subsequent chemical exposure to remove corrosion or oxidation is avoided. | 12-01-2011 |
20120080595 | NON-CONTACT DETERMINATION OF JOINT INTEGRITY BETWEEN A TSV DIE AND A PACKAGE SUBSTRATE - A non-contact voltage contrast (VC) method of determining TSV joint integrity after partial assembly. A TSV die is provided including TSVs that extend from a frontside of the TSV die to TSV tips on a bottomside of the TSV die. At least some TSVs (contacting TSVs) are attached to pads on a top surface of a multilayer (ML) package substrate. The ML package substrate is on a substrate carrier that blocks electrical access to the frontside of the TSV die. Two or more nets including groups of contacting TSVs are tied common within the ML substrate. A charged particle reference beam is directed to a selected TSV within a first net and a charged particle primary beam is then rastered across the TSVs in the first net. VC signals emitted are detected, and joint integrity for the contacting TSVs to pads of the ML package substrate is determined from the VC signals. | 04-05-2012 |
20120149155 | Electronic Assemblies Including Mechanically Secured Protruding Bonding Conductor Joints - A method for joining integrated circuit (IC) die. The includes pressing the IC die toward a workpiece so that a protruding bonding feature is inserted into a cavity of a receptacle through an opening. The pressing bends peripheral shelf regions downward into the cavity and towards sidewall portions of the receptacle to form bent peripheral shelf regions. A protruding bonding feature contacts the bent peripheral shelf regions along a contact area. The contact area being at least primarily along the sidewall surfaces of the protruding bonding feature. | 06-14-2012 |
20120235296 | IC DEVICES HAVING TSVS INCLUDING PROTRUDING TIPS HAVING IMC BLOCKING TIP ENDS - A through substrate via (TSV) die includes a plurality of TSVs including an outer dielectric sleeve, an inner metal core and protruding TSV tips including sidewalls that emerge from the TSV die. A passivation layer lateral to protruding TSV tips is on a portion of the sidewalls of protruding TSV tips. The passivation layers is absent from a distal portion of protruding TSV tips to provide an exposed portion of the inner metal core. The TSV tips include bulbous distal tip ends which cover a portion of the TSV sidewalls, are over a topmost surface of the outer dielectric sleeve, and have a maximum cross sectional area that is ≧25% more as compared to a cross sectional area of the protruding TSV tips below the bulbous distal tip ends. | 09-20-2012 |
20130062736 | POST-POLYMER REVEALING OF THROUGH-SUBSTRATE VIA TIPS - A method of forming semiconductor die includes forming a layer of polymer or a precursor of the polymer on a bottomside of a substrate having a topside including active circuitry and a bottomside, and a plurality of through-substrate-vias (TSVs). The TSVs have a liner including at least a dielectric liner and an inner metal core that extends to TSV tips that protrude from the bottomside. The layer of polymer or precursor and liner cover the plurality of TSV tips, and the layer of polymer or precursor is between the TSV tips on the bottomside. The polymer or precursor and the liner are removed from over a top of the TSV tips to reveal the inner metal core. | 03-14-2013 |
20130113103 | DEVICE HAVING TSVs WITH GETTERING LAYER LATERAL TO TSV TIPS - An integrated circuit (IC) includes a substrate having a topside semiconductor surface including active circuitry configured to provide functionality and a bottomside surface. A plurality of through substrate vias (TSVs) extend from the topside semiconductor surface to beyond the bottomside surface to provide protruding TSV tips. The TSVs include an outer dielectric liner, a metal comprising diffusion barrier layer on the dielectric liner, and a metal filler on the metal comprising barrier layer. A dielectric metal gettering layer (MGL) is on the bottomside surface lateral to and on sidewalls of the protruding TSV tips. The MGL includes at least one metal gettering agent selected from a halogen or a Group 15 element in an average concentration from 0.1 to 10 atomic %. | 05-09-2013 |
20130249011 | INTEGRATED CIRCUIT (IC) HAVING TSVS AND STRESS COMPENSATING LAYER - A through-substrate via (TSV) unit cell includes a substrate having a topside semiconductor surface and a bottomside surface, and a TSV which extends the full thickness of the substrate including an electrically conductive filler material surrounded by a dielectric liner that forms an outer edge for the TSV. A circumscribing region of topside semiconductor surface surrounds the outer edge of the TSV. Dielectric isolation is outside the circumscribing region. A tensile contact etch stop layer (t-CESL) is on the dielectric isolation, and on the circumscribing region. | 09-26-2013 |
20140154880 | Post-Polymer Revealing of Through-Substrate Via Tips - A method of forming semiconductor die includes forming a layer of polymer or a precursor of the polymer on a bottomside of a substrate having a topside including active circuitry and a bottomside, and a plurality of through-substrate-vias (TSVs). The TSVs have a liner including at least a dielectric liner and an inner metal core that extends to TSV tips that protrude from the bottomside. The layer of polymer or precursor and liner cover the plurality of TSV tips, and the layer of polymer or precursor is between the TSV tips on the bottomside. The polymer or precursor and the liner are removed from over a top of the TSV tips to reveal the inner metal core. | 06-05-2014 |
20160133580 | SCRIBE SEALS AND METHODS OF MAKING - A semiconductor die includes a plurality of layers, the plurality of layers having a top surface. A scribe seal is located in the plurality of layers and includes a first metal stack having a first metal layer located proximate the top surface. A trench is located in at least one layer of the plurality of layers. The trench extends from the top surface of the plurality of layers and is located a distance from the first metal stack. An electrical insulating layer is located on the top surface. The electrical insulating layer covers at least a portion of the top surface adjacent the first metal layer and extends a distance from the top surface of the first metal layer. | 05-12-2016 |
Patent application number | Description | Published |
20080290340 | Method for fabricating a semiconductor device having embedded interconnect structures to improve die corner robustness - In a method for fabricating a semiconductor device a redundant scribe seal structure is formed. The semiconductor device includes a die having a rectangular shape with sloped corners. A scribe seal is formed to surround the die, the scribe seal having sides to form sloped corners that match the sloped corners of the die. A scribe seal extension having sharp corners is formed by extending the sides of the scribe seal that have a perpendicular orientation towards one another. The scribe seal extension redundantly encloses a corresponding one of the sloped corners of the scribe seal. | 11-27-2008 |
20100109128 | Crack Deflector Structure for Improving Semiconductor Device Robustness Against Saw-Induced Damage - An integrated circuit containing a crack deflecting scribe seal which separates an interior region of the integrated circuit from a scribeline immediately outside the integrated circuit and a method of forming the same. The crack deflecting scribe seal includes continuous metal layers and continuous contacts and continuous vias between the continuous metal layers. The continuous metal layers do not extend past the continuous contacts and continuous vias. The continuous contacts and continuous vias are recessed from edges of the underlying continuous metal layers on the scribeline side of the scribe seal, providing an angled outer surface on the scribe seal which may desirably terminate crack propagation or deflect crack propagation upward to a top surface of the scribeline or the crack deflecting scribe seal. | 05-06-2010 |
20100171226 | IC HAVING TSV ARRAYS WITH REDUCED TSV INDUCED STRESS - An integrated circuit (IC) includes a substrate having a top side having active circuitry thereon including a plurality of metal interconnect levels including a first metal interconnect level and a top metal interconnect level, and a bottom side. At least one TSV array includes a plurality of TSVs. The TSVs are positioned in rows including a plurality of interior rows and a pair of exterior rows and a plurality of columns including a plurality of interior columns and a pair of exterior columns. At least a portion of the TSVs in the array are electrically connected TSVs that are coupled to a TSV terminating metal interconnect level selected from the plurality of metal interconnect levels. At least one of the exterior rows or exterior columns include a lower number of electrically connected TSVs compared to a maximum number of electrically connected TSVs in the interior rows and interior columns, respectively. | 07-08-2010 |
20100264413 | Replacement of Scribeline Padframe with Saw-Friendly Design - An integrated circuit substrate containing an electrical probe pad structure over, and on both sides of, a dicing kerf lane. The electrical probe pad structure includes metal crack arresting strips adjacent to the dicing kerf lane. A metal density between the crack arresting strips is less than 70 percent. An electrical probe pad structure containing metal crack arresting strips, with a metal density between the crack arresting strips less than 70 percent. A process of forming an integrated circuit by forming an electrical probe pad structure over a dicing kerf lane adjacent to the integrated circuit, such that the electrical probe pad structure has metal crack arresting strips adjacent to the dicing kerf lane, and performing a dicing operation through the electrical probe pad structure. | 10-21-2010 |
20110227227 | INTEGRATED CIRCUIT HAVING TSVS INCLUDING HILLOCK SUPPRESSION - A method for fabricating integrated circuit (ICs) having through substrate vias (TSVs) includes forming active circuit elements on a semiconductor wafer and then forming a plurality of embedded vias through the top side of the wafer. A metal filler layer including a filler metal is deposited to fill the embedded vias. Chemical mechanical polishing (CMP) then forms a plurality of embedded TSVs that have polished top TSV surfaces having exposed filler metal. An electrically conductive hillock suppression structure is formed by forming a silicon or germanium doped region, or a silicide or germanicide at the polished top TSV surface or by forming a metal layer on the polished top TSV surface having a composition different from the filler metal. A dielectric layer is deposited on the semiconductor wafer including over the hillock suppression structure. The dielectric layer is removed over the polished top TSV surface to allow metal contact thereto. | 09-22-2011 |
20120175774 | WARPAGE CONTROL FEATURES ON THE BOTTOMSIDE OF TSV DIE LATERAL TO PROTRUDING BOTTOMSIDE TIPS - A through substrate via (TSV) die includes a substrate including a topside semiconductor surface having active circuitry. The die includes a plurality of TSVs that each include an inner metal core that extend from the topside semiconductor surface to protruding TSV tips that extend out from the bottomside surface. A metal cap is on the protruding TSV tips that includes at least one metal layer that has a metal that is not in the inner metal core. A plurality of protruding warpage control features are on the bottomside surface lateral to the protruding TSV tips, wherein the plurality of protruding warpage control features do not have the protruding TSV tips thereunder. The plurality of protruding warpage control features can include the same metal layer(s) used for the metal cap. | 07-12-2012 |
20120306085 | PROTECTIVE LAYER FOR PROTECTING TSV TIPS DURING THERMO-COMPRESSIVE BONDING - A method of protecting through substrate via (TSV) die from bonding damage includes providing a substrate including a plurality of TSV die having a topside including active circuitry, a bottomside, and a plurality of TSVs that include an inner metal core that reaches from the topside to protruding TSV tips that extend out from the bottomside. A protective layer is formed on or applied to the bottomside of the TSV die including between and over the protruding TSV tips. The TSV die is bonded with its topside down onto a workpiece having a workpiece surface and its bottomside up and in contact with a bond head. The protective layer reduces damage from the bonding process including warpage of the TSV die by preventing the bond head from making direct contact to the protruding TSV tips. | 12-06-2012 |
20130032946 | LASER-ASSISTED CLEAVING OF A RECONSTITUTED WAFER FOR STACKED DIE ASSEMBLIES - A method of forming stacked die devices includes attaching first semiconductor die onto a wafer to form a reconstituted wafer, and then bonding second semiconductor die onto the first semiconductor die to form a plurality of singulated stacked die devices on the wafer. A support tape is attached to a bottomside of the second semiconductor die. A dicing tape is attached to the wafer. The wafer is laser irradiated before or after attachment of the dicing tape at intended dicing lanes that align with gaps between the first semiconductor die to mechanically weaken the wafer at the intended dicing lanes, but not cut through the wafer. The dicing tape is pulled to cleave the wafer into a plurality of singulated portions to form a plurality of singulated stacked die devices attached to the singulated wafer portions by the dicing tape. The support tape is removed prior to cleaving. | 02-07-2013 |
20130249098 | PROTECTIVE LAYER FOR PROTECTING TSV TIPS DURING THERMO-COMPRESSIVE BONDING - A method of protecting through substrate via (TSV) die from bonding damage includes providing a substrate including a plurality of TSV die having a topside including active circuitry, a bottomside, and a plurality of TSVs that include an inner metal core that reaches from the topside to protruding TSV tips that extend out from the bottomside. A protective layer is formed on or applied to the bottomside of the TSV die including between and over the protruding TSV tips. The TSV die is bonded with its topside down onto a workpiece having a workpiece surface and its bottomside up and in contact with a bond head. The protective layer reduces damage from the bonding process including warpage of the TSV die by preventing the bond head from making direct contact to the protruding TSV tips. | 09-26-2013 |
20140038359 | Laser-Assisted Cleaving of a Reconstituted Wafer for Stacked Die Assemblies - A method of forming stacked die devices includes attaching first semiconductor die onto a wafer to form a reconstituted wafer, and then bonding second semiconductor die onto the first semiconductor die to form a plurality of singulated stacked die devices on the wafer. A support tape is attached to a bottomside of the second semiconductor die. A dicing tape is attached to the wafer. The wafer is laser irradiated before or after attachment of the dicing tape at intended dicing lanes that align with gaps between the first semiconductor die to mechanically weaken the wafer at the intended dicing lanes, but not cut through the wafer. The dicing tape is pulled to cleave the wafer into a plurality of singulated portions to form a plurality of singulated stacked die devices attached to the singulated wafer portions by the dicing tape. The support tape is removed prior to cleaving. | 02-06-2014 |
20140124900 | THROUGH-SILICON VIA (TSV) DIE AND METHOD TO CONTROL WARPAGE - A through-substrate via (TSV) die includes a substrate having a top side semiconductor surface having active circuitry therein including a plurality of transistors functionally connected and a bottom side surface, wherein the layers on the top side semiconductor surface exert a net tensile stress to the top side semiconductor surface. A plurality of TSVs which extend from the top side semiconductor surface to TSV tips which protrude from the bottom side surface include an inner metal core surrounded by a dielectric liner that forms an outer edge for the TSVs. A dielectric stack is on the bottom side surface lateral to the TSV tips including a compressive dielectric layer and a tensile dielectric layer on the compressive dielectric layer. | 05-08-2014 |
20140151895 | DIE HAVING THROUGH-SUBSTRATE VIAS WITH DEFORMATION PROTECTED TIPS - A through-substrate via (TSV) die includes a substrate with a top side semiconductor surface having active circuitry therein including a plurality of transistors functionally connected and a bottom side surface. A plurality of TSVs extend from the top side semiconductor surface to TSV tips which protrude from the bottom side surface and include an inner metal core of electrically conductive filler material surrounded by a dielectric liner that forms an outer edge for the TSVs. A tip deformation protecting layer of inorganic dielectric material is on the bottom side surface lateral to the TSV tips. An elastic modulus of the inorganic dielectric material is greater than (>) an elastic modulus of the electrically conductive filler material. A second dielectric layer including a polymer is on the tip deformation protecting layer. | 06-05-2014 |
20150061081 | CRACK DEFLECTOR STRUCTURE FOR IMPROVING SEMICONDUCTOR DEVICE ROBUSTNESS AGAINST SAW-INDUCED DAMAGE - An integrated circuit containing a crack deflecting scribe seal which separates an interior region of the integrated circuit from a scribeline immediately outside the integrated circuit and a method of forming the same. The crack deflecting scribe seal includes continuous metal layers and continuous contacts and continuous vias between the continuous metal layers. The continuous metal layers do not extend past the continuous contacts and continuous vias. The continuous contacts and continuous vias are recessed from edges of the underlying continuous metal layers on the scribeline side of the scribe seal, providing an angled outer surface on the scribe seal which may desirably terminate crack propagation or deflect crack propagation upward to a top surface of the scribeline or the crack deflecting scribe seal. | 03-05-2015 |
20150333055 | HIGH BREAKDOWN VOLTAGE MICROELECTRONIC DEVICE ISOLATION STRUCTURE WITH IMPROVED RELIABILITY - A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node. | 11-19-2015 |
20160133690 | Methods and Apparatus for High Voltage Integrated Circuit Capacitors - High voltage integrated circuit capacitors are disclosed. In an example arrangement, A capacitor structure includes a semiconductor substrate; a bottom plate having a conductive layer overlying the semiconductor substrate; a capacitor dielectric layer deposited overlying at least a portion of the bottom plate and having a first thickness greater than about 6 um in a first region; a sloped transition region in the capacitor dielectric at an edge of the first region, the sloped transition region having an upper surface with a slope of greater than 5 degrees from a horizontal plane and extending from the first region to a second region of the capacitor dielectric layer having a second thickness lower than the first thickness; and a top plate conductor formed overlying at least a portion of the capacitor dielectric layer in the first region. Methods and additional apparatus arrangements are disclosed. | 05-12-2016 |
Patent application number | Description | Published |
20120271327 | Endoscopic Tissue Grasping Systems and Methods - An endoscopic tissue grasper device includes a flexible tubular member, a flexible shaft extending through the tubular member, a proximal handle for moving the shaft and tubular member relative to each other, and a distal helical coil having a sharpened end for engaging tissue. The tissue grasper is advanced through a working channel of an endoscope, engaged relative to tissue, and retracted to pull tissue into a path of a movable needle coupled at a distal end of the endoscope so that the needle can be passed through the tissue. The needle is preferably provided with a suture so that as the needle is passed through the tissue a stitch is formed. | 10-25-2012 |
20130006287 | Endoscopic Helix Tissue Grasping Device - An endoscopic tissue grasper device includes a flexible tubular member, a flexible shaft extending through the tubular member, a proximal handle for moving the shaft and tubular member relative to each other, and a distal helical coil having a sharpened end for engaging tissue. The helical coil has a proximal close wound portion, a distal open wound portion, and an intermediate transition portion between the proximal and distal portions. The flexible shaft extends into the proximal and intermediate portions and is secured thereto, which prevents tissue engaged by the helical coil from becoming wedged in the transition portion and thereby facilitates release of the coil from engaged tissue. In addition, a bearing sheath is provided between the shaft and tubular member to prevent the shaft from binding during operation. | 01-03-2013 |
20140024896 | ENDOSCOPE OVERTUBE FOR INSERTION THROUGH A NATURAL BODY ORIFICE - An endoscope overtube includes a flexible tubular member and a hub assembly provided at the proximal end of the tubular member. The hub assembly includes an elastic sleeve seal cuff extending about the inner surface of a body member of the hub. The ends of seal cuff are coupled to the body member. An inflation line extends into the body member in communication with the outer surface of the seal cuff. When fluid is pressurized through the inflation line, the cuff is distended inward to reduce the size of the opening through the port such that the cuff forms a seal about an endoscope received through the hub. The body member is preferably coupled to each of the flexible tubular member and to the elastic seal cuff using a snap-fit engagement of parts such that no fasteners, welds, glues, etc. are necessary for securing the hub assembly together. | 01-23-2014 |
Patent application number | Description | Published |
20100050921 | SUBSEA INSTALLATION SYSTEMS AND METHODS - There is disclosed a system comprising a vessel floating in a body of water, a line comprising a first portion connected to the vessel and a second portion in the body of water, a tool connected to the second portion of the line, the tool in the body of water below the vessel, a stationary apparatus connected to the second portion of the line, the stationary apparatus in the body of water below the vessel, and a mechanism on the vessel connected to the first portion of the line, the mechanism adapted to keep the line taut as the vessel heaves up and down. | 03-04-2010 |
20120168019 | FAIRING HAVING IMPROVED STABILITY - An apparatus including a fairing having a tail portion and an end portion capable of suppressing a vortex-induced vibration of a tubular. The apparatus further including a stabilizing member attached to the end portion of the fairing, the stabilizing member dimensioned to increase a thickness of the end portion of the fairing and a flange member attached to the stabilizing member, the flange member dimensioned to increase a chord dimension of the fairing so as to improve a stability of the fairing. | 07-05-2012 |
20120291687 | HELICAL STRAKE SYSTEMS - An apparatus including a strake section having a plurality of helical fins separated by at least one helical opening. A method including forming a helically shaped fin that independently maintains the helical shape once formed. | 11-22-2012 |
20130039702 | VORTEX-INDUCED VIBRATION SUPPRESSION DEVICE AND MATING COLLAR SYSTEM - A system including a votex-induced vibration (VIV) suppression device dimensioned to suppress a vortex induced vibration of a support structure, the VIV suppression device having a base portion that encircles at least a portion of the support structure and a support member formed along the base portion. The system further including a collar having a body portion defining an annular channel and a flange portion extending outwardly from the annular channel, the flange portion dimensioned to form a receiving channel around the support structure for receiving the support member. The support member is received within the receiving channel to secure the VIV suppression device to the support structure and the VIV suppression device is capable of rotating around the support structure along the receiving channel. | 02-14-2013 |
20140241793 | VORTEX-INDUCED VIBRATION SUPPRESSION DEVICE AND MATING COLLAR SYSTEM - A system including a vortex-induced vibration (VIV) suppression device dimensioned to suppress a vortex-induced vibration of a support structure, the VIV suppression device having a base portion that encircles at least a portion of the support structure and a support member formed along the base portion. The system further including a collar having a body portion defining an annular channel and a flange portion extending outwardly from the annular channel, the flange portion dimensioned to form a receiving channel around the support structure for receiving the support member. The support member is received within the receiving channel to secure the VIV suppression device to the support structure and the VIV suppression device is capable of rotating around the support structure along the receiving channel. | 08-28-2014 |
20150108305 | SPRING SYSTEMS FOR VORTEX SUPPRESSION DEVICES - A vortex-induced vibration (VIV) suppression system configured to accommodate a change in an underlying tubular diameter. The system including an encircling member dimensioned to at least partially encircle an underlying tubular. The encircling member may be, for example, a collar or a VIV suppression device such as a strake, or any other type of VIV suppression device. The system further including a band member dimensioned to encircle the encircling member and hold the encircling member around the underlying tubular at a desired axial position. A spring member may further be provided. The spring member may be positioned between the encircling member and the band member and dimensioned to contract in response to an increase in a diameter of the underlying tubular and expand in response to a decrease in a diameter of the underlying tubular such that the encircling member remains at the desired axial position. | 04-23-2015 |
20150233494 | FAIRING HAVING IMPROVED STABILITY - An apparatus including a fairing operable to suppress a vortex-induced vibration of a tubular, the fairing having a body portion and a tail portion that tapers from the body portion to an end portion, the body portion defining an annulus dimensioned to encircle a tubular. The apparatus further including a stabilizing member positioned along the body portion, the stabilizing member being dimensioned to stabilize the fairing along a tubular positioned within the annulus. | 08-20-2015 |