Chao-Cheng
Chao-Cheng Chang, Jhudong Township TW
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20100207461 | Power-on signal transmitting system and power-on signal transmitting method - The invention discloses a power-on signal transmitting system, which includes a first electronic device, a second electronic device and a cable coupled between the two electronic devices. The first electronic device includes a power-on control unit. The second electronic device includes a power-on detection unit. The cable includes at least one information wiring and a signal level wiring. The at least one information wiring is used for transmitting an information signal between the first electronic device and the second electronic device. When the second electronic device is at a power-off state, the power-on control unit of the first electronic device is used for transmitting a power-on signal through the signal level wiring to the second electronic device. The power-on detection unit senses the power-on signal and turns on the second electronic device. | 08-19-2010 |
Chao-Cheng Chang, New Taipei City TW
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20140016353 | Light Emitting Mirror Structure - A light emitting mirror structure includes a casing caved in to form an accommodating space having a light guiding area and a mirror area, and at least one surface of the casing as a sidewall communicating with the accommodating space. The mirror structure includes a light guiding device having a light guide plate, and a light emitting member disposed on a side of the light guide plate, and the light guiding device is placed at the light guiding area of the accommodating space of the casing. A mirror body having a substrate and a mirror surface located on the substrate is provided for the disclosed mirror structure also. The mirror body is integrated on the mirror area of the accommodating space, the light guiding plate causes a light to be emitted through the sidewall at a first side of the mirror body, and the mirror surface is uncovered by the sidewall. | 01-16-2014 |
Chao-Cheng Chen, Shin-Chu City TW
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20100068861 | METHOD OF DEFINING GATE STRUCTURE HEIGHT FOR SEMICONDUCTOR DEVICES - Provided is a method of semiconductor fabrication including process steps allowing for defining and/or modifying a gate structure height during the fabrication process. The gate structure height may be modified (e.g., decreased) at one or more stages during the fabrication by etching a portion of a polysilicon layer included in the gate structure. The method includes forming a coating layer on the substrate and overlying the gate structure. The coating layer is etched back to expose a portion of the gate structure. The gate structure (e.g., polysilicon) is etched back to decrease the height of the gate structure. | 03-18-2010 |
20110049567 | BOTTLE-NECK RECESS IN A SEMICONDUCTOR DEVICE - The present disclosure provides a method for fabricating a semiconductor device that includes providing a silicon substrate, forming a gate stack over the silicon substrate, performing a biased dry etching process to the substrate to remove a portion of the silicon substrate, thereby forming a recess region in the silicon substrate, performing a non-biased etching process to the recess region in the silicon substrate, thereby forming a bottle-neck shaped recess region in the silicon substrate, and epi-growing a semiconductor material in the bottle-neck shaped recess region in the silicon substrate. An embodiment may include a biased dry etching process including adding HeO2 gas and HBr gas. An embodiment may include performing a first biased dry etching process including N2 gas and performing a second biased dry etching process not including N2 gas. An embodiment may include performing an oxidation process to the recess region in the silicon substrate by adding oxygen gas to form silicon oxide on a portion of the recess region in the silicon substrate. As such, these processes form polymer protection to help form the bottle-neck shaped recess. | 03-03-2011 |
20110147810 | METHOD OF FABRICATING STRAINED STRUCTURE IN SEMICONDUCTOR DEVICE - The present disclosure provides a semiconductor device that includes a semiconductor substrate, a gate structure disposed on a portion of the substrate, and strained structures disposed at either side of the portion of the substrate and formed of a semiconductor material different from the semiconductor substrate. The portion of the substrate is T shaped having a horizontal region and a vertical region that extends from the horizontal region in a direction away from a surface of the substrate. | 06-23-2011 |
20120108046 | Patterning Methodology for Uniformity Control - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patternable layer over a substrate. The method includes forming a first layer over the patternable layer. The method includes forming a second layer over the first layer. The second layer is substantially thinner than the first layer. The method includes patterning the second layer with a photoresist material through a first etching process to form a patterned second layer. The method includes patterning the first layer with the patterned second layer through a second etching process to form a patterned first layer. The first and second layers have substantially different etching rates during the second etching process. The method includes patterning the patternable layer with the patterned first layer through a third etching process. | 05-03-2012 |
20130078809 | SILICON NITRIDE ETCHING IN A SINGLE WAFER APPARATUS - A single wafer etching apparatus and various methods implemented in the single wafer etching apparatus are disclosed. In an example, etching a silicon nitride layer in a single wafer etching apparatus includes: heating a phosphoric acid to a first temperature; heating a sulfuric acid to a second temperature; mixing the heated phosphoric acid and the heated sulfuric acid; heating the phosphoric acid/sulfuric acid mixture to a third temperature; and etching the silicon nitride layer with the heated phosphoric acid/sulfuric acid mixture. | 03-28-2013 |
20130099323 | METAL GATE STRUCTURE OF A SEMICONDUCTOR DEVICE - The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate comprising an isolation region surrounding and separating a P-active region and an N-active region; a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode comprises a P-work function metal and an oxygen-containing TiN layer between the P-work function metal and substrate; and an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode comprises an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein the nitrogen-rich TiN layer connects to the oxygen-containing TiN layer over the isolation region. | 04-25-2013 |
20130102136 | METHOD OF FORMING AN INTEGRATED CIRCUIT - A method of forming an integrated circuit is disclosed. A second material layer is formed on a first material layer. A patterned mask layer having a plurality of first features with a first pitch P | 04-25-2013 |
20130187235 | COMPOSITE DUMMY GATE WITH CONFORMAL POLYSILICON LAYER FOR FINFET DEVICE - The present disclosure involves a FinFET. The FinFET includes a fin structure formed over a substrate. A gate dielectric layer is least partially wrapped around a segment of the fin structure. The gate dielectric layer contains a high-k gate dielectric material. The FinFET includes a polysilicon layer conformally formed on the gate dielectric layer. The FinFET includes a metal gate electrode layer formed over the polysilicon layer. The present disclosure provides a method of fabricating a FinFET. The method includes providing a fin structure containing a semiconductor material. The method includes forming a gate dielectric layer over the fin structure, the gate dielectric layer being at least partially wrapped around the fin structure. The method includes forming a polysilicon layer over the gate dielectric layer, wherein the polysilicon layer is formed in a conformal manner. The method includes forming a dummy gate layer over the polysilicon layer. | 07-25-2013 |
20130203247 | METHOD OF FABRICATING A SEMICONDUCTOR STRUCTURE - An embodiment of the current disclosure includes a method of providing a substrate, forming a polysilicon layer over the substrate, forming a first photoresist layer on the polysislicon layer, creating a first pattern on the first photoresistlayer, wherein some portions of the polysilicon layer are covered by the first photoresist layer and some portions of the polysilicon layer are not covered by the first photoresist layer, implanting ions into the portions of the polysilicon layer that are not covered by the first photoresist layer, removing the first photoresist layer from the polysilicon layer, forming a second photoresist layer on the polysilicon layer, creating a second pattern on the second photoresistlayer, and implanting ions into the portions of the polysilicon layer that are not covered by the second photoresist layer, removing the second photoresist layer from the polysilicon layer, and removing portions of the polysilicon layer using an etchant. | 08-08-2013 |
20130221443 | FINFETS AND METHOD OF FABRICATING THE SAME - The disclosure relates to a fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a major surface; a plurality of first trenches having a first width and extending downward from the substrate major surface to a first height, wherein a first space between adjacent first trenches defines a first fin; and a plurality of second trenches having a second width less than first width and extending downward from the substrate major surface to a second height greater than the first height, wherein a second space between adjacent second trenches defines a second fin. | 08-29-2013 |
20130267099 | CHEMICAL DISPENSING SYSTEM AND METHOD - A method and apparatus for dispensing a liquid etchant onto a wafer dispenses the liquid etchant onto a wafer using a scanning dispensing nozzle while controlling the dispensing temperature of the etchant in real time as a function of the radial position of the dispensing nozzle over the wafer. The dispensing temperature of the etchant is controlled to enhance the effectiveness of the etchant and thus compensate for the lower etching rate zones in the wafer. | 10-10-2013 |
20130273711 | METHOD OF FORMING A FINFET DEVICE - A method for fabricating a device is disclosed. An exemplary method includes providing a substrate and forming a plurality of fins over the substrate. The method further includes forming a first opening in the substrate in a first longitudinal direction. The method further includes forming a second opening in the substrate in a second longitudinal direction. The first and second longitudinal directions are different. The method further includes depositing a filling material in the first and second openings. | 10-17-2013 |
20130309834 | METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device, patterning a first hard mask to form a first recess in a high-resistor (Hi-R) stack, removing the first hard mask, forming a second recess in the Hi-R stack, forming a second hard mask in the second recess in the Hi-R stack. A HR can then be formed in the semiconductor substrate by the second hard mask and a gate trench etch. | 11-21-2013 |
20130330906 | METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION - A method of fabricating a semiconductor IC is disclosed. The method includes receiving a device. The device includes a semiconductor substrate, a plurality of fins and trenches between fins in the semiconductor substrate. The method also includes filling the trenches with a dielectric material to form shallow trench isolations (STI), applying a low-thermal-budget annealing to the dielectric material, and applying a wet-treatment to the dielectric material. | 12-12-2013 |
20140134759 | METHOD OF FORMING A PATTERN - An embodiment of a method of forming a substrate pattern including forming a bottom layer and an overlying middle layer on the substrate. A photo resist pattern is formed on the middle layer. An etch coating layer is deposited on the photo resist pattern. The etch coating layer and the photo resist pattern are used as a masking element to pattern at least one of the middle layer and the bottom layer. The substrate is etched to form the substrate pattern using the at least one of the patterned middle layer and the patterned bottom layer as a masking element. The substrate pattern may be used as an element of an overlay measurement process. | 05-15-2014 |
20140242775 | METHOD OF FABRICATING FINFETS - The disclosure relates to a method of fabricating a semiconductor device including forming a patterned hardmask layer over a substrate comprising a major surface. The method further includes forming a plurality of first trenches and a plurality of second trenches performed at an electrostatic chuck (ESC) temperature between about 90° C. to 120° C. in the substrate. The plurality of first trenches have a first width and extend downward from the substrate major surface to a first height, and the plurality of second trenches have a second width less than first width and extend downward from the substrate major surface to a second height greater than the first height. | 08-28-2014 |
20140284724 | Method of Semiconductor Integrated Circuit Fabrication - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device, patterning a first hard mask to form a first recess in a high-resistor (Hi-R) stack, removing the first hard mask, forming a second recess in the Hi-R stack, forming a second hard mask in the second recess in the Hi-R stack. A HR can then be formed in the semiconductor substrate by the second hard mask and a gate trench etch. | 09-25-2014 |
20140295654 | METHOD OF FORMING AN INTEGRATED CIRCUIT - A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, the patterned mask layer having a plurality of first features with a first pitch. The method includes patterning the material layer by using the patterned mask layer as a mask to form the first features in the material layer. The method includes trimming the patterned mask layer, after patterning the material layer, to form a trimmed patterned mask layer. The method further includes introducing a plurality of dopants into the material layer exposed by the trimmed patterned mask layer to form doped regions having a second pitch, wherein the second pitch is different from the first pitch. The method further includes removing the trimmed patterned mask layer to expose un-doped regions in the material layer; and removing the un-doped regions to form a plurality of second features corresponding to the respective doped regions. | 10-02-2014 |
20150132971 | PLASMA GENERATION AND PULSED PLASMA ETCHING - One or more plasma etching techniques are provided. Selective plasma etching is achieved by introducing a gas into a chamber containing a photoresist over a substrate, establishing a bias at a frequency to convert the gas to a plasma at the frequency, and using the plasma to etch the photoresist. The frequency controls an electron density of the plasma and by maintaining a low electron density causes free radicals of the plasma to chemically etch the photoresist, rather than physically etching using ion bombardment. A mechanism is thus provided for chemically etching a photoresist under what are typically physical etching conditions. | 05-14-2015 |
20150187927 | Method to Reduce Etch Variation Using Ion Implantation - The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses. | 07-02-2015 |
20150243504 | METHOD OF FORMING AN INTEGRATED CIRCUIT - A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer. | 08-27-2015 |
20150332935 | METHOD OF FABRICATING A SEMICONDUCTOR STRUCTURE - A method of making a semiconductor structure, the method including forming a conductive layer over a substrate. The method further includes forming a first imaging layer over the conductive layer, where the first imaging layer comprises a plurality of layers. The method further includes forming openings in the first imaging layer to expose a first set of areas of the conductive layer. The method further includes implanting ions into each area of the first set of area. The method further includes forming a second imaging layer over the conductive layer. The method further includes forming openings in the second imaging layer to expose a second set of areas of the conductive layer, wherein the second set of areas is different from the first set of areas. The method further includes implanting ions into the each area of the second set of areas. | 11-19-2015 |
20150364573 | Method for Semiconductor Device Fabrication - A method of forming a semiconductor device is disclosed. The method includes exposing a dummy oxide layer of a gate structure to a vapor mixture comprising NH | 12-17-2015 |
20160064234 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes etching a substrate to form a plurality of first trenches and a plurality of second trenches performed at an electrostatic chuck (ESC) temperature between about 90° C. to 120° C. in the substrate, wherein each trench of the plurality of first trenches extends downward from the substrate major surface to a first height, and each trench of the plurality of second trenches extends downward from the substrate major surface to a second height greater than the first height. The method includes forming a first isolation structure in each of the plurality of first trenches. The method includes forming a second isolation structure in each of the plurality of second trenches, wherein a difference between a height of the first isolation structure and the first height equals a difference between a height of the second isolation structure and the second height. | 03-03-2016 |
Chao-Cheng Chen, Shinchu City TW
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20110031562 | SEALING LAYER OF A FIELD EFFECT TRANSISTOR - An exemplary structure for a gate structure of a field effect transistor comprises a gate electrode; a gate insulator under the gate electrode having footing regions on opposing sides of the gate electrode; and a sealing layer on sidewalls of the gate structure, wherein a thickness of lower portion of the sealing layer overlying the footing regions is less than a thickness of upper portion of the sealing layer on sidewalls of the gate electrode, whereby the field effect transistor made has almost no recess in the substrate surface. | 02-10-2011 |
Chao-Cheng Chen, Chong-Ling TW
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20100190349 | Method for backside polymer reduction in dry-etch process - A method for preventing the formation of contaminating polymeric films on the backsides of semiconductor substrates includes providing an oxygen-impregnated focus ring and/or an oxygen-impregnated chuck that releases oxygen during etching operations. The method further provides delivering oxygen gas to the substrate by mixing oxygen in the cooling gas mixture, maintaining the focus ring at a temperature no greater than the substrate temperature during etching and cleaning the substrate using a two step plasma cleaning sequence that includes suspending the substrate above the chuck. | 07-29-2010 |
Chao-Cheng Chen, Shin-Chu TW
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20150206952 | METHOD OF FORMING FINFET - A method of forming a FinFET is provided. A gate oxide layer and a dummy poly layer are substantially simultaneously etched using an etchant having a higher selectivity on the gate oxide layer than on the dummy poly layer. The gate oxide layer and the dummy poly layer are intersected with the gate oxide layer over a fin layer of the FinFET. | 07-23-2015 |
Chao-Cheng Chen, Taoyuan County TW
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20150231285 | RADIOLABELED ACTIVE TARGETING PHARMACEUTICAL COMPOSITION AND THE USE THEREOF - The present invention is related to a radiolabeled active targeting pharmaceutical composition, including: a bioconjugate and a radionuclide, wherein the bioconjugate includes a biomolecule and a metal nanoparticle, wherein the biomolecule has an affinity for receptors on the surface of a cell membrane and is selected from the group consisting of a peptide and a protein. The present invention further provides a method for evaluating a thermal adjuvant therapy for tumors and a kit thereof. The above-mentioned pharmaceutical composition is applied to evaluate a tumor accumulation time, so as to establish the optimal policy for a radiofrequency- or laser-induced thermal adjuvant therapy for tumors. | 08-20-2015 |
Chao-Cheng Chen, Hsin-Chu TW
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20080303102 | Strained Isolation Regions - An isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure. | 12-11-2008 |
20090045482 | Shallow Trench Isolation with Improved Structure and Method of Forming - A shallow trench isolation (STI) structure has a top portion tapering in width from wide to narrow in a direction from a substrate surface, from a first width at a top of the first portion to a second width at a bottom of the first portion. The STI structure also includes a bottom portion below the top portion, which expands from the bottom of the top portion to a substantially widened lateral distance having a third width. The third width is, in general, substantially larger than the second width. The inventive STI structure can provide desired isolation characteristics with a significantly reduced aspect ratio, thus suitable for device isolations in advanced processing technology. | 02-19-2009 |
20120149171 | Shallow Trench Isolation with Improved Structure and Method of Forming - A shallow trench isolation (STI) structure and methods of forming a STI structure are disclosed. An embodiment is a method for forming a semiconductor structure. The method includes forming a recess in a semiconductor substrate; forming a first material on sidewalls of the recess; forming a widened recessed portion through a bottom surface of the recess; removing the first material from the sidewalls of the recess; and forming a dielectric material in the recess and the widened recessed portion. The bottom surface of the recess is exposed through the first material, and the bottom surface of the recess has a first width. The widened recessed portion has a second width. The second width is greater than the first width. | 06-14-2012 |
20130277759 | Semiconductor Fin Structures and Methods for Forming the Same - A device includes a semiconductor substrate, and a plurality of semiconductor fins parallel to each other, wherein the plurality of semiconductor fins is a portion of the semiconductor substrate. A Shallow Trench Isolation (STI) region is on a side of the plurality of semiconductor fins. The STI region has a top surface and a non-flat bottom surface, wherein the plurality of semiconductor fins is over the top surface of the STI region. | 10-24-2013 |
20130320410 | METAL GATE ELECTRODE OF A SEMICONDUCTOR DEVICE - The invention relates to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first rectangular gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first rectangular gate electrode; and a second dielectric material adjacent to the other 3 sides of the first rectangular gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first rectangular gate electrode. | 12-05-2013 |
20140183661 | FinFET Device Structure and Methods of Making Same - Embodiments of the present disclosure are a method of forming a semiconductor device, a method of forming a FinFET device, a FinFET device. An embodiment a method for semiconductor device, the method comprising forming a first dielectric layer over a substrate, forming a first hardmask layer over the first dielectric layer, and patterning the first hardmask layer to form a first hardmask portion with a first width. The method further comprises forming a first raised portion of the first dielectric layer with the first width, wherein the first raised portion is aligned with the first hardmask portion, and forming a first spacer and a second spacer over the first dielectric layer, wherein the first spacer and the second spacer are on opposite sides of the first raised portion, and wherein the sidewalls of the first spacer and the second spacer are substantially orthogonal to the top surface of the substrate. | 07-03-2014 |
20140242776 | Strained Isolation Regions - A method of forming an isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure. | 08-28-2014 |
20140252486 | Fin Shape For Fin Field-Effect Transistors And Method Of Forming - A fin field-effect transistor (finFET) and a method of forming are provided. A gate electrode is formed over one or more fins. Notches are formed in the ends of the gate electrode along a base of the gate electrode. Optionally, an underlying dielectric layer, such as a shallow trench isolation, may be recessed under the notch, thereby reducing gap fill issues. | 09-11-2014 |
20140256093 | FinFET Device Structure and Methods of Making Same - Embodiments of the present disclosure are a method of forming a semiconductor device and a method of forming a FinFET device. An embodiment is a method of forming a semiconductor device, the method including forming a first dielectric layer over a substrate, forming a first hardmask layer on the first dielectric layer, and patterning the first hardmask layer to form a first hardmask portion with a first width. The method further includes forming a second dielectric layer on the first dielectric layer and the first hardmask portion, forming a third dielectric layer on the second dielectric layer, and etching the third dielectric layer and a portion of the second dielectric layer to form a first and second spacer on opposite sides of the first hardmask portion. | 09-11-2014 |
20140256094 | FinFETs and Methods for Forming the Same - Methods for forming a semiconductor device and a FinFET device are disclosed. A method comprises forming a dummy gate electrode layer over a substrate, the dummy gate electrode layer having a first height, forming a first etch stop layer on the dummy gate electrode layer, forming a first hard mask layer on the first etch stop layer, and patterning the first hard mask layer. The method further comprises patterning the first etch stop layer to align with the patterned first hard mask layer, and patterning the gate electrode layer to form a dummy gate electrode, the dummy gate electrode aligning with the patterned first etch stop layer, wherein after the patterning the gate electrode layer the first hard mask layer has a vertical sidewall of a second height, the second height being less than the first height, and the first hard mask layer having a rounded top surface. | 09-11-2014 |
20140264491 | Semiconductor Strips with Undercuts and Methods for Forming the Same - An integrated circuit device includes a semiconductor substrate, and a semiconductor strip extending into the semiconductor substrate. A first and a second dielectric region are on opposite sides of, and in contact with, the semiconductor strip. Each of the first dielectric region and the second dielectric region includes a first portion level with the semiconductor strip, and a second portion lower than the semiconductor strip. The second portion further includes a portion overlapped by the semiconductor strip. | 09-18-2014 |
20140273380 | FinFETs with Regrown Source/Drain and Methods for Forming the Same - A method includes etching a semiconductor substrate to form a recess in the semiconductor substrate, and reacting a surface layer of the semiconductor substrate to generate a reacted layer. The surface layer of the semiconductor substrate is in the recess. The reacted layer is then removed. An epitaxy is performed to grow a semiconductor material in the recess. | 09-18-2014 |
20140302653 | Finlike Structures and Methods of Making Same - Semiconductor materials, particularly III-V materials used to form, e.g., a finlike structure can suffer structural damage during chemical mechanical polishing steps. This damage can be reduced or eliminated by oxidizing the damaged surface of the material and then etching away the oxidized material. The etching step can be accomplished simultaneously with a step of etching back a patterned oxide layers, such as a shallow trench isolation layer. | 10-09-2014 |
20150024566 | Finlike Structures and Methods of Making Same - Semiconductor materials, particularly III-V materials used to form, e.g., a finlike structure can suffer structural damage during chemical mechanical polishing steps. This damage can be reduced or eliminated by oxidizing the damaged surface of the material and then etching away the oxidized material. The etching step can be accomplished simultaneously with a step of etching back a patterned oxide layers, such as a shallow trench isolation layer. | 01-22-2015 |
20150118815 | FinFET Device Structure and Methods of Making Same - Embodiments of the present disclosure are a method of forming a semiconductor device, a method of forming a FinFET device, a FinFET device. An embodiment a method for semiconductor device, the method comprising forming a first dielectric layer over a substrate, forming a first hardmask layer over the first dielectric layer, and patterning the first hardmask layer to form a first hardmask portion with a first width. The method further comprises forming a first raised portion of the first dielectric layer with the first width, wherein the first raised portion is aligned with the first hardmask portion, and forming a first spacer and a second spacer over the first dielectric layer, wherein the first spacer and the second spacer are on opposite sides of the first raised portion, and wherein the sidewalls of the first spacer and the second spacer are substantially orthogonal to the top surface of the substrate. | 04-30-2015 |
20150132910 | FinFET Device Structure and Methods of Making Same - Embodiments of the present disclosure are a method of forming a semiconductor device and a method of forming a FinFET device. An embodiment is a method of forming a semiconductor device, the method including forming a first dielectric layer over a substrate, forming a first hardmask layer on the first dielectric layer, and patterning the first hardmask layer to form a first hardmask portion with a first width. The method further includes forming a second dielectric layer on the first dielectric layer and the first hardmask portion, forming a third dielectric layer on the second dielectric layer, and etching the third dielectric layer and a portion of the second dielectric layer to form a first and second spacer on opposite sides of the first hardmask portion. | 05-14-2015 |
20150137195 | Gate Protection Caps and Method of Forming the Same - A structure includes a substrate, a gate structure over the substrate, a dielectric layer over the substrate, and a cap over a gate electrode of the gate structure. Top surfaces of the dielectric layer and gate electrode are co-planar. The gate structure extends a gate lateral distance between first and second gate structure sidewalls. The cap extends between first and second cap sidewalls. A first cap portion extends from a midline of the gate structure laterally towards the first gate structure sidewall and to the first cap sidewall a first cap lateral distance, and a second cap portion extends from the midline laterally towards the second gate structure sidewall and to the second cap sidewall a second cap lateral distance. The first cap lateral distance and the second cap lateral distance are at least half of the gate lateral distance. | 05-21-2015 |
20150228544 | Fin Shape For Fin Field-Effect Transistors And Method Of Forming - A fin field-effect transistor (finFET) and a method of forming are provided. A gate electrode is formed over one or more fins. Notches are formed in the ends of the gate electrode along a base of the gate electrode. Optionally, an underlying dielectric layer, such as a shallow trench isolation, may be recessed under the notch, thereby reducing gap fill issues. | 08-13-2015 |
20150325417 | METHODS FOR REMOVING PARTICLES FROM ETCHING CHAMBER - A method includes forming a coating layer in a dry etching chamber, placing a wafer into the dry etching chamber, etching a metal-containing layer of the wafer, and moving the wafer out of the dry etching chamber. After the wafer is moved out of the dry etching chamber, the coating layer is removed. | 11-12-2015 |
20150340474 | FinFETs and Methods for Forming the Same - Methods for forming a semiconductor device and a FinFET device are disclosed. A method comprises forming a dummy gate electrode layer over a substrate, the dummy gate electrode layer having a first height, forming a first etch stop layer on the dummy gate electrode layer, forming a first hard mask layer on the first etch stop layer, and patterning the first hard mask layer. The method further comprises patterning the first etch stop layer to align with the patterned first hard mask layer, and patterning the gate electrode layer to form a dummy gate electrode, the dummy gate electrode aligning with the patterned first etch stop layer, wherein after the patterning the gate electrode layer the first hard mask layer has a vertical sidewall of a second height, the second height being less than the first height, and the first hard mask layer having a rounded top surface. | 11-26-2015 |
20150348845 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes: providing a workpiece having a recess and a dielectric layer lining the recess; forming a conductive structure within the recess, wherein the conductive structure partially fills the recess; and recessing the dielectric layer, wherein, after the recessing, a top surface of the recessed dielectric layer is disposed within the recess. | 12-03-2015 |
20150357164 | PROCESS CHAMBER, METHOD OF PREPARING A PROCESS CHAMBER, AND METHOD OF OPERATING A PROCESS CHAMBER - Process chambers and methods of preparing and operating a process chamber are disclosed. In some embodiments, a method of preparing a process chamber for processing a substrate includes: forming a first barrier layer over an element disposed within a cavity of the process chamber, the element comprising an outgassing material; and forming, within the process chamber, a second barrier layer over the first barrier layer. | 12-10-2015 |
Chao-Cheng Chen, Tainan City TW
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20130047101 | PERSONAL SERVICE MENU CONSTRUCTION SYSTEM AND METHOD AND PERSONAL SERVICE MENU PROVISION METHOD THEREOF - A personal service menu construction system is provided for an application software to construct a homemade function menu, including: a selection module for setting required function options from a plurality of function options of the application software; an integration module for receiving the function options set by the selection module such that the function options set by the selection module are edited or packaged and integrated as a personal service menu; and a construction module for inputting the personal service menu to the application software. A personal service menu provision method is provided such that the personal service menu can be saved in a storage device and inputted to the same application software of another electronic device. | 02-21-2013 |
Chao-Cheng Chen, New Taipei City TW
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20150362239 | VARIABLE FREQUENCY CONTROL APPARATUS - A variable frequency control apparatus includes a variable frequency controller, and at least one temperature sensor, and the variable frequency controller is installed at a compressor of an air-conditioning equipment and electrically coupled to the compressor, and the temperature sensor is installed at a position where a refrigerant pipeline passes through the compressor. A temperature change of the refrigerant passing through the compressor is used as a basis for determining whether an air-conditioning host of the air-conditioning equipment situated in an indoor space has reached a predetermined air-conditioning effect, so as to control and adjust a rotational speed of the compressor and drive the compressor of a constant frequency air-conditioning equipment to produce a variable frequency operation effect. | 12-17-2015 |
Chao-Cheng Chen, Hsin-Chu City TW
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20150270397 | BOTTLE-NECK RECESS IN A SEMICONDUCTOR DEVICE - A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess. | 09-24-2015 |
20150364383 | METHOD OF CALIBRATING OR EXPOSING A LITHOGRAPHY TOOL - A method of calibrating or monitoring an exposing tool including forming a substrate pattern in a substrate, wherein forming the substrate pattern includes providing a first patterned photo resist layer having an etch coating layer disposed thereon and using the first patterned photo resist layer and the etch coating layer to pattern an underlying layer. The patterned underlying layer is then used as a masking element when etching the substrate pattern into the substrate. A second photo resist pattern is formed over the substrate pattern. An overlay measurement is executed of the second photo resist pattern to the substrate pattern. | 12-17-2015 |
20160093715 | DUMMY GATE STRUCTURE AND METHODS THEREOF - A structure and method for implementation of dummy gate structures within multi-gate device structures includes a semiconductor device including an isolation region that separates a first and second active region. The first active region is adjacent to a first side of the isolation region and the second active region is adjacent to a second side of the isolation region. A device including a source, a drain, and a gate is formed within the first active region. One of the source and drain regions are disposed adjacent to the isolation region. A dummy gate is formed at least partially over the isolation region and adjacent to the one of the source and drain regions. In various examples, the gate includes a first dielectric layer having a first thickness and the dummy gate includes a second dielectric layer having a second thickness greater than the first thickness. | 03-31-2016 |
20160099151 | Etching Process - A method includes providing a semiconductor substrate; forming a doping oxide layer on the semiconductor substrate; forming a patterning layer on the doping oxide layer, the patterning layer leaving exposed regions of the doping oxide layer; performing a sputtering process to the substrate; and after the sputtering process, performing a wet etching process to the semiconductor substrate to remove the doping oxide layer from the exposed regions. | 04-07-2016 |
20160111297 | ITERATIVE SELF-ALIGNED PATTERNING - A method for self-aligned patterning includes providing a substrate, forming a patterned mandrel layer that includes a plurality of mandrel features, the patterned mandrel layer being formed on the substrate, depositing a first spacer layer over the mandrel layer, the first spacer layer comprising a first type of material, anisotropically etching the first spacer layer to leave a first set of spacers on sidewalls of the mandrel features, removing the mandrel layer, depositing a second spacer layer over remaining portions of the first set of spacers, and anisotropically etching the second spacer layer to form a second set of spacers on sidewalls of the first set of spacers. | 04-21-2016 |
Chao-Cheng Chen, Hsinchu City TW
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20150104913 | Simultaneous Formation of Source/Drain Openings with Different Profiles - A method includes forming a first gate stack and a second gate stack over a first portion and a second portion, respectively, of a semiconductor substrate, masking the first portion of the semiconductor substrate, and with the first portion of the semiconductor substrate being masked, implanting the second portion of the semiconductor substrate with an etch-tuning element. The first portion and the second portion of the semiconductor substrate are etched simultaneously to form a first opening and a second opening, respectively, in the semiconductor substrate. The method further includes epitaxially growing a first semiconductor region in the first opening, and epitaxially growing a second semiconductor region in the second opening. | 04-16-2015 |
Chao-Cheng Chen, Kaohsiung City TW
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20150183910 | METHOD FOR PREPARING A FLAME RETARDANT MODIFIED ACRYLONITRILE-BASED COPOLYMER AND A FLAME RETARDANT FIBROUS MATERIAL - A method for preparing a flame retardant modified acrylonitrile-based copolymer, includes: prepolymerizing a first composition to obtain a first prepolymer solution including a first prepolymer; prepolymerizing a second composition to obtain a second prepolymer solution including a second prepolymer; and mixing the first and second prepolymer solutions and subjecting a mixture of the first and second prepolymers to polymerization to obtain a flame retardant modified acrylonitrile-based copolymer solution containing a flame retardant modified acrylonitrile-based copolymer. | 07-02-2015 |
Chao-Cheng Chiang, Xizhi City TW
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20100179146 | Indolinone Compounds as Kinase Inhibitors - Indolinone compounds of formula (I) or (II): | 07-15-2010 |
Chao-Cheng Hsu, Yilan County TW
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20100061790 | LABEL ROLL HOLDER RETURNING MECHANISM FOR BARCODE PRINTER - A label roll holder returning mechanism is provided for a barcode printer and includes at least one restoration roller, a coiled resilient element, at least two movable rails, and at least two label roll holding elements. The restoration roller is rotatably mounted to a bottom of the barcode printer and has a top portion forming a positive-movement engagement section. The coiled resilient element is received inside the restoration roller to provide a restoration force to the rotation of the restoration roller. The movable rails are set to the bottom of the barcode printer in a substantially parallel manner. Each movable rail has a surface forming at least one counterpart positive-movement engagement section engaging the positive-movement engagement section of the restoration roller. The label roll holding elements are arranged at a top of the barcode printer and are coupled to the movable rails respectively, whereby the label roll holding elements offer the function of outward separating from each other for removing and installing a roll of label and inward approaching each other to clamp and hold the label roll by means of the engagement between the restoration roller and the movable rails and the restoration force thereof. As such, a label roll holder returning mechanism featuring balanced force restoration is provided. | 03-11-2010 |
Chao-Cheng Lin, Hsinchu TW
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20090033813 | MULTI-DOMAIN LIQUID CRYSTAL DISPLAY - A multi-domain liquid crystal display (LCD) including an active device array substrate, an opposite substrate, an electric field shielding layer, and a liquid crystal layer is provided. The active device array substrate has a plurality of pixels, wherein each pixel has a pixel electrode. The opposite substrate has a common electrode disposed between the opposite substrate and the active device array substrate. The electric field shielding layer is disposed on a part of each pixel electrode. The liquid crystal layer is disposed between the active device array substrate and the opposite substrate. The liquid crystal layer corresponding to each pixel is divided into a low-voltage domain and a high-voltage domain having the same cell gap, wherein the position of the electric field shielding layer is corresponding to the position of the low-voltage domain. Color shift of the multi-domain LCD is improved effectively at oblique viewing angles. | 02-05-2009 |
20090130413 | THINNED SUBSTRATE, MANUFACTURING PROCESS THEREOF, AND MANUFACTURING PROCESS OF DISPLAY PANEL APPLYING THE SAME - A thinned substrate for a display panel and manufacturing process thereof are provided. The thinned substrate includes an inorganic transparent plate and a supporting layer to form a stacked layer. The supporting layer avails improvement of structure strength of the thinned substrate and reliability of the thinned substrate. A ratio between thickness of the inorganic transparent plate and thickness of the supporting layer is substantially less than or substantially equal to 4. A total thickness of the stacked layer is substantially less than or substantially equal to 20 mm. Bending strength of the stacked layer is substantially greater than or substantially equal to 150 MPa. Besides, a manufacturing process of the display panel applying said thinned substrate is also provided. | 05-21-2009 |
20100117944 | LIQUID CRYSTAL DISPLAY PANEL - A liquid crystal display panel includes a display region, a periphery circuit region, a joint obligate region, a plurality of first test thin-film transistors (TFTs), a plurality of second TFTs, a plurality of first lines, a plurality of second lines, a blank region, and at least one first adjustment TFT. The first and second test TFTs are disposed on the joint obligate region according to a regular distance. Each of the first and second test TFTs has a transistor width. The first adjustment TFT is disposed on the blank region. The width of the blank region is not smaller than the sum of the twice regular distance and the transistor width. Thereby, the present invention can prevent the band mura of the liquid crystal display panel effectively when the liquid crystal display panel is in testing. | 05-13-2010 |
Chao-Cheng Lin, Taichung TW
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20110059592 | NONVOLATILE MEMORY AND FABRICATION METHOD THEREOF - Non-volatile memories formed on a substrate and fabrication methods are disclosed. A bottom electrode comprising a metal layer is disposed on the substrate. A buffer layer comprising a LaNiO | 03-10-2011 |
Chao-Cheng Lin, New Taipei City TW
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20130021526 | REMOTE CONTROL METHOD, AND SYSTEM, RECEIVING DEVICE, MOBILE INTERNET DEVICE AND RECORDING MEDIUM FOR IMPLEMENTING THE SAME - A remote control method comprises: providing a receiving device electrically connected with a display device; the receiving device establishing wireless communication connections respectively with a mobile internet device and a computer; a user inputting a control instruction to the mobile internet device to transmit the control instruction to the receiving device therefrom; the receiving device forwarding the control instruction to the computer; and the computer responding to the control instruction and transmitting a screen frame to the receiving device for the display device to output the screen frame. The remote control method may simplify the operating procedures for switching computers and enhance the communication quality between the mobile internet device and the computer. | 01-24-2013 |
Chao-Cheng Lin, Hsin-Chu TW
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20090128760 | FLAT DISPLAY PANEL HAVING STRENGTH ENHANCING STRUCTURE - A flat display panel includes a first substrate, a second substrate opposite to the first substrate, a sealant disposed between the first and second substrates. The sealant, the edge of the inner surface of the first substrate, and the edge of the inner surface of the second substrate form a space, and the flat display panel further includes a protection layer disposed inside the space so as to reinforce the structural strength of the flat display panel. | 05-21-2009 |
20090258565 | Method for Manufacturing Display Panel within Substrates having Different Thickness - The present invention provides a method for manufacturing display panel with substrates having different thickness. The display panel manufacturing method includes assembling a first substrate and a second substrate, positioning the anti-etching layer on the outer surface of the first substrate and etching the substrates at the first etching process. Because the anti-etching layer is disposed on the first substrate, the first substrate is protected by the anti-etching layer from being etched or later etched. Simultaneously, the second substrate is etched to reduce its thickness in order to adjust the thickness difference between the first substrate and the second substrate. | 10-15-2009 |
Chao-Cheng Liu, Gangshan Township TW
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20090267210 | INTEGRATED CIRCUIT PACKAGE AND MANUFACTURING METHOD THEREOF - An integrated circuit package and a manufacturing method thereof are provided. The package includes a die pad, a plurality of first and second contact pads, a first die, a second die and a molding compound. The contact pads adjacent to at least one side of the die pad are arranged along an inner row and an outer row with respect to the die pad. The first die is fixed on the first die and electrically connected to the first contact pads by wire-bonding. The second die is fixed on the first die and electrically connected to the second contact pads by wire-bonding. The molding compound covers the second die, the first die, the die pad, the first contact pads and the second contact pads. The bottoms of the die pad, the first contact pads and the second contact pads are exposed at the bottom surface of the molding compound. | 10-29-2009 |
Chao-Cheng Su, Kaohsiung City TW
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20160087706 | Synchronization in a Beamforming System - A beamforming system synchronization architecture is proposed to allow a receiving device to synchronize to a transmitting device in time, frequency, and spatial domain in the most challenging situation with very high pathloss. A periodically configured time-frequency resource blocks in which the transmitting device uses the same beamforming weights for its control beam transmission to the receiving device. A pilot signal for each of the control beams is transmitted in each of the periodically configured time-frequency resource blocks. Pilot symbols are inserted into pilot structures and repeated for L times in each pilot structure. The L repetitions can be implemented by one or more Inverse Fast Fourier Transfers (IFFTs) with corresponding one or more cyclic prefix (CP) lengths. | 03-24-2016 |
20160087707 | Synchronization in a Beamforming System - A beamforming system synchronization architecture is proposed to allow a receiving device to synchronize to a transmitting device in time, frequency, and spatial domain in the most challenging situation with very high pathloss. A detector at the receiving device detects the presence of control beams, synchronizes to the transmission and estimates the channel response by receiving pilot signals. The detector has low complexity when exploiting the structure of the pilot signals. The detector consists of three stages that break down the synchronization procedure into less complicated steps. The detector accurately estimates the parameters required for identifying the transmit device and performing subsequent data communication. | 03-24-2016 |
20160087765 | Synchronization in a Beamforming System - A beamforming system synchronization architecture is proposed to allow a receiving device to synchronize to a transmitting device in time, frequency, and spatial domain in the most challenging situation with very high pathloss. A periodically configured time-frequency resource blocks in which the transmitting device uses the same beamforming weights for its control beam transmission to the receiving device. A pilot signal for each of the control beams is transmitted in each of the periodically configured time-frequency resource blocks. The same synchronization signal can be used for all stages of synchronization including initial coarse synchronization, device and beam identification, and channel estimation for data demodulation. | 03-24-2016 |
Chao-Cheng Tu, Brossard CA
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20160044729 | METHODS AND APPARATUS FOR DETERMINING DEVICE-TO-DEVICE TRANSMISSION PATTERNS - Embodiments include methods and apparatuses for the design, construction and selection of base patterns and associated control signaling for direct device-to-device (D2D) communication, independent of a network. An embodiment includes the selection and transmission, by a wireless transmit and receive unit (WTRU), of base patterns in a scheduling period when the number of medium access control (MAC) protocol data units (PDUs) is larger than the number of MAC PDUs that a family of pre-determined base patterns can support. An embodiment may include the selection and transmission, by a WTRU, of base patterns in a scheduling period when the number of MAC PDUs is smaller than the number of MAC PDUs that a family of pre-determined base patterns can support. In addition, embodiments may include the selection, by a WTRU, of a base pattern or base patterns to minimize interference with other communications and to use resources efficiently. | 02-11-2016 |
Chao-Cheng Wang, Tainan City TW
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20160091732 | EYEWEAR TEMPLE - The eyewear temple has a temple body and a resilient assembly. The resilient assembly is mounted in the chamber of the temple body and has a guide member and a connecting rod. The guide member has a recess, a shaft hole, an opening and a through hole. The recess is axially formed in the guide member. The shaft hole is radially formed through the guide member. The opening is formed on a front surface of the guide member. The through hole is formed in a rear surface of the guide member. The connecting rod is easy to be directly inserted through the opening and the recess of the guide member, and is connected to the temple body. Therefore, the resilient assembly is easy to be assembled on the temple body, and the combination strength between the temple body and the connecting rod is easy to be adjusted. | 03-31-2016 |
Chao-Cheng Wang, Nantou City TW
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20120088318 | Method for Fabricating a Vertical Light-Emitting Diode with High Brightness - A method for fabricating a vertical light-emitting diode comprises forming a stack including a plurality of epitaxial layers on a patterned first substrate, placing a second substrate on the stack, removing the first substrate to expose the first surface, planarizing a first surface of the stack that was in contact with the patterned first substrate and has a pattern corresponding to a pattern provided on the first substrate to form a planarized second surface, and forming a first electrode in contact with a side of the second substrate that is opposite to the stack, and a second electrode in contact with the second surface of the stack. A roughening step can be performed to form uneven surface portions on a region of the second surface for improving light emission through the second surface of the stack. | 04-12-2012 |
Chao-Cheng Wen, Hsinchu County TW
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20140340355 | TOUCH CONTROL SYSTEM AND SIGNAL PROCESSING METHOD THEREOF - A signal processing method for a touch panel is provided. The touch panel includes a first sensing region and a second sensing region. The first sensing region is monitored by at least one first sensor to generate a first monitoring result. The second sensing region is monitored by at least one second sensor to generate a second monitoring result. The signal processing method includes determining whether a touch point formed in the first sensing region is close to the second sensing region, and generating position information of the touch point according to the first monitoring result and the second monitoring result when the touch point is close to the second sensing region. | 11-20-2014 |
Chao-Cheng Wen, Zhunan Township TW
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20140118282 | METHOD AND ASSOCIATED METHOD FOR COORDINATE CORRECTION OF TOUCH CONTROL - A method for coordinate correction of touch control is provided. An original x-coordinate and an original y-coordinate are corrected according to a total sensing value, the original x-coordinate and the original y-coordinate provided by touch sensing of a touch panel. The method includes providing an estimated x-axis correction value according to the original x-coordinate and the total sensing value, generating a corrected x-coordinate according to the estimated x-axis correction value and the original x-coordinate, and providing a corrected y-coordinate according to the original x-coordinate, the corrected x-coordinate and the total sensing value. | 05-01-2014 |
20140218323 | TOUCH DETECTION METHOD AND ASSOCIATED APPARATUS - A method for touch detection is provided for detecting a touch point on a display device. The method includes: providing a display signal, according to which the display device has two parts of a vertical blanking interval within each frame period, wherein the two parts of the vertical blanking interval are discontinuous; and performing a touch detection in the two parts of the vertical blanking interval, respectively. The touch detection method is capable of performing multiple touch detections within one frame period. | 08-07-2014 |
20150029147 | METHOD FOR DESIGNING PATTERN OF SENSING CHANNELS IN TOUCH PANEL - A method for designing a pattern of sensing channels is provided. The method is applied to a touch panel including a plurality of electrodes and a plurality of sections of sensing channels. The electrodes are connected to a plurality of sensors for the touch panel via the sections of sensing channels. According to a minimum sensing channel width, a minimum sensing channel gap, a maximum distribution width and lengths of the sections of sensing channels, a set of rules are established. According to the set of rules, a programming process is utilized to determine respective widths of the sections of sensing channels. | 01-29-2015 |
Chao-Cheng Wen, Hsinchu Hsien TW
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20110025628 | Method for Determining Touch Point Displacement and Associated Apparatus - A method for determining a displacement of a touch point is applied to a touch panel to reduce noise interfering with determination of the displacement. The method includes obtaining a displacement according to a movement of a touch point on the touch panel; checking whether the displacement is within a predetermined range; and determining that the movement is valid when the displacement is within the predetermined range. | 02-03-2011 |
20110242022 | Touch Determining Method and Determining Method of Touch Gesture on a Touch Panel - A determining method of touch gesture on a touch panel is provided to avoid misjudgment of determination of a multi-finger touch as a single-finger touch. The method includes determining whether a first valid touch is present on the touch panel; determining whether a second valid touch is present on the touch panel within a predetermined time period when the first valid touch is continuously present within the predetermined time period; generating a first hand gesture instruction when the second valid touch is not detected during the predetermined time period; and generating a second hand gesture instruction when the second valid touch is detected within the predetermined time period. | 10-06-2011 |
20110242025 | Hand Gesture Recognition Method for Touch Panel and Associated Apparatus - A hand gesture recognition method according to the present disclosure is applied to a touch panel comprising a plurality of sensors, each of which generating a sensing value according to a touch operation. The method includes providing a first reference value and a second reference value; generating a count value by counting a quantity of the sensing values that are greater than a threshold; determining the touch operation as a first hand gesture when the count value is greater than the first reference value but smaller than the second reference value; and determining the touch operation as a second hand gesture when the count value is greater than the second reference value. | 10-06-2011 |
20130162588 | Signal Processing Method for Touch Panel and Touch Panel System - A signal processing method for a touch panel is provided. The touch panel includes several capacitor electrodes. The method includes the following steps. Detection values are provided according to self-capacitance changes of the capacitor electrodes. The detection values are then low-pass filtered by a filter structure to generate several filtered values. A position where a touch event occurs on the touch panel is determined according to the filtered values. | 06-27-2013 |
Chao-Cheng Wu, New Taipei City TW
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20140133921 | OFFSHORE INSTALLATION METHOD OF A WIND POWER GENERATOR AND ITS FABRICATION SEGMENTS - The invention relates to an offshore installation method of a wind power generator and its fabrication segments. A prefabricated wind power generator is finished at a first location, and then carried by a ship to a second location for installation, largely saving installation time. With a tower inserted down through a base to shrink height of the generator, the ship can not only effectively diminish shaking posed by wind and sea waves, advancing steadiness of delivery, but also be one with smaller tonnage to save cost. | 05-15-2014 |
Chao-Cheng Wu, Tamshui TW
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20110097207 | PRESSURE RELIEF DEVICE - A pressure relief device includes a main body and at least two air control units. The main body has at least one passage therein and two outlets formed at upper and lower ends of the passage. A lid is pivotally connected to each of the outlets. The two air control units are each disposed in the passage close to the lid. An air control device drives the air control units to open/close the lid which is adapted to open/close the passage. | 04-28-2011 |