Gurrum
Siva P. Gurrum, Irving, TX US
Patent application number | Description | Published |
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20100301470 | STUD BUMPS AS LOCAL HEAT SINKS DURING TRANSIENT POWER OPERATIONS - A thermal management configuration for a flip chip semiconductor device is disclosed. The device includes a high power silicon based die having a metal bonding surface. A plurality of interconnects are formed on the metal surface and connected to a substrate. A plurality of thermal management stud bumps are formed on the metal bonding surface, the thermal management stud bumps positioned distinct from the interconnects and local to die hot spots, exposed ends of the thermal management stud bumps spaced from the substrate. | 12-02-2010 |
Siva P. Gurrum, Dallas, TX US
Patent application number | Description | Published |
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20090026605 | Heat Extraction from Packaged Semiconductor Chips, Scalable with Chip Area - A semiconductor device ( | 01-29-2009 |
20090267218 | Heat Extraction from Packaged Semiconductor Chips, Scalable with Chip Area - A semiconductor device ( | 10-29-2009 |
20140038358 | METHOD FOR CONTACTING AGGLOMERATE TERMINALS OF SEMICONDUCTOR PACKAGES - In fabricating a semiconductor device first layers are formed of sintered bondable and solderable metal on a carrier strip. The first layers are patterned into first pads and second pads. A set of first pads is surrounding each second pad. The first pads are spaced from the second pad by gaps. The patterned layers are formed of agglomerate metal vertically on the first layers of sintered bondable and solderable metal of the first pads and of the second pad. The second layers are formed of sintered bondable and solderable metal vertically on the layers of agglomerate metal of the first pads | 02-06-2014 |
Siva P. Gurrum, Allen, TX US
Patent application number | Description | Published |
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20160035655 | Semiconductor Package Having Etched Foil Capacitor Integrated Into Leadframe - A packaged semiconductor device including a leadframe and a plurality of angularly shaped capacitors. The leadframe includes structures with surfaces and sidewalls. The angularly shaped capacitors are attached to surface portions of the leadframe structures. The angularly shaped capacitors have sidewalls coplanar with structure sidewalls. The angularly shaped capacitors includes a conductive material attached to the structure surface. The conductive material having pores covered by oxide and filled with conductive polymer. The angularly shaped capacitors topped by electrodes are made of a second metal. | 02-04-2016 |
Siva Prakash Gurrum, Irving, TX US
Patent application number | Description | Published |
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20110027943 | Stud Bumps as Local Heat Sinks During Transient Power Operations - A thermal management configuration for a flip chip semiconductor device is disclosed. The device includes a high power silicon based die having a metal bonding surface. A plurality of interconnects are formed on the metal surface and connected to a substrate. A plurality of thermal management stud bumps are formed on the metal bonding surface, the thermal management stud bumps positioned distinct from the interconnects and local to die hot spots, exposed ends of the thermal management stud bumps spaced from the substrate. | 02-03-2011 |
Siva Prakash Gurrum, Dallas, TX US
Patent application number | Description | Published |
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20090212418 | THERMAL INTERFACE MATERIAL DESIGN FOR ENHANCED THERMAL PERFORMANCE AND IMPROVED PACKAGE STRUCTURAL INTEGRITY - An electronic package comprising a semiconductor device, a heat spreader layer, and a thermal interface material layer located between the semiconductor device and the heat spreader layer. The thermal interface material layer includes a resin layer having heat conductive particles suspended therein. A portion of the particles are exposed on at least one non-planar surface of the resin layer such that the portion of exposed particles occupies a majority of a total area of a horizontal plane of the non-planar surface. | 08-27-2009 |
20090289648 | COAXIAL FOUR-POINT PROBE FOR LOW RESISTANCE MEASUREMENTS - Various exemplary embodiments provide probes, systems and methods for measuring an effective electrical resistance/resistivity with high sensitivity. In one embodiment, the measuring system can include an upper probe set and a similar lower probe set having a sample device sandwiched there-between. The device-under-test (DUT) samples can be sandwiched between two conductors of the sample device. Each probe set can have an inner voltage sense probe coaxially configured inside an electrically-isolated outer current source probe that has a large contact area with the sample device. The measuring system can also include a computer readable medium for storing circuit simulations including such as FEM simulations for extracting a bulk through-plane electrical resistivity and an interface resistivity for an effective electrical z-resistivity of the DUT, in some cases, having sub-micro-ohm resistance. | 11-26-2009 |
20110204506 | Thermal Interface Material Design for Enhanced Thermal Performance and Improved Package Structural Integrity - An electronic package | 08-25-2011 |
20120194208 | Coaxial Four-Point Probe for Low Resistance Measurements - Various exemplary embodiments provide probes, systems and methods for measuring an effective electrical resistance/resistivity with high sensitivity. In one embodiment, the measuring system can include an upper probe set and a similar lower probe set having a sample device sandwiched there-between. The device-under-test (DUT) samples can be sandwiched between two conductors of the sample device. Each probe set can have an inner voltage sense probe coaxially configured inside an electrically-isolated outer current source probe that has a large contact area with the sample device. The measuring system can also include a computer readable medium for storing circuit simulations including such as FEM simulations for extracting a bulk through-plane electrical resistivity and an interface resistivity for an effective electrical z-resistivity of the DUT, in some cases, having sub-micro-ohm resistance. | 08-02-2012 |
20120211889 | METHOD FOR CONTACTING AGGLOMERATE TERMINALS OF SEMICONDUCTOR PACKAGES - A plastic package ( | 08-23-2012 |
Siva Prakash Gurrum, Allen, TX US
Patent application number | Description | Published |
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20140129166 | ON-TIME BASED PEAK CURRENT DENSITY RULE AND DESIGN METHOD - A method of computing a peak current density specification (j | 05-08-2014 |