Patent application number | Description | Published |
20090185440 | ACTIVE CYCYLE CONTROL CIRCUIT FOR SEMICONDUCTOR MEMORY APPARATUS - An active cycle control circuit for a semiconductor memory apparatus is configured to precharge a word line corresponding to a read cycle, and activate a word line corresponding to a refresh request signal in response to the refresh request signal generated during the read cycle. | 07-23-2009 |
20110026344 | DATA CONTROL CIRCUIT - The data control circuit includes an input/output line and a driver. The input/output line precharging circuit precharges a global input/output line to a predetermined voltage when either a reading operation or a writing operation is inoperative. The driver includes a number of MOS transistors and drives the global input/output line in response to receiving data from a local input/output line and a complementary local input/output line during the reading operation. | 02-03-2011 |
20110102025 | DATA OUTPUT CIRCUIT - The data output circuit includes a first decoder, a second decoder, a first selective output circuit, a second selective output circuit, and an output driver. The first decoder is configured to generate a pull-up selection signal by decoding a pull-up code. The second decoder is configured to generate a pull-down selection signal by decoding a pull-down code. The first selective output circuit is configured to select and output a voltage level of a pull-up level signal in response to the pull-up selection signal. The second selective output circuit is configured to select and output a voltage level of a pull-down level signal in response to the pull-down selection signal. The output driver is configured to drive output data in response to receiving a pre-pull-up signal and a pre-pull-down signal. | 05-05-2011 |
20130033949 | DATA CONTROL CIRCUIT - The data control circuit includes an input/output line and a driver. The input/output line precharging circuit precharges a global input/output line to a predetermined voltage when either a reading operation or a writing operation is inoperative. The driver includes a number of MOS transistors and drives the global input/output line in response to receiving data from a local input/output line and a complementary local input/output line during the reading operation. | 02-07-2013 |
Patent application number | Description | Published |
20090040845 | Column Path Circuit - A column path circuit includes address transition detectors which detect level transition of page address signals, thereby outputting transition detection signals each having a predetermined enable period, respectively. A detection signal coupler logically operates on the transition detection signals respectively outputted from the address transition detectors, and outputs a signal representing the results of the logical operation. A ready signal generator outputs a strobe ready signal having a predetermined enable period in response to an enabled state of the signal outputted from the detection signal coupler. A strobe signal generator generates a read strobe signal and a page address strobe signal for latch of the page address signals in response to the strobe ready signal. Page address buffers are enabled by the page address strobe signal, and latch the page address signals, thereby buffering the page address signals, a page address decoder which decodes the buffered page address signals respectively outputted from the page address buffers. And, a column selection signal generator outputs column selection signals respectively corresponding to the decoded page address signals in response to the read strobe signal. | 02-12-2009 |
20090323436 | Refresh signal generating circuit - A refresh signal generating circuit of a semiconductor memory device includes a flag signal generator which generates a flag signal in response to a refresh signal and a precharge signal, a clock enable signal buffer which generates first and second buffer enable signals based on an external clock enable signal in response to the flag signal, and a chip select signal buffer which generates an internal chip select signal based on an external chip select signal in response to the flag signal. | 12-31-2009 |
20110050290 | OUTPUT DRIVER CIRCUIT - An output driver circuit includes a pre-driver unit and a first driving unit. The pre-driver unit is configured to generate a driving selection signal and a driving signal from a pre-driving signal in response to a group selection signal and a code signal. The first driving unit is configured to drive a data pad in response to the driving selection signal and the driving signal. | 03-03-2011 |
20110116326 | Refresh Signal Generating Circuit - A refresh signal generating circuit of a semiconductor memory device includes a flag signal generator which generates a flag signal in response to a refresh signal and a precharge signal, a clock enable signal buffer which generates first and second buffer enable signals based on an external clock enable signal in response to the flag signal, and a chip select signal buffer which generates an internal chip select signal based on an external chip select signal in response to the flag signal. | 05-19-2011 |
20120014190 | Refresh Signal Generating Circuit - A refresh signal generating circuit of a semiconductor memory device includes a flag signal generator which generates a flag signal in response to a refresh signal and a precharge signal, a clock enable signal buffer which generates first and second buffer enable signals based on an external clock enable signal in response to the flag signal, and a chip select signal buffer which generates an internal chip select signal based on an external chip select signal in response to the flag signal. | 01-19-2012 |
20120113728 | DATA INPUT CIRCUIT - A data input circuit includes a clock sampling unit, a final clock generation unit, and a write latch signal generation unit. The sampling unit is configured to generate a shifting signal including a pulse generated after a write latency is elapsed, and generate a sampling clock by sampling an internal clock during a burst period from substantially a time when the pulse of the shifting signal is generated. The final clock generation unit is configured to generate a level signal by latching the shifting signal in synchronization with the sampling clock and generate a final clock from the level signal in response to a burst signal. The write latch signal generation unit is configured to generate an enable signal by latching the final clock and generate a write latch signal for latching and outputting aligned data in response to the enable signal. | 05-10-2012 |
20120218832 | DATA TRANSMISSION CIRCUIT - A data transmission circuit includes: a driving voltage generation unit configured to generate a driving voltage having a lower level than an external driving voltage; a switch unit configured to transmit the driving voltage when any one of a write enable signal and a read enable signal is enabled; and a data transmission unit configured to be driven by receiving the driving voltage, transmit a signal of a DQ pad as data in response to the write enable signal, and transmit the data to the DQ pad in response to the read enable signal. | 08-30-2012 |
20130147542 | FUSE CIRCUIT - A fuse circuit includes a programming fuse signal generation block configured to generate parity signals, logic levels of which are determined according to addresses selected among a plurality of addresses with a programming enable signal enabled, and generate programming fuse signals which are programmed in response to the programming enable signal, the plurality of addresses and the parity signals; a corrected pulse generation block configured to correct an error included in the programming fuse signals and generate corrected pulses; and a fuse unit configured to generate fuse signals which are reprogrammed according to the corrected pulses. | 06-13-2013 |
20140145764 | MULTI-PHASE CLOCK GENERATION CIRCUIT - A multi-phase clock generation circuit includes a first clock buffer unit configured to invert and buffer a first internal clock and a second internal clock in response to an external clock, and to generate a third internal clock and a fourth internal clock, and a second clock buffer unit configured to invert and buffer the third internal clock and the fourth internal clock in response to the external clock, and to generate the first internal clock and the second internal clock. | 05-29-2014 |
20140156213 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF TESTING OPEN FAILURES THEREOF - Semiconductor memory devices are provided. The semiconductor memory device includes an input/output (I/O) drive controller, a data I/O unit and a data transmitter. The data I/O unit selectively drives a first global I/O line and first/second global I/O lines according to the first or second test modes. The data transmitter selectively transfers the data on the first global I/O line onto first and second local I/O lines to store the data on the first global I/O line, and the data on the first and second global I/O lines onto the first and second local I/O lines according to the first or second test modes. | 06-05-2014 |
20140297986 | SEMICONDUCTOR MEMORY DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME - The semiconductor memory device includes an internal flag signal generator and an active information generator. The internal flag signal generator generates a plurality of internal flag signals which are selectively enabled when combination signals of bank address signals and row address signals supplied are inputted from an external device at least a predetermined number of times. The active information generator outputs a flag signal enabled when at least one of the plurality of internal flag signals is enabled in response to a start signal for extracting information on a number of times that a word line is activated and outputs a plurality of bank information signals according to the plurality of internal flag signals. The active information generator generates internal bank address signals and internal row address signals according to the plurality of internal flag signals to refresh a bank. | 10-02-2014 |
20150046723 | SENSE-AMPLIFIER DRIVING DEVICE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A sense-amplifier driving device includes: a power-supply driving unit configured to respectively provide a first pull-up voltage and a first pull-down voltage to a pull-up power line and a pull-down power line during a first over-driving time section, and provide the first pull-up voltage to the pull-up power line during a second over-driving time section; an over-driving controller configured to provide a second pull-down voltage lower than the first pull-down voltage to the pull-down power line during the second over-driving time section; and a drive-signal generator configured to generate a drive signal activated for the first and second over-driving time sections so as to control driving of the power-supply driving unit. | 02-12-2015 |
Patent application number | Description | Published |
20080291761 | Burn-in test apparatus - A burn-in test apparatus and a semiconductor device using the same are disclosed. The burn-in test apparatus includes a flag signal generating unit configured to receive an external input signal and an external address externally inputted for a burn-in test and generate a flag signal, and a burn-in test unit configured to receive the flag signal, generate a toggled output enable signal, and drive an input/output line to toggle a signal on the input/output line. | 11-27-2008 |
20090003122 | Address synchronous circuit capable of reducing current consumption in dram - An address synchronous circuit comprises an address control signal generating unit for generating a control signal in response to operation mode signals of a semiconductor memory and an internal clock signal, and an address synchronous unit for controlling output of an address which is buffered in accordance with a clock enable signal, in response to the control signal. | 01-01-2009 |
20090109783 | Refresh controlling circuit - A refresh controlling circuit includes an MRS latch unit configured to output a mask information signal of a bank and a mask information signal of a segment by synchronizing a first address signal and a second address signal with a pulse signal, a bank active control unit configured to output a bank active signal in response to the mask information signal of the bank, and a decoding unit configured to output a row address decoding signal in response to the bank active signal, the mask information signal of the segment, and a third address signal. | 04-30-2009 |
20090116326 | Semiconductor memory device capable of performing per-bank refresh - A semiconductor memory device is provided that can support a per-bank refresh as well as an all-bank refresh and a self refresh. The semiconductor memory device includes an address counting unit for counting a bank address signal of a specific bank and row address signals of the specific bank in response to a control signal including refresh mode information when a per-bank refresh command is lo received, and for counting row address signals in response to the control signal when an all-bank refresh command or a self refresh command is received. | 05-07-2009 |
20120013357 | Semiconductor Device - A semiconductor device comprises a burn-in test circuit configured to receive a flag signal for a burn-in test, generate a toggled output enable signal, and drive a first input/output line to toggle a signal on the first input/output line, and a switching device connected between a bit line and a second input/output line for transferring a signal on the bit line to the second input/output line in response to the output enable signal. | 01-19-2012 |