Patent application number | Description | Published |
20090028493 | Plasmon-enhanced electromagnetic-radiation-emitting devices and methods for fabricating the same - Various embodiments of the present invention are directed to surface-plasmon-enhanced electromagnetic-radiation-emitting devices and to methods of fabricating these devices. In one embodiment of the present invention, an electromagnetic-radiation-emitting device comprises a multilayer core, a metallic device layer, and a substrate. The multilayer core has an inner layer and an outer layer, wherein the outer layer is configured to surround at least a portion of the inner layer. The metallic device layer is configured to surround at least a portion of the outer layer. The substrate has a bottom conducting layer in electrical communication with the inner layer and a top conducting layer in electrical communication with the metallic device layer such that the exposed portion emits surface-plasmon-enhanced electromagnetic radiation when an appropriate voltage is applied between the bottom conducting layer and the top conducting layer. | 01-29-2009 |
20100187572 | SUSPENDED MONO-CRYSTALLINE STRUCTURE AND METHOD OF FABRICATION FROM A HETEROEPITAXIAL LAYER - Methods of fabricating a suspended mono-crystalline structure use annealing to induce surface migration and cause a surface transformation to produce the suspended mono-crystalline structure above a cavity from a heteroepitaxial layer provided on a crystalline substrate. The methods include forming a three dimensional (3-D) structure in the heteroepitaxial layer where the 3-D structure includes high aspect ratio elements. The 3-D structure is annealed at a temperature below a melting point of the heteroepitaxial layer. The suspended mono-crystalline structure may be a portion of a semiconductor-on-nothing (SON) substrate. | 07-29-2010 |
20110006284 | PHOTONIC STRUCTURE - A photonic structure includes a plurality of annealed, substantially smooth-surfaced ellipsoids arranged in a matrix. Additionally, a method of producing a photonic structure is provided. The method includes providing a semiconductor material, providing an etch mask comprising a two-dimensional hole array, and disposing the etch mask on at least one surface of the semiconductor material. The semiconductor material is then etched through the hole array of the etch mask to produce holes in the semiconductor material and thereafter applying a passivation layer to surfaces of the holes. Additionally, the method includes repeating the etching and passivation-layer application to produce a photonic crystal structure that contains ellipsoids within the semiconductor material and annealing the photonic crystal structure to smooth the surfaces of the ellipsoids. | 01-13-2011 |
20110012222 | METHOD OF MAKING LIGHT TRAPPING CRYSTALLINE STRUCTURES - A method of making a crystalline semiconductor structure provides a photonic device by employing low thermal budget annealing process. The method includes annealing a non-single crystal semiconductor film formed on a substrate to form a polycrystalline layer that includes a transition region adjacent to a surface of the film and a relatively thicker columnar region between the transition region and the substrate. The transition region includes small grains with random grain boundaries. The columnar region includes relatively larger columnar grains with substantially parallel grain boundaries that are substantially perpendicular to the substrate. The method further includes etching the surface to expose the columnar region having an irregular serrated surface. | 01-20-2011 |
20110182107 | MEMRISTIVE DEVICE - A memristive routing device ( | 07-28-2011 |
20110227022 | Memristor Having a Nanostructure Forming An Active Region - A memristor having an active region having a first electrode, a second electrode, and a nanostructure connecting the first electrode with the second electrode. The nanostructure includes a generally insulating material configured to have an electrically conductive channel formed in the material. The nanostructure forms the active region and has a length and a thickness, where the length is substantially equivalent to a distance extending from the first electrode to the second electrode along the nanostructure and the thickness is a distance across the nanostructure substantially perpendicular to the length of the nanostructure. The length of the nanostructure is substantially greater than the thickness of the nanostructure. | 09-22-2011 |
20110303890 | Electrically Actuated Device - An electrically actuated device includes a first electrode and a second electrode crossing the first electrode at a non-zero angle, thereby forming a junction therebetween. A material is established on the first electrode and at the junction. At least a portion of the material is a matrix region. A current conduction channel extends substantially vertically between the first and second electrodes, and is defined in at least a portion of the material positioned at the junction. The current conduction channel has a controlled profile of dopants therein. | 12-15-2011 |
20120025343 | THERMOELECTRIC DEVICE HAVING A VARIABLE CROSS-SECTION CONNECTING STRUCTURE - A thermoelectric device having a variable cross-section connecting structure includes a first electrode, a second electrode, and a connecting structure connecting the first electrode and the second electrode. The connecting structure has a first section and a second section. The width of the second section is greater than the width of the first section, and the width of the first section is less than a width that is approximately equivalent to a phonon mean free path through the first section. | 02-02-2012 |
20120032168 | PHOTONIC DEVICE AND METHOD OF MAKING THE SAME - A photonic device ( | 02-09-2012 |
20120112157 | NANOWIRE SENSOR WITH ANGLED SEGMENTS THAT ARE DIFFERENTLY FUNCTIONALIZED - A nanowire device includes a nanowire | 05-10-2012 |
20120281980 | OPTICAL SENSOR NETWORKS AND METHODS FOR FABRICATING THE SAME - Various embodiments of the present invention are directed to sensor networks and to methods for fabricating sensor networks. In one aspect, a sensor network includes a processing node ( | 11-08-2012 |
20130000688 | THERMOELECTRIC DEVICE - A thermoelectric device ( | 01-03-2013 |
20140097398 | MEMRISTIVE DEVICES AND MEMRISTORS WITH RIBBON-LIKE JUNCTIONS AND METHODS FOR FABRICATING THE SAME - Memristive devices, memristors and methods for fabricating memristive devices are disclosed. In one aspect, a memristor includes a first electrode wire and a second electrode wire. The second electrode wire and the first electrode wire define an overlap area. The memristor includes an electrode extension in contact with the first electrode wire and disposed between the first and second electrode wires. At least one junction is disposed between the second electrode wire and the electrode extension. Each junction contacts a portion of the electrode extension and has a junction contact area with the second electrode wire, and the sum total junction contact area of the at least one junction is less than the overlap area. | 04-10-2014 |
20140374693 | VARIED MULTILAYER MEMRISTIVE DEVICE - A varied multilayer memristive device includes a first memristive device stacked on a second memristive device. The physical parameters of the second memristive device differ from physical parameters of the first memristive to account for thermal budgeting differences present during formation processes for the memristive devices to reach specified performance parameters. | 12-25-2014 |
Patent application number | Description | Published |
20090310429 | SINGLE-ENDED DIFFERENTIAL SIGNAL AMPLIFICATION AND DATA READING - A method and system that can be used with signals read from a memory cell or other feature that varies in amplitude as a function of the data being read. The data read from the memory cell may be of the type that decreases in voltage when a ‘low’ is being read and that remains at a predetermined voltage when a ‘high’ is being read. The method and system may vary a reference to voltage used to judge whether the data is being read ‘low’ or ‘high’. | 12-17-2009 |
20100157706 | METHODS AND APPARATUSES FOR IMPROVING REDUCED POWER OPERATIONS IN EMBEDDED MEMORY ARRAYS - Methods and apparatuses are presented for improving reduced power operations in embedded memory arrays. Some embodiments may include a microprocessor, the microprocessor including at least one execution unit, a memory coupled to the execution unit, the memory including, a memory cell comprising a memory cell bus, a power circuit selectively coupling the memory cell bus to a first power plane and a second power plane, where the memory cell bus is coupled to the second power plane when the power circuit is substantially off, and a bit line pre-charge circuit coupled to the power circuit, where the power circuit selectively couples the first power plane to the pre-charge circuit for a predetermined period of time. | 06-24-2010 |
20100329063 | DYNAMICALLY CONTROLLED VOLTAGE REGULATOR FOR A MEMORY - A memory device that includes multiple blocks of static random access memory (SRAM), which each have a standby mode and an active operating mode, is described. During the active operating mode, a selection circuit couples a higher voltage from a first power-signal line and a power-supply circuit to a given block of SRAM, and during the standby mode the selection circuit couples a lower voltage from a second power-signal line to the given block of SRAM. Note that a regulator circuit regulates the lower voltage on the second power-signal line by selectively opening or closing a first switch between the first power-signal line and the second power-signal line. Furthermore, a recycling circuit selectively opens a second switch between the first switch and the first power-signal line when the block of SRAM transitions from the active operating mode to the standby mode, thereby transferring charge from the block of SRAM to other blocks of SRAM. | 12-30-2010 |
20130235680 | SEPARATE READ/WRITE COLUMN SELECT CONTROL - Systems and methods are described herein that reduce the read latency of a cache by separating read and write column select signals that cause the cache to initiate certain read and write operations, respectively. | 09-12-2013 |
20140082278 | High Speed Read Access Memory Array with Variation Tolerant Bypass Scheme with Protection Circuit - A memory array for process variation tolerant bypass operation. The memory array may utilize normal read operation data path of a memory I/O module. Accordingly, the speed at which the bypass operation may be executed may be increased. Furthermore, a potential for false read operations introduced by the utilization of the normal read operation data path of the memory I/O module may be reduced using a protect mechanism operable to block the output of false reads from the memory array. | 03-20-2014 |
20140136787 | SPECULATION TO SELECTIVELY ENABLE POWER IN A MEMORY - Systems, methods, and other embodiments associated with speculating whether a read request will cause an access to a memory are described. In one embodiment, a method includes detecting, in a memory, a read request from a processor and speculating whether the read request will cause an access to a memory bank in the memory based, at least in part, on an address identified by the read request. The method selectively enables power to the memory bank in the memory based, at least in part, on speculating whether the read request will cause an access to the memory bank. | 05-15-2014 |
20140146627 | SECONDARY BIT LINE EQUALIZER - Systems, methods, and other embodiments associated with bit line equalization are described. Systems and methods described herein provide secondary bit line equalization for embedded memory systems to reduce equalization time and improve memory performance. The reduction in equalization time is accomplished by adding a secondary equalizer in addition to a standard primary equalizer for a column of memory cells. | 05-29-2014 |
Patent application number | Description | Published |
20100002482 | MEMORY DEVICE AND METHOD - A content addressable memory includes a first plurality of search lines, a second plurality of search lines, a first match line, and a storage location. Each search line of the first plurality of search lines receives a corresponding high voltage level or low voltage level during a match detect operation, and each search line of the second plurality of search lines to receive a corresponding high voltage level or low voltage level during the match detect operation. The storage location of the content addressable memory includes a plurality of CAM cells, each CAM cell a first thyristor and second thyristor. | 01-07-2010 |
20100002502 | MEMORY DEVICE AND METHOD OF REFRESHING - A content addressable memory includes a first plurality of search lines, a second plurality of search lines, a first match line, and a storage location. Each search line of the first plurality of search lines receives a corresponding high voltage level or low voltage level during a match detect operation, and each search line of the second plurality of search lines to receive a corresponding high voltage level or low voltage level during the match detect operation. The storage location of the content addressable memory includes a plurality of CAM cells, each CAM cell a first thyristor and second thyristor. | 01-07-2010 |
20100146330 | MEMORY DEVICE AND METHOD THEREOF - An error correction module is disclosed whereby two bit cells are used to store a bit of information in a redundant manner so that a redundant error correction module can correct a sporadic data error at one of the two bits. | 06-10-2010 |
20100248454 | METHOD OF FORMING FIN STRUCTURES USING A SACRIFICIAL ETCH STOP LAYER ON BULK SEMICONDUCTOR MATERIAL - A method of manufacturing semiconductor fins for a semiconductor device may begin by providing a bulk semiconductor substrate. The method continues by growing a layer of first epitaxial semiconductor material on the bulk semiconductor substrate, and by growing a layer of second epitaxial semiconductor material on the layer of first epitaxial semiconductor material. The method then creates a fin pattern mask on the layer of second epitaxial semiconductor material. The fin pattern mask has features corresponding to a plurality of fins. Next, the method anisotropically etches the layer of second epitaxial semiconductor material, using the fin pattern mask as an etch mask, and using the layer of first epitaxial semiconductor material as an etch stop layer. This etching step results in a plurality of fins formed from the layer of second epitaxial semiconductor material. | 09-30-2010 |
20100295058 | TUNNELING FIELD EFFECT TRANSISTOR SWITCH DEVICE - A tunneling field effect transistor (TFET) device includes a semiconductor substrate having a layer of relatively intermediate bandgap semiconductor material, a layer of relatively low bandgap semiconductor material overlying the layer of relatively intermediate bandgap semiconductor material, and a layer of relatively high bandgap semiconductor material overlying the layer of relatively low bandgap semiconductor material. The TFET device includes a source region, a drain region, and a channel region defined in the semiconductor substrate. The TFET device also has a gate structure overlying at least a portion of the channel region. The source region is highly doped with an impurity dopant having a first conductivity type, and the drain region is highly doped with an impurity dopant having a second conductivity type. The layer of relatively low bandgap semiconductor material promotes tunneling at a first junction between the source region and the channel region, and the layer of relatively high bandgap semiconductor material inhibits tunneling at a second junction between the source region and the channel region. | 11-25-2010 |
20120292672 | FINFET INTEGRATED CIRCUITS AND METHODS FOR THEIR FABRICATION - FINFET ICs and methods for their fabrication are provided. In accordance with one embodiment a FINFET IC is fabricated by forming in a substrate a region doped with an impurity of a first doping type. The substrate region is etched to form a recess defining a fin having a height and sidewalls and the recess adjacent the fin is filled with an insulator having a thickness less than the height. Spacers are formed on the sidewalls and a portion of the insulator is etched to expose a portion of the sidewalls. The exposed portion of the sidewalls is doped with an impurity of the first doping type, the exposed sidewalls are oxidized, and the sidewall spacers are removed. A gate insulator and gate electrode are formed overlying the fin, and end portions of the fin are doped with an impurity of a second doping type to form source and drain regions. | 11-22-2012 |
20130043592 | Methods of Forming a Replacement Gate Comprised of Silicon and a Device Including Same - Disclosed herein are various methods of forming a replacement gate comprised of silicon and various semiconductor devices incorporation such a replacement gate structure. In one example, the method includes removing a sacrificial gate electrode structure to define a gate opening, forming a replacement gate structure in the gate opening, the replacement gate structure including at least one metal layer and a silicon-containing gate structure that is at least partially made of a metal silicide and forming a protective layer above at least a portion of the replacement gate structure. | 02-21-2013 |
20130045580 | METHODS FOR FABRICATING FINFET INTEGRATED CIRCUITS IN BULK SEMICONDUCTOR SUBSTRATES - Methods are provided for fabricating FinFETs that avoid thickness uniformity problems across a die or a substrate. One method includes providing a semiconductor substrate divided into a plurality of chips, each chip bounded by scribe lines. The substrate is etched to form a plurality of fins, each of the fins extending uniformly across the width of the chips. An oxide is deposited to fill between the fins and is etched to recess the top of the oxide below the top of the fins. An isolation hard mask is deposited and patterned overlying the plurality of fins and is used as an etch mask to etch trenches in the substrate defining a plurality of active areas, each of the plurality of active areas including at least a portion of at least one of the fins. The trenches are filled with an insulating material to isolate between adjacent active areas. | 02-21-2013 |
20130175583 | SEMICONDUCTOR DEVICES HAVING DIELECTRIC CAPS ON CONTACTS AND RELATED FABRICATION METHODS - Fabrication methods for semiconductor device structures are provided. One method for fabricating a semiconductor device structure involves forming a first layer of a first dielectric material overlying a doped region formed in a semiconductor substrate, forming a first conductive contact electrically connected to the doped region within the first layer, forming a dielectric cap on the first conductive contact, forming a second layer of a second dielectric material overlying the dielectric cap and a gate structure overlying the semiconductor substrate, and forming a second conductive contact electrically connected to the gate structure within the second layer. | 07-11-2013 |
20130181263 | Methods of Forming a Dielectric Cap Layer on a Metal Gate Structure - Disclosed herein are various methods of forming isolation structures on FinFETs and other semiconductor devices, and the resulting devices that have such isolation structures. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define a fin for a FinFET device, forming a layer of insulating material in the trenches, wherein the layer of insulating material covers a lower portion of the fin but not an upper portion of the fin, forming a protective material on the upper portion of the fin, and performing a heating process in an oxidizing ambient to form a thermal oxide region on the covered lower portion of the fin. | 07-18-2013 |
20130244387 | METHODS FOR FABRICATING INTEGRATED CIRCUITS - Methods are provided for forming semiconductor devices. One method includes forming a first layer overlying a bulk semiconductor substrate. A second layer is formed overlying the first layer. A plurality of trenches is etched into the first and second layers. Portions of the second layer that are disposed between the plurality of trenches define a plurality of fins. A gate structure is formed overlying the plurality of fins. The first layer is etched to form gap spaces between the bulk semiconductor substrate and the plurality of fins. The plurality of fins is at least partially supported in position adjacent to the gap spaces by the gate structure. The gap spaces are filled with an insulating material. | 09-19-2013 |
20130295756 | METHODS OF FORMING CONTACTS FOR SEMICONDUCTOR DEVICES USING A LOCAL INTERCONNECT PROCESSING SCHEME - One method disclosed herein includes forming a plurality of source/drain contacts that are conductively coupled to a source/drain region of a plurality of transistor devices, wherein at least one of the source/drain contacts is a local interconnect structure that spans the isolation region and is conductively coupled to a first source/drain region in a first active region and to a second source/drain region in a second active region, and forming a patterned mask layer that covers the first and second active regions and exposes at least a portion of the local interconnect structure positioned above an isolation region that separates the first and second active regions. The method further includes performing an etching process through the patterned mask layer to remove a portion of the local interconnect structure, thereby defining a recess positioned above a remaining portion of the local interconnect structure, and forming an insulating material in the recess. | 11-07-2013 |
20140264499 | SEMICONDUCTOR DEVICES HAVING DIELECTRIC CAPS ON CONTACTS AND RELATED FABRICATION METHODS - Semiconductor device structures are provided. An exemplary semiconductor device structure includes a substrate of a semiconductor material and a gate structure overlying the substrate. The semiconductor substrate further includes a doped region formed in the substrate proximate the gate structure and a first dielectric material overlying the doped region. The semiconductor substrate also includes a conductive contact formed in the first dielectric material, the conductive contact being electrically connected to the doped region, and a dielectric cap overlying the conductive contact. | 09-18-2014 |
20150041898 | BULK FINFET SEMICONDUCTOR-ON-NOTHING INTEGRATION - Methods and structures for forming fully insulated finFETs beginning with a bulk semiconductor substrate are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first epitaxial layer may be sacrificial. A final gate structure may be formed around the fin structures, and the first epitaxial layer removed to form a void between a fin and the substrate. The void may be filled with an insulator to fully insulate the fin. | 02-12-2015 |
20150076498 | TEST MACRO FOR USE WITH A MULTI-PATTERNING LITHOGRAPHY PROCESS - A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro having a first and second gate region during a first step of MPLP, and forming a first and second source/drain regions in the active area during a second step of the MPLP. The method also includes forming a first contact connected to the first gate region, a second contact connected to the second gate region, a third contact connected to the first source/drain region, and a forth contact connected to the source/drain region and determining if an overlay shift occurred between the first step and the second step of the step of the MPLP by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact. | 03-19-2015 |