Patent application number | Description | Published |
20120326298 | BUMP STRUCTURE WITH BARRIER LAYER ON POST-PASSIVATION INTERCONNECT - A semiconductor device includes a barrier layer between a solder bump and a post-passivation interconnect (PPI) layer. The barrier layer is formed of at least one of an electroless nickel (Ni) layer, an electroless palladium (Pd) layer or an immersion gold (Au) layer. | 12-27-2012 |
20140131861 | Plasma Treatment for Semiconductor Devices - A semiconductor device having a polymer layer and a method of fabricating the same is provided. A two-step plasma treatment for a surface of the polymer layer includes a first plasma process to roughen the surface of the polymer layer and loosen contaminants, and a second plasma process to make the polymer layer smoother or make the polymer layer less rough. An etch process may be used between the first plasma process and the second plasma process to remove the contaminants loosened by the first plasma process. In an embodiment, the polymer layer exhibits a surface roughness between about 1% and about 8% as measured by Atomic Force Microscopy (AFM) with the index of surface area difference percentage (SADP) and/or has surface contaminants of less than about 1% of Ti, less than about 1% of F, less than about 1.5% Sn, and less than about 0.4% of Pb. | 05-15-2014 |
20160049384 | BUFFER LAYER(S) ON A STACKED STRUCTURE HAVING A VIA - A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on a first side of the second semiconductor substrate. The first substrate is bonded to the second substrate at a bonding interface. A via extends at least through the second semiconductor substrate into the second interconnect structure. The first stress buffer layer is on a second side of the second semiconductor substrate opposite from the first side of the second semiconductor substrate. The PPI structure is on the first stress buffer layer and is electrically coupled to the via. The second stress buffer layer is on the PPI structure and the first stress buffer layer. | 02-18-2016 |
Patent application number | Description | Published |
20100035226 | COMPUTERIZED EDUCATION DEVICE, MULTIMEDIA PRODUCTION DEVICE AND ASSOCIATED METHODS TO SUPPORT DISTANCE LEARNING - A computerized education device, a multimedia production device and associated methods in accordance with the present invention provide students with an adaptive and proactive interaction learning environment. The computerized education device allows students to log in and take tests and comprises a computer-based learning platform, a content database, a student database and a processor. The multimedia production device has multiple-user and multiple-tasking capabilities to produce multimedia materials and comprises a managing server and multiple stations. A FLASH component conversion method generates a Flash component without expensive creation work and comprises acts of retrieving content, sampling, generating a small web format file, generating a data model and generating a FLASH quiz. The interacting method changes difficulty of content based on responses of students and comprises acts of qualifying, entertaining and compiling statistics. | 02-11-2010 |
20100062410 | COMPUTERIZED TESTING DEVICE WITH A NETWORK EDITING INTERFACE - The computerized testing device with a network editing interface in accordance with the present invention allows a teacher to generate customized quizzes or teaching materials for students logging into the computerized testing device to take tests through a network. The computerized testing device comprises an examination managing module, a content database, a testing module and a recording module. The network editing interface allows teachers to generate quizzes or teaching materials, and comprises a quiz database, a template database, a teacher database and a network editing interface. | 03-11-2010 |
20160054776 | METHOD FOR PERFORMING SYSTEM POWER CONTROL WITHIN AN ELECTRONIC DEVICE, AND ASSOCIATED APPARATUS - A method for performing system power control within an electronic device and an associated apparatus are provided. The method includes the steps of: utilizing a power consumption index generator positioned in a specific subsystem to generate a power consumption index corresponding to the specific subsystem, where the electronic device includes a plurality of subsystems, and the specific subsystem is one of the plurality of subsystems; and triggering a power limiter protection operation for the electronic device according to the power consumption index. For example, the power consumption index corresponding to the specific subsystem may represent a power consumption value of the specific subsystem, and the method may further include: comparing the power consumption value of the specific subsystem with a peak power threshold to determine whether the power consumed by the specific subsystem reaches the peak power threshold to generate a determining result, for triggering the power limiter protection operation. | 02-25-2016 |
20160062439 | METHOD FOR PERFORMING SYSTEM POWER BUDGETING WITHIN ELECTRONIC DEVICE, AND ASSOCIATED APPARATUS - A method for performing system power budgeting within an electronic device and an associated apparatus are provided. The method includes the steps of: utilizing a power consumption index generator positioned in a specific subsystem to generate a power consumption index corresponding to the specific subsystem, where the electronic device includes a plurality of subsystems, and the specific subsystem is one of the plurality of subsystems; and performing configuration adjustment on at least one portion of the electronic device according to the power consumption index corresponding to the specific subsystem. | 03-03-2016 |
Patent application number | Description | Published |
20120274411 | Pulse Width Modulation Driving IC and Pulse Width Modulation Output Signal Generating Method - The present invention discloses a pulse width modulation driving IC. The pulse width modulation driving IC includes a first pin, for receiving a first signal, a second pin, for receiving a second signal, a comparing unit, for comparing the first signal with a reference voltage, to generate a comparison result indicating a operating mode of the pulse width modulation driving IC, and an output unit, for outputting a pulse width modulation output signal according to the first signal, the second signal and the comparison result. | 11-01-2012 |
20120280642 | Start-up Circuit and Motor Driving IC - The present invention discloses a start-up circuit for a motor driving IC. The activation circuit includes a determination unit, for generating a determination result indicating an operating mode of the motor driving IC according to an external pulse width modulation signal, and an output unit, for outputting an activation signal according to the determination result and a pulse width modulation activation signal. A duty of the pulse width modulation activation signal is greater than a duty of the external pulse width modulation signal. | 11-08-2012 |
20140028232 | Motor Driving Circuit and Method - A motor driving circuit for driving a direct-current (DC) motor, includes a driving circuit for converting an input voltage into a first and a second output voltages, a Hall sensor for generating a first and a second time sequential control signals according to a working condition of the DC motor, a current sensing unit for detecting a motor current through the DC motor and comparing the motor current to a reference current to generate a comparison result and determine a first transition voltage selector value accordingly, and a control unit coupled to the driving circuit, the current sensing unit and the Hall sensor for controlling a working status of the driving circuit according to the first and the second time sequential control signals and the first transition voltage selector value. | 01-30-2014 |
20160087562 | Motor Driving Circuit and Method - A motor driving circuit for driving a direct-current (DC) motor, includes a driving circuit for converting an input voltage into a first and a second output voltages, a Hall sensor for generating a first and a second time sequential control signals according to a working condition of the DC motor, a current sensing unit for comparing the motor current to a reference current to generate a comparison result, and a control unit coupled to the driving circuit, the current sensing unit and the Hall sensor for controlling a working status of the driving circuit according to the first and the second time sequential control signals and the comparison result. | 03-24-2016 |
Patent application number | Description | Published |
20130270671 | Capacitor Array Layout Arrangement for High Matching Methodology - Some embodiments relate a capacitor array arranged on a semiconductor substrate. The capacitor array includes an array of unit capacitors arranged in a series of rows and columns. An interconnect structure couples unit capacitors of the array to establish a plurality of capacitor elements. The respective capacitor elements have different numbers of unit capacitors and different corresponding capacitances. In establishing the plurality of capacitor elements, the interconnect structure couples unit capacitors of the array in substantially identical sub-arrays tiled over the semiconductor substrate. Other methods and devices are also disclosed. | 10-17-2013 |
20140067348 | ARRAY MODELING FOR ONE OR MORE ANALOG DEVICES - Among other things, one or more techniques for creating an array model for analog device modeling are provided. In an embodiment, the array model represents a mean value or a standard deviation value of an analog device characteristic for an analog device based on a physical location of the analog device within a circuit layout, where the physical location is identified using a physical set of coordinates. The physical set of coordinates maps to an array set of coordinates of the array model. In this manner, a mean value and a standard deviation value are obtainable from the array model using the array set of coordinates. The mean value and the standard deviation value are usable to model the analog device, and thus a circuit within which the analog device is used, to obtain a more accurate or realistic prediction of operation or behavior, for example. | 03-06-2014 |
20150102861 | SHORT CURRENT-FREE EFFECTIVE CAPACITANCE TEST CIRCUIT AND METHOD - A method of determining an effective capacitance of a ring oscillator free of short current. The method comprises determining a frequency of an oscillator signal communicated from a ring oscillator to an inverter via a first communication path. The first communication path has connectivity to a first voltage source, a ground path and the inverter. The first communication path is divided into a second communication path and a third communication path. The method further comprises determining a voltage line current. The method additionally comprises determining an effective capacitance of the ring oscillator based on a first voltage of the first voltage source, the voltage line current and the frequency of the oscillator signal communicated to the inverter along the third communication path. | 04-16-2015 |
20150212128 | RISE TIME AND FALL TIME MEASUREMENT - Among other things, one or more systems and techniques for transition time evaluation of a circuit are provided herein. In some embodiments, a comparator is configured to receive a circuit signal from the circuit. The circuit signal is evaluated by the comparator based upon one or more control voltages to create one or more voltage waveforms. In some embodiments, the one or more voltage waveforms have substantially similar slopes. A time converter, such as a time-to-current converter or a time-to-digital converter, is used to evaluate the one or more output waveforms to determine a transition time, such as a rise time or a fall time, of the circuit. In some embodiments, the one or more output waveforms are used to reconstruct a transition waveform representing a waveform of the circuit signal. | 07-30-2015 |
20150268297 | CIRCUIT AND METHOD FOR MEASURING THE GAIN OF AN OPERATIONAL AMPLIFIER - A circuit for measuring the gain of an operational amplifier is provided. The circuit comprises a first operational amplifier, a first resistive device and a second resistive device. The first operational amplifier has an original gain and includes a first input terminal and a second input terminal. The first resistive device is coupled between the first input terminal and the second input terminal of the first operational amplifier. The second resistive device is coupled to the second input terminal of the first operational amplifier. The first resistive device and the second resistive device are configured to reduce a predetermined amount of gain from the original gain of the first operational amplifier. | 09-24-2015 |
Patent application number | Description | Published |
20090171286 | Safety syringe - A safety syringe includes a barrel which has a hollow passage inside and is coupled with a barrel cover. A push rod has a distal end coupled with a rubber ring to form a close contact with the hollow passage in a slidable manner. A driving module has an inner detent member, a piston seat and a piston rubber ring held in the barrel cover. The push rod is movable forwards to push the inner detent member and the piston rubber ring of the driving module forwards to make a cut surface at one end of the push rod to hit one end of a first stem of the needle mount to be broken and separated so that continuous moving forward of the push rod causes instant release of air pressure inside to retract the needle mount in a holding chamber of the push rod to safely hold a needle after injection. | 07-02-2009 |
20120040297 | APPARATUS FOR MIXING AND PROPORTIONING OIL AND WATER - An apparatus for mixing and proportioning oil and water comprises an upper lid, a first chunk member, a holder, a second chunk member and a base. The first chunk member and second chunk member have respectively an oil inlet, an oil-water mixture outlet and a water outlet that are connected with one another to receive and discharge oil and water. The first and second chunk members have respectively two oil flow gears and two water flow gears that engage with each other to control oil and water entering ratio to achieve optimal combustion efficiency. In the base, a located water regulation valve is adjusted to buffer water intake ratio responding to internal pressure alterations. The water regulation valve forms a buffer passage allowing different ratios of water to flow to the water in/out passage so that an improved oil-water mixture is achieved to enhance combustion efficiency of the combustion system. | 02-16-2012 |
20120103968 | OIL WATER MIXTURE HEATING APPARATUS - An oil water mixture heating apparatus comprises a metal outer barrel with a helical trough formed inside, a metal inner barrel held in the metal outer barrel to form a helical passage with the helical trough, a first and a second guide cap coupled on two sides of the metal outer and inner barrels, a first and a second seal cap coupled respectively on the first and second guide caps, a first and a second holder fixedly located on outer sides of the two seal caps and an electric heater encasing the metal outer barrel. When combustible oil or oil water mixture enters the helical passage and are heated by the electric heater, the oil or oil water mixture also is constantly blended in the helical passage so that it is heated rapidly to a required temperature and forms a finer oil water mixture. | 05-03-2012 |
Patent application number | Description | Published |
20110024823 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH INTRINSIC CHARGE TRAPPING LAYER - A non-volatile semiconductor memory device includes a substrate, a first gate formed on a first region of a surface of the substrate, a second gate formed on a second region of the surface of the substrate, a charge storage layer filled between the first gate and the second gate, a first diffusion region formed on a first side of the charge storage layer, and a second diffusion region formed opposite the charge storage layer from the first diffusion region. The first region and the second region are separated by a distance sufficient for forming a self-aligning charge storage layer therebetween. | 02-03-2011 |
20110242893 | NON-VOLATILE MEMORY UNIT CELL WITH IMPROVED SENSING MARGIN AND RELIABILITY - A non-volatile memory unit cell includes a first transistor pair and first and second control gates. The first transistor pair includes first and second transistors that are connected in series and of the same type. The first and second transistors have a first floating polysilicon gate and a second floating polysilicon gate, respectively. The first control gate is coupled to the first floating polysilicon gate through a tunneling junction and the second control gate is coupled to the second floating polysilicon gate through another tunneling junction. | 10-06-2011 |
20120018794 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH INTRINSIC CHARGE TRAPPING LAYER - A non-volatile semiconductor memory device includes a substrate, a first gate formed on a first region of a surface of the substrate, a second gate formed on a second region of the surface of the substrate, a charge storage layer filled between the first gate and the second gate, a first diffusion region formed on a first side of the charge storage layer, and a second diffusion region formed opposite the charge storage layer from the first diffusion region. The first region and the second region are separated by a distance sufficient for forming a self-aligning charge storage layer therebetween. | 01-26-2012 |
20120087170 | Single Polysilicon Non-Volatile Memory - A one-time-programmable memory device comprises a one-time-programmable memory cell array, a voltage pumping circuit, and a programming verification circuit. The one-time-programmable memory cell array comprises a plurality of memory cells. Each memory cell is arranged at an intersection of a bit line and a word line. The voltage pumping circuit comprises a plurality of local voltage boost circuits. Each local voltage boost circuit is shared by a corresponding memory cell of the plurality of memory cells. The programming verification circuit is coupled to the one-time-programmable memory cell array for verifying that conduction current of programmed memory cells of the plurality of memory cells is greater than a predetermined current level after programming. Each local boost circuit isolates leakage current of a corresponding programmed memory cell, and prevents programming voltage failure due to current overloading at a corresponding voltage pumping circuit. | 04-12-2012 |
20120134205 | OPERATING METHOD FOR MEMORY UNIT - An operating method for a memory unit is provided, wherein the memory unit includes a well region, a select gate, a first gate, a second gate, an oxide nitride spacer, a first diffusion region, and a second diffusion region. The operating method for the memory unit comprises the following steps. During a programming operation, a breakdown voltage is coupled to the second diffusion region through a first channel region formed under the select gate. A programming voltage is sequentially or simultaneously applied to the first gate and the second gate to rupture a first oxide layer and a second oxide layer, wherein the first oxide layer is disposed between the first gate and the well region, and the second oxide layer is disposed between the second gate and the well region. | 05-31-2012 |
20120273860 | NON-VOLATILE MEMORY UNIT CELL WITH IMPROVED SENSING MARGIN AND RELIABILITY - An only-one-polysilicon layer non-volatile memory unit cell includes a first P-type transistor, a second P-type transistor, a N-type transistor pair, a first and second coupling capacitors is provided. The N-type transistor pair has a third transistor and a fourth transistor that are connected. The third transistor and the fourth transistor have a first floating polysilicon gate and a second floating polysilicon gate to serve as charge storage mediums, respectively. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage. | 11-01-2012 |
20120314474 | NON-VOLATILE MEMORY CELL STRUCTURE AND METHOD FOR PROGRAMMING AND READING THE SAME - The present invention provides a non-volatile memory cell structure. A first isolation structure is disposed on a substrate and a semiconductor layer is disposed on the first isolation structure to form a silicon on insulator device. A first doping region is made of a portion of the semiconductor layer. A gate is disposed on the first doping region. A gate oxide layer is sandwiched between the first doping region and the gate. A second doping region is disposed within the semiconductor layer and outside the first doping region. A second doping region is in direct contact with the first doping region. A second isolation structure is disposed on the first isolation structure. Further, the second isolation structure surrounds the first doping region and the second doping region. The second isolation structure is also in direct contact with the first doping region and the second doping region. | 12-13-2012 |
20130010518 | ANTI-FUSE MEMORY ULTILIZING A COUPLING CHANNEL AND OPERATING METHOD THEREOF - An anti-fuse memory with coupling channel is provided. The anti-fuse memory includes a substrate of a first conductive type, a doped region of a second conductive type, a coupling gate, a gate dielectric layer, an anti-fuse gate, and an anti-fuse layer. The substrate has an isolation structure. The doped region is disposed in the substrate. A channel region is defined between the doped region and the isolation structure. The coupling gate is disposed on the substrate between the doped region and the isolation structure. The coupling gate is adjacent to the doped region. The gate dielectric layer is disposed between the coupling gate and the substrate. The anti-fuse gate is disposed on the substrate between the coupling gate and the isolation structure. The anti-fuse gate and the coupling gate have a space therebetween. The anti-fuse layer is disposed between the anti-fuse gate and the substrate. | 01-10-2013 |
20130105884 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH INTRINSIC CHARGE TRAPPING LAYER | 05-02-2013 |
20130119453 | NON-VOLATILE MEMORY UNIT CELL WITH IMPROVED SENSING MARGIN AND RELIABILITY - A non-volatile memory unit cell includes a transistor pair, and first, second, third and fourth control gates. The transistor pair has a first transistor and a second transistor that are connected in parallel and of opposite types. The first transistor and the second transistor have a first floating polysilicon gate and a second floating polysilicon gate, respectively, wherein the first floating polysilicon gate and the second floating polysilicon gate are electrically or physically isolated. The first control gate is capacitively coupled to the first floating polysilicon gate through a first coupling junction. The second control gate is capacitively coupled to the second floating polysilicon gates through a second coupling junction. The third control gate is capacitively coupled to the first floating polysilicon gate through a first tunneling junction. The fourth control gate is capacitively coupled to the second floating polysilicon gates through a second tunneling junction. | 05-16-2013 |
Patent application number | Description | Published |
20140085583 | DISPLAY PANEL - A display panel includes a pixel structure that has first, second, and third sub-pixels. In the first sub-pixel, a first pixel electrode having first branches and a second pixel electrode having second branches are alternately arranged. Gap dB is defined between adjacent first and second branches. In the second sub-pixel, a third pixel electrode having third branches and a fourth pixel electrode having fourth branches are alternately arranged. Gap dG is defined between adjacent third and fourth branches. In the third sub-pixel, a fifth pixel electrode having fifth branches and a sixth pixel electrode having sixth branches are alternately arranged. Gap dR is defined between adjacent fifth and sixth branches. The gaps dB, dG, and dR at least include minimum gaps dB | 03-27-2014 |
20140111716 | LIQUID CRYSTAL DISPLAY PANEL - A liquid crystal display panel having pixel regions includes a light shielding layer having opening regions corresponding to the pixel regions, first pixel electrodes and second pixel electrodes. Each first pixel electrode includes strip first pixel electrode patterns. Each second pixel electrode includes strip second pixel electrode patterns. Each opening region includes sub regions. Each of the strip first pixel electrode patterns and its neighboring strip second pixel electrode pattern in each of the sub regions are separated by an electrode spacing. Electrode spacings in different sub regions are different. An area of all the sub regions with the electrode spacings less than or equal to 12 micrometers accounts for less than or equal to 35% area of each opening region. An area of the other sub regions with the electrode spacings greater than 12 micrometers accounts for more than or equal to 65% area of each opening region. | 04-24-2014 |
20150021649 | PIXEL STRUCTURE - A pixel structure having a first region and a second region adjacent to each other is provided. The pixel structure includes a first pixel electrode and a second pixel electrode. The first pixel electrode forms a plurality of first V-shaped electrode patterns. A tip of the first V-shaped electrode patterns is located at a boundary of the first region and the second region. The second pixel electrode includes a plurality of second V-shaped electrode patterns and a first protrusion electrode pattern. The first protrusion electrode pattern is connected to one of the second V-shaped electrode patterns and protrudes towards an adjacent first V-shaped electrode pattern from the tip of the second V-shaped electrode pattern. | 01-22-2015 |
20150055069 | DISPLAY PANEL - A display panel includes a first substrate, plural pixel structures on the first substrate, a second substrate and a display medium between the two substrates. Each of the pixel structures includes a scan line, a data line, an active device, a pixel electrode, a common electrode, an insulating layer and a counter electrode. The active device is electrically connected to the scan line and the data line. The pixel electrode is electrically connected to the active device. The common electrode is electrically insulated from the pixel electrode. The insulating layer is between the pixel electrode and the common electrode. The counter electrode is electrically insulated from the pixel electrode and the common electrode, wherein the counter electrode is disposed symmetrically around the pixel electrode, and the voltage absolute value of the counter electrode is greater than the voltage absolute value of the pixel electrode. | 02-26-2015 |
20150070644 | PIXEL STRUCTURE - A pixel structure includes a scan line, a data line, an active device, a first electrode layer, a second electrode layer, and an insulation layer. The active device is electrically connected to the scan line and the data line. The first electrode layer is electrically connected to the active device. The second electrode layer is electrically insulated from the first electrode layer. The insulation layer is located between the first electrode layer and the second electrode layer, and the first electrode layer or the second electrode layer includes an enclosed-frame-shaped portion, first V-shaped branch portions, and second V-shaped branch portions. The first V-shaped branch portions and the second V-shaped branch portions are arranged within the enclosed-frame-shaped portion in opposite directions, and end terminals of the first V-shaped branch portions and end terminals of the second V-shaped branch portions are connected to the enclosed-frame-shaped portion. | 03-12-2015 |
Patent application number | Description | Published |
20120034864 | POWER DISTRIBUTION APPARATUS, POWER DISTRIBUTION METHOD, AND NON-INSTANT COMPUTER READABLE MEDIUM THEREOF - A power distribution apparatus (PDA), a power distribution method, and a non-instant computer readable medium thereof are provided. The PDA is used in a relay transmission system (RTS) comprising a mobile station (MS), a relay station (RS) and a base station (BS). The MS communicates with the BS through the RS. The PDA may communicate with the MS, BS and RS. The PDA computes optimum transmission parameters of the MS and BS and an optimum relay forward parameter of the RS according to a power threshold, transmission information of the RTS, an optimum condition and an algorithm. Accordingly, the MS, RS and BS may determine the optimum transmission power of the MS, RS and BS according to the optimum transmission parameters and the optimum relay forward parameter respectively. | 02-09-2012 |
20140105253 | TWO-WAY RELAY, WIRELESS APPARATUS AND SIGNAL PROCESSING METHOD THEREOF - A two-way relay, a wireless apparatus and a signal processing method thereof are provided. The two-way relay comprises a transceiver and a processor. The transceiver receives a relay receiving signal including a first terminal transmitting signal transmitted by a first wireless apparatus and a second terminal transmitting signal transmitted by a second wireless apparatus. The processor, which is electrically connected to the transceiver, uses a mapping function to transform the relay receiving signal into a relay signal and enables the transceiver to broadcast the relay signal. | 04-17-2014 |
Patent application number | Description | Published |
20130169411 | METHOD FOR OPERATING AN ELECTRONIC LOCK - A method for operating an electronic lock is disclosed. The electronic lock includes a processing unit, an inner body and an outer body. The inner body includes an inner input portion, and the outer body includes an input device. The method includes operating the inner input portion of the inner body to output various signals according to operation of the inner input portion, wherein the various signals comprises a first signal and utilizing the input device to log in a manage menu of the electronic lock when the processing unit receives the first signal, wherein the manage menu of the electronic lock comprises a first controlling item for setting a left-handed mode or a right-handed mode by the input device. | 07-04-2013 |
20140116102 | LOCK STRUCTURE - A lock structure includes a lock cylinder, a plug and a pin assembly, the plug is within an accommodating space of the lock cylinder. The plug comprises an outer lateral wall, a plurality of first lower pin holes and at least one second lower pin hole, each of the first lower pin holes comprises a first blocking edge, the second lower pin hole comprises a second blocking edge, wherein a second depth defined between the second blocking edge and the outer lateral wall is smaller than a first depth defined between the first blocking edge and the outer lateral wall. By height difference between the position of the first blocking edge and the position of the second blocking edge, an unmatched key can not contact with the second lower pin under instantaneous bump to prevent an unlock situation. Therefore, the burglar proof function is achieved. | 05-01-2014 |
20140197645 | HANDLE DEVICE AND LOCK IMPLEMENTING THE SAME - A handle device includes a pivoting portion and a handle body. The pivoting portion includes a surrounding wall formed along a longitudinal axis, and the surrounding wall has a top surface. The handle body comprises an extending portion which protrudes from the pivoting portion along a radial direction perpendicular to the longitudinal axis and is apart from the top surface of the surrounding wall by a gap. | 07-17-2014 |
20140250960 | REKEYABLE LOCK - A rekeyable lock includes a lock cylinder, a plug, a pin assembly and a stopper, the lock cylinder comprises a plug hole, a plurality of upper pin holes and a lower-pin-replacing hole, the plug is disposed at the plug hole, the pin assembly comprises a plurality of upper pins and a plurality of lower pins, the lower-pin-replacing hole selectively reveals the lower pins, the stopper is utilized for plugging into the lower-pin-replacing hole. When the stopper separates from the lower-pin-replacing hole, the lower-pin-replacing hole reveals the lower pins so as to replace the lower pins rapidly. When the stopper plugs into the lower-pin-replacing hole, the width of the stopper equals to that of the lower-pin-replacing hole. Otherwise, when the stopper separates from the lower-pin-replacing hole, the width of the stopper is larger than that of the lower-pin-replacing hole. | 09-11-2014 |
20140290317 | LOCK CYLINDER CAPABLE OF CHANGING A KEY MEMBER - A lock cylinder includes a cylinder housing with a upper pin hole set and a replacing opening, a cylinder body with a lower pin hole set, a upper locking pin set, a second locking pin set and a clip member. The cylinder body is movably disposed inside the cylinder housing. The upper locking pin set is disposed inside the upper pin hole set for engaging the cylinder housing and the cylinder body. The second locking pin set is disposed inside the lower pin hole set for disengaging the cylinder housing from the cylinder body. The clip member constrains the cylinder body from sliding on the cylinder housing in a first position, and does not constrains the cylinder body from sliding on the cylinder housing in a second position. The cylinder body slides to a replacing position for replacing the second locking pin set via the replacing opening. | 10-02-2014 |
20160040450 | HANDLE APPARATUS AND RETURN MECHANISM THEREIN - A handle apparatus comprises a case, a first positioning base, a second positioning base, a handle and a return mechanism. The return mechanism is engaged with the handle. The first positioning base and the second positioning base are disposed at the case. A positioning plate of the return mechanism optionally engages with the first positioning base or the second positioning base for making the handle apparatus optionally disposed at a left-hand swing door or a right-hand swing door. | 02-11-2016 |
20160047143 | METHOD FOR INSPECTING LOCK SET - A method for inspecting a lock set is to utilize a reception unit for receiving the signals from a lock set mounted at a door to inspect whether the door is closed and whether the lock set is locked or being broken. | 02-18-2016 |
20160053509 | HANDLE MECHANISM - A handle mechanism used for driving a lock module in operation includes a handle, a linking member and a transmission rod, wherein the linking member is selectively engaged with the handle and the transmission rod. The handle is unable to drive the lock module in operation by the transmission rod driving and prevents the lock module from damage once an excessive force is applied to the handle when the linking member is not engaged with the handle and the transmission rod. Oppositely, the handle is able to drive the lock module in operation by the transmission rod driving when the linking member is engaged with the handle and the transmission rod. | 02-25-2016 |
20160060905 | LOCK STRUCTURE - A lock structure includes a case, a first latch, a second latch, a transmission member, a transmission module, a swaying plate and a driving plate, wherein the transmission module is rotated to drive the swaying plate and the transmission member to perform swing action for making the swaying plate driving the first latch being hidden into the case. In addition, the driving plate moves upwardly by swing action of the transmission member, and the driving plate drives the second latch in operation for making the second latch being hidden into the case. | 03-03-2016 |
Patent application number | Description | Published |
20130001722 | Co-implant for Backside Illumination Sensor - A system and method for image sensing is disclosed. An embodiment comprises a substrate with a pixel region, the substrate having a front side and a backside. A co-implant process is performed along the backside of the substrate opposing a photosensitive element positioned along the front side of the substrate. The co-implant process utilizes a first pre-amorphization implant process that creates a pre-amorphization region. A dopant is then implanted wherein the pre-amorphization region retards or reduces the diffusion or tailing of the dopants into the photosensitive region. An anti-reflective layer, a color filter, and a microlens may also be formed over the co-implant region. | 01-03-2013 |
20130082342 | POLISHING PROCESS FOR ENHANCING IMAGE QUALITY OF BACKSIDE ILLUMINATED IMAGE SENSOR - The present disclosure provides an image sensor device and a method of forming the image sensor device. In an example, a method includes providing a substrate having a first surface and a second surface, the first surface being opposite the second surface; forming a light sensing region at the first surface of the substrate; forming a doped layer at the second surface of the substrate; and after forming the doped layer, polishing the second surface of the substrate. | 04-04-2013 |
20130084660 | PROCESS FOR ENHANCING IMAGE QUALITY OF BACKSIDE ILLUMINATED IMAGE SENSOR - A method of forming an image sensor device includes forming a light sensing region at a front surface of a silicon substrate and a patterned metal layer there over. Thereafter, the method also includes performing an ion implantation process to the back surface of the silicon substrate and performing a green laser annealing process to the implanted back surface of the silicon substrate. The green laser annealing process uses an annealing temperature greater than or equal to about 1100° C. for a duration of about 100 to about 400 nsec. After performing the green laser annealing process, a silicon polishing process is performed on the back surface of the silicon substrate. | 04-04-2013 |
20130134542 | DARK CURRENT REDUCTION FOR BACK SIDE ILLUMINATED IMAGE SENSOR - Provided is a semiconductor image sensor device that includes a non-scribe-line region and a scribe-line region. The image sensor device includes a first substrate portion disposed in the non-scribe-line region. The first substrate portion contains a doped radiation-sensing region. The image sensor device includes a second substrate portion disposed in the scribe-line region. The second substrate portion has the same material composition as the first substrate portion. Also provided is a method of fabricating an image sensor device. The method includes forming a plurality of radiation-sensing regions in a substrate. The radiation-sensing regions are formed in a non-scribe-line region of the image sensor device. The method includes forming an opening in a scribe-line region of the image sensor device by etching the substrate in the scribe-line region. A portion of the substrate remains in the scribe-line region after the etching. The method includes filling the opening with an organic material. | 05-30-2013 |
20130249037 | Co-implant for Backside Illumination Sensor - A system and method for image sensing is disclosed. An embodiment comprises a substrate with a pixel region, the substrate having a front side and a backside. A co-implant process is performed along the backside of the substrate opposing a photosensitive element positioned along the front side of the substrate. The co-implant process utilizes a first pre-amorphization implant process that creates a pre-amorphization region. A dopant is then implanted wherein the pre-amorphization region retards or reduces the diffusion or tailing of the dopants into the photosensitive region. An anti-reflective layer, a color filter, and a microlens may also be formed over the co-implant region. | 09-26-2013 |
20140357010 | Process For Enhancing Image Quality Of Backside Illuminated Image Sensor - A method includes providing a substrate having a first surface and a second surface, the first surface being opposite the second surface, forming a light sensing region at the first surface of the substrate, forming a doped layer at the second surface of the substrate using a laser annealing process, and performing a chemical mechanical polishing process on the annealed, doped layer. | 12-04-2014 |
20150349009 | DARK CURRENT REDUCTION FOR BACK SIDE ILLUMINATED IMAGE SENSOR - A method of fabricating a semiconductor image sensor device is disclosed. A plurality of radiation-sensing regions is formed in a substrate. The radiation-sensing regions are formed in a non-scribe-line region of the image sensor device. An opening is formed in a scribe-line region of the image sensor device by etching the substrate in the scribe-line region. A portion of the substrate remains in the scribe-line region after the etching. The opening is then filled with an organic material. | 12-03-2015 |
Patent application number | Description | Published |
20120202328 | METHOD FOR FABRICATING MOS TRANSISTOR - The invention discloses a method for fabricating a MOS transistor. A substrate having thereon a gate structure is provided. A silicon nitride layer is deposited on the gate structure. A dry etching process is then performed to define a silicon nitride spacer on each sidewall of the gate structure and a recess in a source/drain region on each side of the gate structure. A transitional layer covering the gate structure and the recess is deposited. A pre-epitaxial clean process is performed to remove the transitional layer. The substrate is subjected to a pre-bake process. An epitaxial growth process is performed to grow an embedded SiGe layer in the recess. The disposable silicon nitride spacer is removed. | 08-09-2012 |
20120264267 | METHOD FOR FABRICATING MOS TRANSISTOR - A method of fabricating a MOS transistor includes the steps of: providing a substrate; forming a gate structure on the substrate; forming a first spacer on the sidewall of the gate structure and forming at least a recess within the substrate next to the first spacer; performing an oxygen-containing process to form an oxygen-containing layer on the surface of the recess; performing a cleaning process to remove the oxygen-containing layer; performing an epitaxial process to form an epitaxial layer in the recess; and removing the first spacer. | 10-18-2012 |
20120270382 | METHOD OF FABRICATING AN EPITAXIAL LAYER - A method of fabricating an epitaxial layer includes providing a substrate. The substrate is etched to form at least a recess within the substrate. A surface treatment is performed on the recess to form a Si—OH containing surface. An in-situ epitaxial process is performed to form an epitaxial layer within the recess, wherein the epitaxial process is performed in a hydrogen-free atmosphere and at a temperature lower than 800° C. | 10-25-2012 |
20120292720 | METAL GATE STRUCTURE AND MANUFACTURING METHOD THEREOF - A metal gate structure includes a high dielectric constant (high-K) gate dielectric layer, a metal gate having at least a U-shaped work function metal layer positioned on the high-K gate dielectric layer, and a silicon carbonitride (SiCN) seal layer positioned on sidewalls of the high-K gate dielectric layer and of the metal gate. | 11-22-2012 |
20120309171 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a gate structure thereon; forming a film stack on the substrate and covering the gate structure, wherein the film stack comprises at least an oxide layer and a nitride layer; removing a portion of the film stack for forming recesses adjacent to two sides of the gate structure and a disposable spacer on the sidewall of the gate structure; and filling the recesses with a material comprising silicon atoms for forming a faceted material layer. | 12-06-2012 |
20120315734 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a gate structure thereon; forming an offset spacer on the sidewall of the gate structure; forming a cap layer to cover the substrate and the gate structure; performing an ion implantation process to implant carbon atoms into the cap layer; performing a first etching process to form a recess in the substrate adjacent to two sides of the gate structure; and forming an epitaxial layer in the recess. | 12-13-2012 |
20120326238 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region thereon; forming a high-k dielectric layer, a barrier layer, and a first metal layer on the substrate; removing the first metal layer of the second region; forming a polysilicon layer to cover the first metal layer of the first region and the barrier layer of the second region; patterning the polysilicon layer, the first metal layer, the barrier layer, and the high-k dielectric layer to form a first gate structure and a second gate structure in the first region and the second region; and forming a source/drain in the substrate adjacent to two sides of the first gate structure and the second gate structure. | 12-27-2012 |
20120329261 | MANUFACTURING METHOD FOR METAL GATE - A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function. | 12-27-2012 |
20130020657 | METAL OXIDE SEMICONDUCTOR TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A method for manufacturing a MOS transistor is provided. A substrate has a high-k dielectric layer and a barrier in each of a first opening and a second opening formed by removing a dummy gate and located in a first transistor region and a second transistor region. A dielectric barrier layer is formed on the substrate and filled into the first opening and the second opening to cover the barrier layers. A portion of the dielectric barrier in the first transistor region is removed. A first work function metal layer is formed. The first work function metal layer and a portion of the dielectric barrier layer in the second transistor region are removed. A second work function metal layer is formed. The method can avoid a loss of the high-k dielectric layer to maintain the reliability of a gate structure, thereby improving the performance of the MOS transistor. | 01-24-2013 |
20130072030 | METHOD FOR PROCESSING HIGH-K DIELECTRIC LAYER - A method for processing a high-k dielectric layer includes the following steps. A semiconductor substrate is provided, and a high-k dielectric layer is formed thereon. The high-k dielectric layer has a crystalline temperature. Subsequently, a first annealing process is performed, and a process temperature of the first annealing process is substantially smaller than the crystalline temperature. A second annealing process is performed, and a process temperature of the second annealing process is substantially larger than the crystalline temperature. | 03-21-2013 |
20130280878 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A gate structure is formed on a substrate. An oxide layer is formed and covers the gate structure and the substrate. A plasma process without oxygen is performed to densify the oxide layer. A material layer is formed and covers the oxide layer. The material layer and the oxide layer are etched to form a dual spacer. | 10-24-2013 |
20140035070 | METAL OXIDE SEMICONDUCTOR TRANSISTOR - A MOS transistor including a silicon substrate, a first gate structure and a second gate structure disposed on the silicon substrate is provided. The first gate structure and the second gate structure each includes a high-k dielectric layer disposed on the silicon substrate, a barrier layer disposed on the high-k dielectric layer, and a work function layer disposed on and contacted with the barrier layer. The MOS transistor further includes a dielectric material spacer. The dielectric material spacer is disposed on the barrier layer of each of the first gate structure and the second gate structure and surrounding the work function layer of each of the first gate structure and the second gate structure. | 02-06-2014 |
20140162431 | METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE - A method for manufacturing a semiconductor structure includes the following steps. First, a semiconductor substrate is provided and a patterned pad layer is formed on the semiconductor substrate so as to expose a portion of the semiconductor substrate. Then, the semiconductor substrate exposed from the patterned pad layer is etched away to form a trench inside the semiconductor substrate. A selectively-grown material layer is selectively formed on the surface of the trench, followed by filling a dielectric precursor material into the trench. Finally, a transformation process is carried out to concurrently transform the dielectric precursor material into a dielectric material and transform the selectively-grown material layer into an oxygen-containing amorphous material layer. | 06-12-2014 |
20140199854 | METHOD OF FORMING FILM ON DIFFERENT SURFACES - A method of forming a film is provided. The method includes at least the following steps. A first substrate and a second substrate are provided in a batch processing system, wherein a first surface of the first substrate is adjacent to a second surface of the second substrate, the first surface of the first substrate has a first surface condition, the second surface of the second substrate has a second surface condition, and the first surface condition is different from the second surface condition. A pretreatment gas is provided to the surfaces of the substrates for transforming the first surface condition and the second surface condition to a third surface condition. A reaction gas is provided to form the film on the surfaces, having the third surface condition, of the substrates. | 07-17-2014 |
20140295629 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device is disclosed. At least one gate structure is provided on a substrate, wherein the gate structure includes a first spacer formed on a sidewall of a gate. A first disposable spacer material layer is deposited on the substrate covering the gate structure. The first disposable spacer material layer is etched to form a first disposable spacer on the first spacer. A second disposable spacer material layer is deposited on the substrate covering the gate structure. The second disposable spacer material layer is etched to form a second disposable spacer on the first disposable spacer. A portion of the substrate is removed, by using the first and second disposable spacers as a mask, so as to form two recesses in the substrate beside the gate structure. A stress-inducing layer is formed in the recesses. | 10-02-2014 |
20150140780 | METHOD FOR FABRICATING SHALLOW TRENCH ISOLATION STRUCTURE - A method for fabricating shallow trench isolation structure is disclosed. The method includes the steps of: (a) providing a substrate; (b) forming a trench in the substrate; (c) forming a silicon layer in the trench; and (d) performing an oxidation process to partially transform a surface of the silicon layer into an oxide layer. | 05-21-2015 |
Patent application number | Description | Published |
20130168794 | Seamless Multi-Poly Structure and Methods of Making Same - A sensor array is integrated onto the same chip as core logic. The sensor array uses a first polysilicon and the core logic uses a second polysilicon. The first polysilicon is etched to provide a tapered profile edge in the interface between the sensor array and the core logic regions to avoid an excessive step. Amorphous carbon can be deposited over the interface region without formation of voids, thus providing for improved manufacturing yield and reliability. | 07-04-2013 |
20130323876 | IMAGE DEVICE AND METHODS OF FORMING THE SAME - A method of forming of an image sensor device includes a patterned hardmask layer is formed over a substrate. The patterned hard mask layer has a plurality of first openings in a periphery region, and a plurality of second openings in a pixel region. A first patterned mask layer is formed over the pixel region to expose the periphery region. A plurality of first trenches is etched into the substrate in the periphery region. Each first trench, each first opening and each second opening are filled with a dielectric material. A second patterned mask layer is formed over the periphery region to expose the pixel region. The dielectric material in each second opening over the pixel region is removed. A plurality of dopants is implanted through each second opening to form various doped isolation features in the pixel region. | 12-05-2013 |
20130323917 | SELF-ALIGNED PATTERNING FOR DEEP IMPLANTATION IN A SEMICONDUCTOR STRUCTURE - Methods of forming self-aligned patterns for performing oppositely doped deep implantations in a semiconductor substrate are disclosed. The semiconductor substrate has implantation and non-implantation regions. The methods include forming a hardmask pattern for a first implantation with a first conductivity-type dopant, depositing an etch stop layer, filling trenches between the hardmask pattern with a sacrificial filler material having a higher wet etch resistance than the hardmask, removing a top portion of the sacrificial filler material and the etch stop layer over a top surface of the hardmask pattern, removing the hardmask pattern in the implantation region by wet etching, and performing a second ion implantation with a second conductivity type dopant opposite of the first conductivity type. | 12-05-2013 |
20150255503 | Image Device and Methods of Forming the Same - A method of forming of an image sensor device includes a patterned hardmask layer is formed over a substrate. The patterned hard mask layer has a plurality of first openings in a periphery region, and a plurality of second openings in a pixel region. A first patterned mask layer is formed over the pixel region to expose the periphery region. A plurality of first trenches is etched into the substrate in the periphery region. Each first trench, each first opening and each second opening are filled with a dielectric material. A second patterned mask layer is formed over the periphery region to expose the pixel region. The dielectric material in each second opening over the pixel region is removed. A plurality of dopants is implanted through each second opening to form various doped isolation features in the pixel region. | 09-10-2015 |
Patent application number | Description | Published |
20120295437 | METHOD FOR FABRICATING THROUGH-SILICON VIA STRUCTURE - A method for fabricating through-silicon via structure is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a through-silicon via in the semiconductor substrate; covering a liner in the through-silicon via; performing a baking process on the liner; forming a barrier layer on the liner; and forming a through-silicon via electrode in the through-silicon via. | 11-22-2012 |
20120305403 | Electrical Chemical Plating Process - An electrical chemical plating process is provided. A semiconductor structure is provided in an electrical plating platform. A pre-electrical-plating step is performed wherein the pre-electrical-plating step is carried out under a fixed voltage environment and lasts for 0.2 to 0.5 seconds after the current is above the threshold current of the electrical plating platform. After the pre-electrical-plating step, a first electrical plating step is performed on the semiconductor structure. | 12-06-2012 |
20130023098 | MANUFACTURING METHOD FOR METAL GATE - A manufacturing method for a metal gate includes providing a substrate having a dielectric layer and a polysilicon layer formed thereon, the polysilicon layer, forming a protecting layer on the polysilicon layer, forming a patterned hard mask on the protecting layer, performing a first etching process to etch the protecting layer and the polysilicon layer to form a dummy gate having a first height on the substrate, forming a multilayered dielectric structure covering the patterned hard mask and the dummy gate, removing the dummy gate to form a gate trench on the substrate, and forming a metal gate having a second height in the gate trench. The second height of the metal gate is substantially equal to the first height of the dummy gate. | 01-24-2013 |
20130045595 | METHOD FOR PROCESSING METAL LAYER - The method for processing a metal layer including the following steps is illustrated. First, a semiconductor substrate is provided. Then, a metal layer is formed over the semiconductor substrate. Furthermore, a microwave energy is used to selectively heat the metal layer without affecting the underlying semiconductor substrate and other formed structures, in which the microwave energy has a predetermined frequency in accordance with a material of the metal layer, and the predetermined frequency ranges between 1 KHz to 1 MHz. | 02-21-2013 |