Patent application number | Description | Published |
20100258733 | COMPOSITE DIELECTRIC FINS IN ENHANCED AREA BORON COATED NEUTRON DETECTORS - A neutron detector that includes a hollow member extending along and circumscribing an axis. The hollow member has an interior surface and bounds a volume. The detector also includes an anode extending within the volume. The detector also includes a cathode that includes at least one fin extending within the volume. The fin has a substrate material with at least one surface. At least part of the interior surface of the hollow member and the surface of the at least one fin have neutron sensitive material thereon. | 10-14-2010 |
20100258736 | NEUTRON SENSITIVITY BY INCREASING BORON SURFACE AREA - A neutron detector including an anode and a cathode. The cathode extends proximate the anode and has a face including boron. The face has varied topography. The varied provides increased surface density. | 10-14-2010 |
20100258737 | HIGH SENSITIVITY B-10 NEUTRON DETECTORS USING HIGH SURFACE AREA INSERTS - A neutron detector that includes an anode and a cathode. The cathode includes at least one portion that has a porous substrate with surface segments that define open pores and a layer of neutron sensitive material on the surface segments of the porous substrate. | 10-14-2010 |
20110116589 | WATER BASED DISPERSIONS OF BORON OR BORON COMPOUNDS FOR USE IN COATING BORON LINED NEUTRON DETECTORS - A method for providing a boron-lined neutron detector. The method includes providing a boron-containing material and providing water. The method includes mixing the boron-containing material into the water to create a water-based liquid mixture and providing a substrate of a cathode of the neutron detector. The method includes applying the water-based liquid mixture to the substrate of the cathode and removing water from the water-based liquid applied to the substrate to leave a boron-containing layer upon the substrate that is sensitive to neutron impingement. The step of providing a boron-containing material may be to provide the material to include B-10. | 05-19-2011 |
20120325942 | JET MILLING OF BORON POWDER USING INERT GASES TO MEET PURITY REQUIREMENTS - A processing system and associated method for milling boron with impurity contamination avoidance. The system includes a jet mill for reducing the particle size of a boron feed stock, and a feed stock inlet for delivering the boron feed stock toward the jet mill. The system includes at least one inlet for delivering at least one gas into the jet mill. The gas and the boron feed stock comingle within the jet mill during milling reduction of boron particle size. The system includes a source of the at least one gas operatively connected to the at least one inlet, with the at least one gas being a gas that avoids transferring impurity during milling reduction of boron particle size. | 12-27-2012 |
20130052114 | METHOD FOR REMOVING CONTAMINANTS FROM BORON POWDER - Methods for removing an organic contaminant from contaminated boron powder are provided. One method includes providing a contaminated boron powder, the boron powder being comingled with an organic contaminant. The method also includes placing the contaminated boron powder and the organic contaminant comingled therewith onto an inert container. The method includes placing the inert container, the contaminated boron powder, and the organic contaminant comingled therewith, into an enclosed space. A heat source is provided in the enclosed space. The method also includes heating the contaminated boron powder and the organic contaminant comingled therewith to an elevated temperature. The method includes altering the organic contaminant so as to reduce the amount of the organic contaminant comingled with the boron powder. Another method includes reducing the amount of the organic contaminant comingled with the boron powder to not more than about 0.1 weight percent of soluble residue. | 02-28-2013 |
20130062531 | BORON CONTAINING COATING FOR NEUTRON DETECTION - A neutron detector includes an exterior shell bounding an interior volume. The neutron detector includes at least a wall portion serving as a cathode. In one example the wall portion has microfeatures. The neutron detector includes a central structure located within the interior volume and serving as an anode. The neutron detector includes a boron coating on the wall portion. In on example, the boron coating is applied by an electrostatic spray process. In one example, the boron coating conforms to the microfeatures on the wall portion. In one example, the wall portion has a thickness of between 2 to 5 microns. The neutron detector includes an electrical connector operatively connected to the central structure for transmission of a signal collected by the central structure. An associated method provides for depositing the boron coating. | 03-14-2013 |
20130101488 | OPTIMIZED BORON POWDER FOR NEUTRON DETECTION APPLICATIONS - An optimized boron powder is provided. The quantity of a soluble residue comingled with the optimized boron powder is less than 7.00×10 | 04-25-2013 |
20130189633 | METHOD FOR REMOVING ORGANIC CONTAMINANTS FROM BORON CONTAINING POWDERS BY HIGH TEMPERATURE PROCESSING - Methods for removing an organic contaminant from contaminated boron powder include providing a contaminated boron powder, the boron powder being comingled with an organic contaminant. The method also includes placing the contaminated boron powder onto an inert container and placing the inert container and the contaminated boron powder into an enclosed space. The enclosed space environment is altered to create an oxygen deficient atmosphere. A heat source is provided to heat the contaminated boron powder to an elevated temperature. The method includes vaporizing the organic contaminant so as to reduce the amount of the organic contaminant comingled with the boron powder. Another method includes reducing the amount of the organic contaminant comingled with the boron powder to not more than about 0.1 weight percent of soluble residue. | 07-25-2013 |
20140138462 | JET MILLING OF BORON POWDER USING INERT GASES TO MEET PURITY REQUIREMENTS - A processing system and associated method for milling boron with impurity contamination avoidance. The system includes a jet mill for reducing the particle size of a boron feed stock, and a feed stock inlet for delivering the boron feed stock toward the jet mill. The system includes at least one inlet for delivering at least one gas into the jet mill. The gas and the boron feed stock comingle within the jet mill during milling reduction of boron particle size. The system includes a source of the at least one gas operatively connected to the at least one inlet, with the at least one gas being a gas that avoids transferring impurity during milling reduction of boron particle size. | 05-22-2014 |
Patent application number | Description | Published |
20120068315 | METHOD OF IMPROVING MECHANICAL PROPERTIES OF SEMICONDUCTOR INTERCONNECTS WITH NANOPARTICLES - In a BEOL process, UV radiation is used in a curing process of ultra low-k (ULK) dielectrics. This radiation penetrates through the ULK material and reaches the cap film underneath it. The interaction between the UV light and the film leads to a change the properties of the cap film. Of particular concern is the change in the stress state of the cap from compressive to tensile stress. This leads to a weaker dielectric-cap interface and mechanical failure of the ULK film. A layer of nanoparticles is inserted between the cap and the ULK film. The nanoparticles absorb the UV light before it can damage the cap film, thus maintaining the mechanical integrity of the ULK dielectric. | 03-22-2012 |
20120146224 | Semiconductor having interconnects with improved mechanical properties by insertion of nanoparticles - In a BEOL process, UV radiation is used in a curing process of ultra low-k (ULK) dielectrics. This radiation penetrates through the ULK material and reaches the cap film underneath it. The interaction between the UV light and the film leads to a change the properties of the cap film. Of particular concern is the change in the stress state of the cap from compressive to tensile stress. This leads to a weaker dielectric-cap interface and mechanical failure of the ULK film. A layer of nanoparticles is inserted between the cap and the ULK film. The nanoparticles absorb the UV light before it can damage the cap film, thus maintaining the mechanical integrity of the ULK dielectric. | 06-14-2012 |
20120249159 | Stacked Via Structure For Metal Fuse Applications - A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region. | 10-04-2012 |
20120326269 | E-FUSE STRUCTURES AND METHODS OF MANUFACTURE - E-fuse structures in back end of the line (BEOL) interconnects and methods of manufacture are provided. The method includes forming an interconnect via in a substrate in alignment with a first underlying metal wire and forming an e-fuse via in the substrate, exposing a second underlying metal wire. The method further includes forming a defect with the second underlying metal wire and filling the interconnect via with metal and in contact with the first underlying metal wire thereby forming an interconnect structure. The method further includes filling the e-fuse via with the metal and in contact with the defect and the second underlying metal wire thereby forming an e-fuse structure. | 12-27-2012 |
20130127584 | Redundant Via Structure For Metal Fuse Applications - A metal fuse structure using redundant vias. The redundant vias are formed on one metal level in a stacked via metal fuse structure to force failures to occur in the metal level that does not have the redundant vias. The metal fuse structure includes: a first dielectric layer having a metal feature; a second dielectric layer having a first metal connector embedded therein; and a third dielectric layer having a second metal connector embedded therein. The metal connectors include at least one via and one line, and at least one metal connector has at least two vias. | 05-23-2013 |
20130176073 | BACK-END ELECTRICALLY PROGRAMMABLE FUSE - A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current. | 07-11-2013 |
20130214894 | METAL FUSE STRUCTURE FOR IMPROVED PROGRAMMING CAPABILITY - Structure providing more reliable fuse blow location, and method of making the same. A vertical metal fuse blow structure has, prior to fuse blow, an intentionally damaged portion of the fuse conductor. The damaged portion helps the fuse blow in a known location, thereby decreasing the resistance variability in post-blow circuits. At the same time, prior to fuse blow, the fuse structure is able to operate normally. The damaged portion of the fuse conductor is made by forming an opening in a cap layer above a portion of the fuse conductor, and etching the fuse conductor. Preferably, the opening is aligned such that the damaged portion is on the top corner of the fuse conductor. A cavity can be formed in the insulator adjacent to the damaged fuse conductor. The damaged fuse structure having a cavity can be easily incorporated in a process of making integrated circuits having air gaps. | 08-22-2013 |
20130307151 | METHOD TO RESOLVE HOLLOW METAL DEFECTS IN INTERCONNECTS - A method of repairing hollow metal void defects in interconnects and resulting structures. After polishing interconnects, hollow metal void defects become visible. The locations of the defects are largely predictable. A repair method patterns a mask material to have openings over the interconnects (and, sometimes, the adjacent dielectric layer) where defects are likely to appear. A local metal cap is formed in the mask openings to repair the defect. A dielectric cap covers the local metal cap and any recesses formed in the adjacent dielectric layer. | 11-21-2013 |
20140028325 | STACKED VIA STRUCTURE FOR METAL FUSE APPLICATIONS - A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region. | 01-30-2014 |
20140070362 | E-FUSE STRUCTURES AND METHODS OF MANUFACTURE - E-fuse structures in back end of the line (BEOL) interconnects and methods of manufacture are provided. The method includes forming an interconnect via in a substrate in alignment with a first underlying metal wire and forming an e-fuse via in the substrate, exposing a second underlying metal wire. The method further includes forming a defect with the second underlying metal wire and filling the interconnect via with metal and in contact with the first underlying metal wire thereby forming an interconnect structure. The method further includes filling the e-fuse via with the metal and in contact with the defect and the second underlying metal wire thereby forming an e-fuse structure. | 03-13-2014 |
20140118020 | STRUCTURES AND METHODS FOR DETERMINING TDDB RELIABILITY AT REDUCED SPACINGS USING THE STRUCTURES - A structure for TDDB measurement, a method determining TDDB at reduced spacings. The structure includes an upper dielectric layer on a top surface of a lower dielectric layer, a bottom surface of the upper dielectric layer and the top surface of the lower dielectric layer defining an interface; a first wire formed in the lower dielectric layer; a second wire formed in the upper dielectric layer; and wherein a distance between the first wire and the second wire measured in a direction parallel to the interface is below the lithographic resolution limit of the fabrication technology. | 05-01-2014 |
20140167268 | GRAPHENE AND METAL INTERCONNECTS - A graphene and metal interconnect structure and methods of making the same are disclosed. The graphene is a multiple layer graphene structure that is grown using a graphene catalyst. The graphene forms an electrical connection between two or more VIAs or components, or a combination of VIAs and components. A VIA includes a fill metal, with at least a portion of the fill metal being surrounded by a barrier metal. A component may be a routing track, a clock signal source, a power source, an electromagnetic signal source, a ground terminal, a transistor, a macrocell, or a combination thereof. The graphene is grown, using a graphene catalyst, from both solid and liquid carbon sources using chemical vapor deposition (CVD) at a temperature between 300° C.-400° C. The graphene catalyst can be an elemental form of, or alloy including, nickel, palladium, ruthenium, iridium or copper. | 06-19-2014 |
20140167772 | STACKED VIA STRUCTURE FOR METAL FUSE APPLICATIONS - A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region. | 06-19-2014 |
20140183688 | MODIFIED VIA BOTTOM FOR BEOL VIA EFUSE - An electronic fuse structure including an M | 07-03-2014 |
20140203435 | SELECTIVE LOCAL METAL CAP LAYER FORMATION FOR IMPROVED ELECTROMIGRATION BEHAVIOR - A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines. | 07-24-2014 |
20140217612 | ELECTRONIC FUSE HAVING A DAMAGED REGION - An electronic fuse structure including an M | 08-07-2014 |
20140252538 | ELECTRONIC FUSE WITH RESISTIVE HEATER - A method of forming an electronic fuse including forming an M | 09-11-2014 |
20140319685 | Hybrid Graphene-Metal Interconnect Structures - Hybrid metal-graphene interconnect structures and methods of forming the same. The structure may include a first end metal, a second end metal, a conductive line including one or more graphene portions extending from the first end metal to the second end metal, and one or more line barrier layers partially surrounding each of the one or more graphene portions. The conductive line may further include one or more intermediate metals separating each of the one or more graphene portions. Methods of forming said interconnect structures may include forming a plurality of metals including a first end metal and a second end metal in a dielectric layer, forming one or more line trenches between each of the plurality of metals, forming a line barrier layer in each of the one or more line trenches, and filling the one or more line trenches with graphene. | 10-30-2014 |
20140332924 | E-FUSE WITH HYBRID METALLIZATION - A structure including a first interconnect including a first line overlying a first via and a second interconnect including a second line overlying a second via. The first line and the second line are co-planar. The first interconnect comprises a first conductor, the first conductor comprises a metal silicide including titanium silicide, cobalt silicide, nickel silicide, tungsten silicide, platinum silicide, molybdenum silicide, tantalum silicide, or some combination thereof. The second interconnect comprises a second conductor, the second conductor comprising copper. | 11-13-2014 |
20140332965 | High Performance Refractory Metal / Copper Interconnects To Eliminate Electromigration - An interconnect structure and method of making the same. A preferred interconnect structure has a first interconnect including a first dual damascene via and narrow line and a second interconnect at the same level as the first including a second dual damascene via and wider line. The first and second interconnects may have different aspect ratio and may have different line heights while being co-planar with each other. The second line of the second interconnect may abut or partially surround the first line of the first interconnect. The first interconnect includes a refractory metal material as the main conductor, whereas the second interconnect includes a lower resistivity material as its main conductor. | 11-13-2014 |
20140346674 | GRAPHENE-METAL E-FUSE - A structure including an M | 11-27-2014 |
20150035115 | MODIFIED VIA BOTTOM FOR BEOL VIA EFUSE - An electronic fuse structure including an M | 02-05-2015 |
20150130018 | VIA-FUSE WITH LOW DIELECTRIC CONSTANT - In an embodiment of the present invention, a semiconductor device comprises a non-fuse area that has a non-fuse via, a non-fuse line, and a non-fuse dielectric stack. The semiconductor device further comprises a fuse area that has a fuse via, a fuse line, and a fuse dielectric stack. The fuse dielectric stack comprises at least a first dielectric and a second dielectric material. The fuse via is at least partially embedded in the first dielectric material and the fuse line is embedded in the second dielectric material. | 05-14-2015 |
20150137377 | GRAPHENE AND METAL INTERCONNECTS WITH REDUCED CONTACT RESISTANCE - A structure including a first metal line in a first interconnect level, the first metal line comprising one or more graphene portions, a second metal line in a second interconnect level above the first interconnect level, the second metal line comprising one or more graphene portions, and a metal via comprising a palladium liner extends vertically and electrically connects the first metal line with the second metal line, the via is at least partially embedded in the first metal line such that the palladium liner is in direct contact with at least an end portion of the one or more graphene portions of the first metal line. | 05-21-2015 |
20150228578 | ELECTRONIC FUSE WITH RESISTIVE HEATER - An electronic fuse structure including an M | 08-13-2015 |
20150235946 | REDUNDANT VIA STRUCTURE FOR METAL FUSE APPLICATIONS - A metal fuse structure using redundant vias. The redundant vias are formed on one metal level in a stacked via metal fuse structure to force failures to occur in the metal level that does not have the redundant vias. The metal fuse structure includes: a first dielectric layer having a metal feature; a second dielectric layer having a first metal connector embedded therein; and a third dielectric layer having a second metal connector embedded therein. The metal connectors include at least one via and one line, and at least one metal connector has at least two vias. | 08-20-2015 |
20150255342 | SELECTIVE LOCAL METAL CAP LAYER FORMATION FOR IMPROVED ELECTROMIGRATION BEHAVIOR - A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines. | 09-10-2015 |
20150255343 | SELECTIVE LOCAL METAL CAP LAYER FORMATION FOR IMPROVED ELECTROMIGRATION BEHAVIOR - A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines. | 09-10-2015 |
20150255398 | SELECTIVE LOCAL METAL CAP LAYER FORMATION FOR IMPROVED ELECTROMIGRATION BEHAVIOR - A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines. | 09-10-2015 |
20160027733 | BACK-END ELECTRICALLY PROGRAMMABLE FUSE - A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current. | 01-28-2016 |
Patent application number | Description | Published |
20090093114 | METHOD OF FORMING A DUAL-DAMASCENE STRUCTURE USING AN UNDERLAYER - A method of forming a dual-damascene wire. The method includes forming a via opening in a dielectric layer, filling the via opening with a polymeric formation including at least about 6% by weight of solids of thermal acid generator; heating the polymeric underlayer to a temperature greater than room temperature but less than about 180° C.; lithographically forming a trench in the dielectric layer and filling the via opening and the trench with an electrical conductor, a top surface of the electrical conductor substantially co-planer with the top surface of the second dielectric capping layer. | 04-09-2009 |
20100213522 | METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE TO REMEDY BOX UNDERCUT AND STRUCTURE FORMED THEREBY - A method of forming a silicon-on-insulator (SOI) semiconductor structure in a substrate having a bulk semiconductor layer, a buried oxide (BOX) layer and an SOI layer. During the formation of a trench in the structure, the BOX layer is undercut. The method includes forming a dielectric material on the upper wall of the trench adjacent to the undercutting of the BOX layer and then etching the dielectric material to form a spacer. The spacer fixes the BOX layer undercut and protects it during subsequent steps of forming a bottle-shaped portion of the trench, forming a buried plate in the deep trench; and then forming a trench capacitor. There is also a semiconductor structure, preferably an SOI eDRAM structure, having a spacer which fixes the undercutting in the BOX layer. | 08-26-2010 |
20130234284 | Fuse and Integrated Conductor - A fuse structure includes within an aperture within a dielectric layer located over a substrate that exposes a conductor contact layer within the substrate a seed layer interposed between the conductor contact layer and another conductor layer. The seed layer includes a doped copper material that includes a dopant immobilized predominantly within the seed layer. The fuse structure may be severed while not severing a conductor interconnect structure also located over the substrate that exposes a second conductor contact layer within a second aperture. In contrast with the fuse structure that includes the doped seed layer having the immobilized dopant, the interconnect structure includes a doped seed layer having a mobile dopant. | 09-12-2013 |
20140070363 | ELECTRONIC ANTI-FUSE - An electronic anti-fuse structure, the structure including an M | 03-13-2014 |
20140077334 | Electronic Fuse Vias in Interconnect Structures - An electronic fuse and method for forming the same. Embodiments of the invention include e-fuses having a first metallization level including a metal structure, a second metallization level above the first metallization level, a metal via in the second metallization level, an interface region where the metal via meets the first metallization level, and a damaged region at the interface region. Embodiments further include a method including providing a first metallization level including a metal structure, forming a capping layer on the first metallization level, forming an opening in the capping layer that exposes a portion of the metal structure; forming above the capping layer an adhesion layer contacting the metal structure, forming an insulating layer above the adhesion layer, etching the insulating layer and the adhesion layer to form a recess exposing the metal structure, and filling the fuse via recess to form a fuse via. | 03-20-2014 |
20150041951 | ELECTRONIC FUSE VIAS IN INTERCONNECT STRUCTURES - An electronic fuse and method for forming the same. Embodiments of the invention include e-fuses having a first metallization level including a metal structure, a second metallization level above the first metallization level, a metal via in the second metallization level, an interface region where the metal via meets the first metallization level, and a damaged region at the interface region. Embodiments further include a method including providing a first metallization level including a metal structure, forming a capping layer on the first metallization level, forming an opening in the capping layer that exposes a portion of the metal structure; forming above the capping layer an adhesion layer contacting the metal structure, forming an insulating layer above the adhesion layer, etching the insulating layer and the adhesion layer to form a recess exposing the metal structure, and filling the fuse via recess to form a fuse via. | 02-12-2015 |