Patent application number | Description | Published |
20080208857 | PROCESSING, BROWSING AND EXTRACTING INFORMATION FROM AN ELECTRONIC DOCUMENT - The present invention relates to methods, apparatus and systems for processing an electronic document and its corresponding device. It provides methods for browsing an electronic document and its corresponding browser, and methods for extracting information segments from an electronic document and its corresponding system for the same. An example of a method for processing an electronic document comprises extracting one or more information segments of the domains to which the electronic document relates from the electronic document being written by an author, and correspondingly storing said extracted information segments with said document. Wherein one or more information extraction patterns are used to extract information segments of different domains to which the electronic document relates from said document. And the extracted information segments are verified by the writer so as to ensure its correctness, reliability and readability. | 08-28-2008 |
20080222138 | Method and Apparatus for Constructing a Link Structure Between Documents - A method and computer system for constructing a link structure for T documents. An initial link structure G | 09-11-2008 |
20080288535 | Method, Apparatus and System for Linking Documents - A method, apparatus and system for linking documents, the method comprising the steps of: providing a plurality of clusters in an enterprise intranet, each cluster consists of one or more documents; building a cluster page for each cluster to present the documents in the cluster; and building links between the cluster pages, between the documents, and between the cluster page and the document, based on analysis of the contents of the clusters and the documents. The present invention is useful for building the links between separate documents and may apply a link analyzing algorithm to the search for these documents to implement better search performance within the enterprise intranet. | 11-20-2008 |
20090024610 | COMPUTER AIDED AUTHORING, ELECTRONIC DOCUMENT BROWSING, RETRIEVING, AND SUBSCRIBING AND PUBLISHING - Provides methods, apparatus, and systems for computer aided authoring. Included are: a method for browsing an electronic document, an apparatus for aided authoring, an electronic document browser, a method for retrieving an electronic document, a system for retrieving electronic documents, a method for subscribing and publishing an electronic document as well as a system for subscribing and publishing electronic documents. An example method for computer aided authoring includes: generating one or more topic summaries based on an electronic document while a writer is writing said electronic document, wherein the reliability of the topic summary is ensured by the writer; and saving said topic summary information in correspondence with said electronic document. | 01-22-2009 |
20090307217 | Method, Device and System for Processing, Browsing and Searching an Electronic Documents - A method for processing electronic document and its corresponding device, a method for browsing electronic document and its corresponding browser, as well as a method for searching electronic document and its corresponding searching system are disclosed in the present invention. The method comprises at least the following steps of: generating one or more query according to the content of said document when an author is composing the electronic document; and correspondingly storing information about said one or more query with said electronic document. Wherein the query comprises keywords, keyword string or questions, and the query has passed the verification in order to ensure its reliability. | 12-10-2009 |
Patent application number | Description | Published |
20090208223 | FOUR WAVE MIXING SUPPRESSION - Methods, systems and computer program products for countering the effects of four wave mixing are described. In one implementation, a controller can be used to shift an operating wavelength of an optical transmitter away from a zero-dispersion wavelength through which signals of the optical transmitter are transmitted. The controller can perform the shifting process while allowing sufficient margin for division multiplexing and minimal dispersion. The controller may determine an appropriate offset to be used for shifting the operating wavelength without subjecting the signals to a significant increase in undesirable effects such as dispersion, crosstalk and signal distortion which can impact the overall bit-error rate. | 08-20-2009 |
20090290880 | Dispersion Compensation Circuitry and System for Analog Video Transmission With Direct Modulated Laser - An improved precompensation circuit includes a greatly improved differentiator in the dispersion precompensation path, a preprocessor in the dispersion precompensation path for reducing f2−f1 type Composite Second Order (CSO) distortion, and a broadband phase shifter for compensating undesired vector interaction between the laser predistortion and dispersion compensation. | 11-26-2009 |
20110210777 | DISPERSION COMPENSATION CIRCUITRY AND SYSTEM FOR ANALOG VIDEO TRANSMISSION WITH DIRECT MODULATED LASER - An improved precompensation circuit includes a greatly improved differentiator in the dispersion precompensation path, a preprocessor in the dispersion precompensation path for reducing f2−f1 type Composite Second Order (CSO) distortion, and a broadband phase shifter for compensating undesired vector interaction between the laser predistortion and dispersion compensation. | 09-01-2011 |
20120027421 | Four Wave Mixing Suppression - Methods, systems and computer program products for countering the effects of four wave mixing are described. In one implementation, a controller can be used to shift an operating wavelength of an optical transmitter away from a zero-dispersion wavelength through which signals of the optical transmitter are transmitted. The controller can perform the shifting process while allowing sufficient margin for division multiplexing and minimal dispersion. The controller may determine an appropriate offset to be used for shifting the operating wavelength without subjecting the signals to a significant increase in undesirable effects such as dispersion, crosstalk and signal distortion which can impact the overall bit-error rate. | 02-02-2012 |
Patent application number | Description | Published |
20140285346 | POWER SUPPLY DETECTING CIRCUIT FOR VENDING MACHINE - A power supply detecting circuit for detecting a power supply status of a controlling system of a vending machine, includes a port equipped on the controlling system, a power supply unit, an alarming unit, and a switch unit. The port outputs a high level voltage signal when a normal power is supplied to the controlling system. The power supply unit provides power to the alarming unit. The switch unit is connected between the alarming unit and ground. The switch unit is controlled by the port. The switch unit is turned off to switch off the alarming unit when the high level voltage signal is outputted from the port. The switch unit is turned on to switch on the alarming unit when the normal power is not supplied to controlling system and the high level voltage signal is not outputted from the port. | 09-25-2014 |
20150206420 | ALARM SYSTEM - An alarm system includes a wireless signal generating module configured to be mounted in an electronic device, a wireless signal receiving module, a processing module coupled to the wireless signal receiving module, a drive circuit coupled to the processing module, and an alarm device coupled to the drive circuit. The wireless signal generating module communicates with the wireless signal receiving module wirelessly when within a communication range of the wireless signal receiving module. The wireless signal generating module does not communicate with the wireless signal receiving module wirelessly when out of the communication range with the wireless signal receiving module, thereby the processing module sends a connection signal to the drive circuit. The drive circuit drives the alarm device to give an alarm when receiving the connection signal. | 07-23-2015 |
20150249303 | CONNECTOR - An electrical connector includes a plug and a socket coupled to the plug. The plug includes a base body and at least one first pin and a second pin. The at least one first pin and the second pin are attached to the base body. The socket defines at least one first hole and a second hole. A size of the first hole corresponds to the first pin and is configured to receive the first pin. A size of the second hole corresponds to that of the second pin and is configured to receive the second pin. A size of the second pin is greater than that of the first hole to prevent any wrong connections. | 09-03-2015 |
Patent application number | Description | Published |
20080237746 | Gated diode with non-planar source region - A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and a drain. The top of the source or drain region, or both, are formed so as to be at a higher elevation, in whole or in part, than the bottom of the gate structure. This configuration may be achieved by overlaying the gate structure and substrate with a profile layer that guides a subsequent etch process to create a sloped profile. The source and drain, if both are present, may be symmetrical or asymmetrical. This configuration significantly reduces dopant encroachment and, as a consequence, reduces junction leakage. | 10-02-2008 |
20080242039 | METHOD OF ENHANCING DOPANT ACTIVATION WITHOUT SUFFERING ADDITIONAL DOPANT DIFFUSION - A method of enhancing dopant activation without suffering additional dopant diffusion, includes forming shallow and lightly-doped source/drain extension regions in a semiconductor substrate, performing a first anneal process on the source/drain extension regions, forming deep and heavily-doped source/drain regions in the substrate adjacent to the source/drain extension regions, and performing a second anneal process on source/drain regions. The first anneal process is a flash anneal process performed for a time of between about 1 millisecond and 3 milliseconds, and the second anneal process is a rapid thermal anneal process performed for a time of between about 1 second and 30 seconds. | 10-02-2008 |
20110147765 | DUMMY STRUCTURE FOR ISOLATING DEVICES IN INTEGRATED CIRCUITS - The present disclosure provides an integrated circuit. The integrated circuit includes a first operational device having a first transistor of a first composition; a second operational device having a second transistor of the first composition; and an isolation transistor disposed between the first and second transistors, the isolation transistor having a second composition different from the first composition. | 06-23-2011 |
20120091540 | STRAINED STRUCTURE OF A P-TYPE FIELD EFFECT TRANSISTOR - In a p-type field effect transistor, a pair of spacers are formed over the top surface of a substrate. A channel recess cavity includes an indentation in the substrate top surface between the pair of spacers. A gate stack has a bottom portion in the channel recess cavity and a top portion extending outside the channel recess cavity. A source/drain (S/D) recess cavity has a bottom surface and sidewalls below the substrate top surface. The S/D recess cavity has a portion extending below the gate stack. A strained material is filled the S/D recess cavity | 04-19-2012 |
20120100686 | METHOD OF FORMING ULTRA-SHALLOW JUNCTIONS IN SEMICONDUCTOR DEVICES - A method of forming ultra-shallow lightly doped source/drain (LDD) regions of a CMOS transistor in a surface of a substrate includes the steps of providing a semiconductor substrate, providing a gate stack on the semiconductor substrate, performing a low temperature pocket implantation process on the substrate, performing a low temperature co-implanted ion implantation process on the substrate, and/or performing a low temperature lightly doped source/drain implantation process on the substrate. | 04-26-2012 |
20120319203 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed device comprises a gate structure over a substrate and defining a channel region in the substrate, an epitaxial feature with a first dopant in the substrate, and an epitaxial source/drain feature with a second dopant in the substrate. The epitaxial source/drain feature is farther from the channel region than the epitaxial feature is. The second dopant has an electrical carrier type opposite to the first dopant. | 12-20-2012 |
20130099314 | Semiconductor Device With Multiple Stress Structures And Method Of Forming The Same - A method of fabricating and a semiconductor device with multiple dislocation structures is disclosed. The exemplary semiconductor device includes gate structure overlying a top surface of a semiconductor substrate and a first gate spacer disposed on a sidewall of the gate structure and overlying the top surface of the substrate. The semiconductor device further includes a crystallized semiconductor material overlying the top surface of the semiconductor substrate and adjacent to a sidewall of the first gate spacer. The semiconductor device further includes a second gate spacer disposed on the sidewall of the first gate spacer and overlying the crystallized semiconductor material. The semiconductor device further includes a first stressor region disposed in the semiconductor substrate and a second stressor region disposed in the semiconductor substrate and in the crystallized semiconductor material. | 04-25-2013 |
20130187221 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A method of forming a semiconductor device includes performing a first pre-amorphous implantation process on a substrate, where the substrate has a gate stack. The method further includes forming a first stress film over the substrate. The method also includes performing a first annealing process on the substrate and the first stress film. The method further includes performing a second pre-amorphous implantation process on the annealed substrate, forming a second stress film over the substrate, and performing a second annealing process on the substrate and the second stress film. | 07-25-2013 |
20130280875 | METHOD OF MANUFACTURING STRAINED SOURCE/DRAIN STRUCTURES - A method includes forming a gate structure over a semiconductor substrate. The gate structure defines a channel region in the semiconductor substrate. Trenches are formed in the semiconductor substrate, and the trenches are interposed by the channel region. A first semiconductor layer is epitaxially grown in the trenches, and the first semiconductor layer has a first dopant with a first dopant concentration. A second semiconductor layer is epitaxially grown over the first semiconductor layer, and the second semiconductor layer has a second dopant with a second dopant concentration. The second dopant has an electrical carrier type opposite to an electrical carrier type of the first dopant. | 10-24-2013 |
20140346614 | SEMICONDUCTOR DEVICE - A semiconductor device includes a gate structure over a substrate, a source region in the substrate, where the source region is adjacent to the gate structure. Additionally, the semiconductor device includes a drain region in the substrate, where the drain region is adjacent to the gate structure. Moreover, the semiconductor device includes a first dislocation in the substrate between the source region and the drain region. Furthermore, the semiconductor device includes a second dislocation in the substrate between the source region and the drain region, where the second dislocation is substantially parallel to the first dislocation. | 11-27-2014 |
Patent application number | Description | Published |
20100210086 | Junction Profile Engineering Using Staged Thermal Annealing - An annealing method includes performing an activation annealing on a wafer with a peak temperature of greater than about 1200° C., wherein the activation annealing has a first duration; and performing a defect-recovery annealing on the wafer at a defect-recovery temperature lower than the peak temperature for a second duration. The second duration is longer than the first duration. The annealing method includes no additional annealing steps at temperatures greater than about 1200° C., and no room-temperature cooling step exists between the activation annealing and the defect-recovery annealing. | 08-19-2010 |
20100237441 | Gated Diode with Non-Planar Source Region - A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and a drain. The top of the source or drain region, or both, are formed so as to be at a higher elevation, in whole or in part, than the bottom of the gate structure. This configuration may be achieved by overlaying the gate structure and substrate with a profile layer that guides a subsequent etch process to create a sloped profile. The source and drain, if both are present, may be symmetrical or asymmetrical. This configuration significantly reduces dopant encroachment and, as a consequence, reduces junction leakage. | 09-23-2010 |
20130099294 | MOSFETs with Multiple Dislocation Planes - A method includes forming a metal-oxide-semiconductor field-effect transistor (MOSFET), which includes forming a first dislocation plane adjacent to a gate electrode of the MOSFET, and forming a second dislocation plane adjacent to the gate electrode of the MOSFET. The first and the second dislocation planes are on a same side of the gate electrode, and extend into source/drain regions of the MOSFET. | 04-25-2013 |
Patent application number | Description | Published |
20080247932 | Method for making colloidal nanocrystals - A method for making colloidal nanocrystals includes the following steps: dissolving a nanocrystal powder in an organic solvent, and achieving a solution A of a concentration of 1-30 mg/ml; dissolving a surfactant in water, and achieving a solution B of a concentration of 0.002-0.05 mmol/ml; mixing the solution A and the solution B in a volume ratio of 1: (5-30), and achieving a mixture; stirring and emulsifying the mixture, until an emulsion C is achieved; removing the organic solvent from the emulsion C, and achieving a deposit; then washing the deposit with deionized water, and achieving colloidal nanocrystals. The present method for making colloidal nanocrystals is economical and timesaving, and has a low toxicity associated therewith. Thus, the method is suitable for industrial mass production. The colloidal nanocrystals made by the present method have a readily controllable size, a narrow size distribution, and good configuration. | 10-09-2008 |
20100278721 | Method for making mesoporous material - A method for making the mesoporous material includes the following steps: dissolving a nanocrystal powder in an organic solvent, and achieving a solution A with concentration of 1-30 mg/ml; dissolving a surfactant in water, and achieving a solution B with an approximate concentration of 0.002-0.05 mol/ml; mixing the solution A and the solution B in a volume ratio of 1: (5-30), and achieving a mixture; stirring and emulsifying the mixture, until an emulsion C is achieved; removing the organic solvent from the emulsion C, and achieving a deposit; washing the deposit with deionized water, and achieving a colloid; and drying and calcining the colloid, and eventually achieving a mesoporous material. The mesoporous material has a large specific surface area, a high porosity, and a narrow diameter distribution. | 11-04-2010 |