Patent application number | Description | Published |
20140110823 | CONTACT STRUCTURE - One or more techniques or systems for forming a contact structure for a deep trench capacitor (DTC) are provided herein. In some embodiments, a contact structure includes a substrate region, a first region, a second region, contact landings, a first trench region, a first landing region, and a second trench region. In some embodiments, a first region is over the substrate region and a second region is over the first region. For example, the first region and the second region are in the first trench region or the second trench region. Additionally, a contact landing over the first trench region, the second trench region, or the first landing region is in contact with the first region, the second region, or the substrate region. In this manner, additional contacts are provided and landing area is reduced, thus reducing resistance of the DTC, for example. | 04-24-2014 |
20140239350 | SEMICONDUCTOR DEVICE CONTAINING HEMT AND MISFET AND METHOD OF FORMING THE SAME - A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer. | 08-28-2014 |
20140252534 | METHOD OF MAKING DEEP TRENCH, AND DEVICES FORMED BY THE METHOD - A method for forming a semiconductor device includes providing a semiconductor-on-insulator (SOI) structure, and forming at least one hard mask (HM) layer over the SOI structure. The SOI structure includes an insulator layer and a semiconductor layer over the insulator layer. The method further comprises forming a trench inside the at least one HM layer and the semiconductor layer, and depositing a spacer layer in the trench. The spacer layer comprises a bottom surface portion over the bottom surface of the trench, and a side wall portion along the side wall of the trench. The method further comprises etching the bottom surface portion of the spacer layer while the side wall portion of the spacer layer remains, and etching the insulator layer to extend the trench into the insulator layer. | 09-11-2014 |
20150044008 | Robot Blade Design - The present disclosure relates to a wafer transfer robot having a robot blade that can be used to handle substrates that are patterned on both sides without causing warpage of the substrates. In some embodiments, the wafer transfer robot has a robot blade coupled to a transfer arm that varies a position of the robot blade. The robot blade has a wafer reception area that receives a substrate. Two or more spatially distinct contact points are located at positions along a perimeter of the wafer reception area that provide support to opposing edges of the substrate. The two or more contact points are separated by a cavity in the robot blade. The cavity mitigates contact between a backside of the substrate and the robot blade, while providing support to opposing sides of the substrate to prevent warpage of the substrate. | 02-12-2015 |
20150069539 | Cup-Like Getter Scheme - The present disclosure relates to a method of gettering that provides for a high efficiency gettering process by increasing an area in which a getter layer is deposited, and an associated apparatus. In some embodiments, the method is performed by providing a substrate into a processing chamber having one or more residual gases. A cavity is formed within a top surface of the substrate. The cavity has a bottom surface and sidewalls extending from the bottom surface to the top surface. A getter layer, which absorbs the one or more residual gases, is deposited over the substrate at a position extending from the bottom surface of the cavity to a location on the sidewalls. By depositing the getter layer to extend to a location on the sidewalls of the cavity, the area of the substrate that is able to absorb the one or more residual gases is increased. | 03-12-2015 |
20150069574 | INTEGRATED CIRCUIT AND MANUFACTURING AND METHOD THEREOF - A novel integrated circuit and method thereof are provided. The integrated circuit includes a plurality of first interconnect pads, a plurality of second interconnect pads, a first inter-level dielectric layer, a thin film resistor, and at least two end-caps. The end-caps, which are connectors for the thin film resistor, are positioned at the same level with the plurality of second interconnect pads. Therefore, an electrical connection between the end-caps and the plurality of second interconnect pads can be formed by directly connection of them. An integrated circuit with a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above. | 03-12-2015 |
20150069581 | NOBLE GAS BOMBARDMENT TO REDUCE SCALLOPS IN BOSCH ETCHING - A method of etching a trench in a substrate is provided. The method repeatedly alternates between using a fluorine-based plasma to etch a trench, which has trench sidewalls, into a selected region of the substrate; and using a fluorocarbon plasma to deposit a liner on the trench sidewalls. The liner, when formed and subsequently etched, has an exposed sidewall surface that includes scalloped recesses. The trench, which includes the scalloped recesses, is then bombarded with a molecular beam where the molecules are directed on an axis parallel to the trench sidewalls to reduce the scalloped recesses. | 03-12-2015 |
20150076657 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A novel method for manufacturing a semiconductor device and a semiconductor device are provided. The semiconductor device includes a substrate, a trench capacitor, a contact pad, an inter-layer dielectric (ILD) layer and contact elements. The trench capacitor includes a doped region, a first dielectric layer, a bottom electrode, a second dielectric layer and a top electrode, in which the contact pad is positioned on the doped region. The ILD layer has contact windows, and the contact elements are disposed therein. Because of the presence of the contact pad positioned on the doped region, the thickness of the ILD layer over the top electrode is increased but still satisfying the requirement of the maximum depth limit to the contact windows of etching the ILD layer. | 03-19-2015 |
20150097267 | INDUCTOR STRUCTURE WITH MAGNETIC MATERIAL AND METHOD FOR FORMING THE SAME - Embodiments of mechanisms of forming an inductor structure are provided. The inductor structure includes a substrate and a first dielectric layer formed over the substrate. The inductor structure includes a first metal layer formed in the first dielectric layer and a second dielectric layer over the first metal layer. The inductor structure further includes a magnetic layer formed over the first dielectric layer, and the magnetic layer has a top surface, a bottom surface and sidewall surfaces between the top surface and the bottom surface, and the sidewall surfaces have at least two intersection points. | 04-09-2015 |
20150145103 | CAPACITIVE DEVICE AND METHOD OF MAKING THE SAME - A capacitive device includes a well, a first dielectric layer, a first conductive layer, a cap dielectric layer, and a first electrode. The well includes a first shoulder portion having an upper surface, a second shoulder portion having an upper surface, and a first trench, sandwiched between the first and second shoulder portions, having sidewalls and a bottom surfaces. The first dielectric layer is lined along at least a portion of the upper surfaces of the first and second shoulder portions, the sidewalls of the first trench, and the bottom surface of the first trench. The first conductive layer is lined along the first dielectric layer. The cap dielectric layer is over the well, the first dielectric layer, and the first conductive layer. The first electrode is in contact with the first shoulder portion. | 05-28-2015 |
Patent application number | Description | Published |
20110292022 | POWER CONVERTING APPARATUS AND POWER CONVERTING METHOD - A power converting apparatus including a power converting unit and a control unit is provided. The power converting unit receives an input voltage and generates an output voltage for a display driving unit according to a control signal. The control unit provides the control signal to the power converting unit, wherein the control unit adjusts the duty cycle or the frequency of the control signal according to an image signal. In addition, a power converting method is also provided. | 12-01-2011 |
20120293473 | DISPLAY APPARATUS AND IMAGE COMPENSATING METHOD THEREOF - A display apparatus is disclosed. The display apparatus includes an environment luminance detector, a display image data analyser, and an image compensation processor. The environment luminance detector detects an environment luminance and generates an environment luminance grade according to the environment luminance. The display image data analyser receives display image data and analyses a luminance of the display image data to generate a display image data luminance grade. The image compensation processor generates an image luminance enhancement value, an image color compensating value and an image edge enhancement value. The image compensation processor compensates the display image data to generate compensated image data according to the image luminance enhancement value, the image color compensating value and the image edge enhancement value. | 11-22-2012 |
20130044088 | DATA TRANSMISSION METHOD AND DISPLAY DRIVING SYSTEM - A data transmission method applied in a display, which includes a display panel, is provided. The data transmission method includes the following steps of: providing a host controller and n display drivers, n is a natural number greater than 1; providing a communication link under mobile industry processor interface (MIPI), connecting the host controller to the n display drivers; determining n virtual channel values Vc1-Vcn corresponding to the respective n display drivers; employing the host controller for providing a command with a virtual channel parameter through the communication link under MIPI; when the virtual channel parameter corresponds to an i | 02-21-2013 |
20130044089 | DATA TRANSMISSION METHOD AND DISPLAY DRIVING SYSTEM - A data transmission method applied in a display, which includes a display panel, is provided. The data transmission method includes the following steps of: providing a host controller and n display drivers, n is a natural number greater than 1; providing a communication link under mobile industry processor interface (MIPI), connecting the host controller to the n display drivers; determining n virtual channel values Vc | 02-21-2013 |
20140247402 | In-cell Touch Control Panel - An in-cell touch control panel includes a liquid crystal layer; a top glass; a bottom glass; a plurality of driving electrodes, formed between the top glass and the liquid crystal layer; and a plurality of sensing electrodes, formed between the bottom glass and the liquid crystal layer, and perpendicular to the plurality of driving electrodes. The plurality of driving electrodes and the plurality of sensing electrodes are utilized for sensing a touch point on the in-cell touch control panel. | 09-04-2014 |
20140306968 | Method of Reading Data, Method of Transmitting Data and Mobile Device thereof - A method of reading data for a display drive IC of a panel is provided. The method includes receiving a write format and at least one image packet, generating a synchronization signal according to the write format, and reading data of the at least one image packet according to the synchronization signal such that the panel uses a video mode to display the data of the at least one image packet. | 10-16-2014 |
20140306969 | Display method and system capable of dynamically adjusting frame rate - A display method for a monitor is capable of dynamically adjusting a frame rate of a display panel in a monitor. The display method includes storing a display data outputted from a host to a memory unit, generating a control signal according to a frequency of storing the display data to the memory unit, adjusting the frame rate according to the control signal and a predefined adjustment value, and outputting the display data stored in the memory unit to the display panel according to the frame rate. | 10-16-2014 |
20150085452 | LAYOUT METHOD, ELECTRONIC DEVICE AND CONNECTOR - A layout method applied to a connector is provided. The connector is electrically connected between a flexible printed circuit (FPC) and a printed circuit board (PCB). The FPC includes M pairs of differential lines and X shield lines. The PCB includes M pairs of differential lines and Z shield lines. The layout method includes following steps. Firstly, M pairs of conductive lines are disposed on the connector. The M conductive lines are correspondingly electrically connected to the M differential lines of the FPC and the M differential lines of the PCB. Then; Y conductive lines are disposed on the connector, wherein Y is smaller than X. Furthermore, at least one of the Y conductive lines is electrically connected to at least one of the X shield lines and at least one of the Z shield lines. | 03-26-2015 |
Patent application number | Description | Published |
20130193448 | PATTERNED SUBSTRATE AND STACKED LIGHT EMITTING DIODE - A patterned substrate is provided, including: a substrate having a (0001) crystal plane and a plurality of alternatively arranged recess structures therein, thereby forming a plurality of alternatively arranged top surfaces; and a dielectric barrier layer covering the bottom surface and/or the sidewalls of the recess structures. Each of the alternatively arranged recess structures includes a bottom surface and a plurality of sidewalls surrounding the bottom surface. | 08-01-2013 |
20130207143 | PATTERNED SUBSTRATE OF LIGHT EMITTING SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A patterned substrate of a light emitting semiconductor device has a plurality of convex members on a top surface thereof. Each convex member has a substantially flat top surface and a plurality of convex arc-shaped sidewalls. | 08-15-2013 |
20140008766 | EPITAXIAL STRUCTURE AND EPITAXIAL GROWTH METHOD FOR FORMING EPITAXIAL LAYER WITH CAVITIES - An epitaxial growth method includes the steps of: providing a substrate; forming a sacrifice layer on the substrate; patterning the sacrifice layer to form a plurality of bumps spaced apart from each other on the substrate; epitaxially forming a first epitaxial layer on the substrate to cover a portion of each of the bumps; removing the bumps to form a plurality of cavities; and epitaxially forming a second epitaxial layer on the first epitaxial layer such that the cavities are enclosed by the first epitaxial layer and the second epitaxial layer. An epitaxial structure grown by the method is disclosed as well. | 01-09-2014 |
20150076537 | LIGHT-EMITTING DIODE - The present disclosure provides a light-emitting diode, including: a silicon substrate having a first surface and a second surface opposite to the first surface; a buffer layer disposed over the first surface of the substrate, wherein the buffer layer includes alternating SiC and In | 03-19-2015 |
20150214431 | LIGHT-EMITTING DIODE DEVICE AND METHOD FOR FABRICATING THE SAME - The invention provides a light-emitting diode device and a method for fabricating the same. The light-emitting diode device includes a metal substrate. A light-emitting diode structure is bonded on the metal substrate. The light-emitting diode structure includes a first type semiconductor substrate and a second type semiconductor layer. The first type semiconductor layer has a first surface and a second surface opposite to the first surface. The second type semiconductor layer is in contact with the metal substrate. A light-emitting layer is disposed between the first type semiconductor substrate and the second type semiconductor layer. A portion of the second surface and a sidewall adjacent to the second surface are uneven roughened surfaces. | 07-30-2015 |
20150228853 | EPITAXIAL STRUCTURE AND EPITAXIAL GROWTH METHOD FOR FORMING EPITAXIAL LAYER WITH CAVITIES - An epitaxial structure includes a substrate, a first epitaxial layer and a second epitaxial layer. The substrate has a surface, and the first epitaxial layer is disposed over the substrate and defines a plurality of slanting air voids tapering away from the substrate and an opening over each of the slanting air voids. The second epitaxial layer is disposed on the first epitaxial layer and collectively defines the slanting air voids in a shape of trapezoid with the surface and the first epitaxial layer. | 08-13-2015 |
20150228854 | EPITAXIAL STRUCTURE AND EPITAXIAL GROWTH METHOD FOR FORMING EPITAXIAL LAYER WITH CAVITIES - An epitaxial structure includes a substrate, a first epitaxial layer and a second epitaxial layer. The substrate has a surface, and the first epitaxial layer is disposed over the substrate and defines a plurality of stepped air voids and an opening over each of the stepped air voids. The second epitaxial layer is disposed on the first epitaxial layer and collectively defines the stepped air voids with the surface and the first epitaxial layer. | 08-13-2015 |
Patent application number | Description | Published |
20090103752 | DEVICE AND METHOD FOR AUTOMATICALLY ADJUSTING GAIN - A device and method are provided for automatically adjusting gain, including a conversion module for converting an audio time-domain signal to an audio frequency-domain signal, an analysis module for analyzing the audio frequency-domain signal in accordance with an equal-loudness level contour of human hearing so as to generate strength weightings and generating a signal strength in accordance with the weightings, a calculation module for calculating a gain by analysis of the audio frequency-domain signal when the signal strength falls outside a default range, and a control module for generating an audio output signal in accordance with the gain and the audio time-domain signal. | 04-23-2009 |
20090257335 | AUDIO SIGNAL PROCESSING METHOD - An audio signal processing method includes the steps of: dividing an audio signal data stream into a plurality of selection segments; determining a target segment in the audio signal data stream, the target segment including a splice point for splicing a splice segment thereto; selecting one of the selection segments as the splice segment according to at least one parameter of the target segment; and processing the target segment and the splice segment to splice the splice segment to the target segment, and outputting a processed segment. | 10-15-2009 |
20140215204 | DEVICE FOR PREVENTING LOGGING OF CLIENTS INPUT DATA IN A COMPUTER SYSTEM - A device for preventing logging of client input data in a computer system, characterized in that it includes a first transmission interface used to connect the smart electronic device, a second transmission interface used to connect the computer system, and a data encryption chip for encryption of the input data. The data encryption chip is set between the first and second transmission interfaces and is used to encrypt data input from the first transmission interface, and then transmit the encrypted data to the computer system via the second transmission interface. The device allows for the use of a smart electronic device as a real keyboard, and the computer system permits the data encryption chip to encrypt the data input by the smart electronic device, which are then sent to the computer system, helping to prevent logging of keying data with higher efficacy and applicability. | 07-31-2014 |
Patent application number | Description | Published |
20120044398 | CMOS SENSOR WITH LOW PARTITION NOISE AND LOW DISTURBANCE BETWEEN ADJACENT ROW CONTROL SIGNALS IN A PIXEL ARRAY - A CMOS image sensor includes a pixel array including a plurality of unit pixels with individual rows of unit pixels being coupled to respective row control signal lines, and a buffer including plural row control signal drivers. Each driver is coupled to a respective one of the row control signal lines and is configured to provide a row control signal pulse to a respective row control signal line in response to an input pulse when the row control signal line is in an active state and to bias the row control signal line at a ground voltage when the respective row control signal line is in an inactive state. Each driver has a first drive capability when the row control signal line is in the active state and a second drive capability greater than the first drive capability when the row control signal line is in an inactive state. | 02-23-2012 |
20120098975 | COLOR IMAGE SENSOR ARRAY WITH COLOR CROSSTALK TEST PATTERNS - An integrated circuit comprises a semiconductor substrate and a color image sensor array on the substrate. The color image sensor array has a first configuration of color pixels for collecting color image data, and at least one crosstalk test pattern on the substrate proximate the color image sensor array. The crosstalk test pattern includes a plurality of color sensing pixels arranged for making color crosstalk measurements. The test pattern configuration is different from the first configuration. | 04-26-2012 |
20130113958 | COLOR IMAGE SENSOR ARRAY WITH COLOR CROSSTALK TEST PATTERNS - An integrated circuit comprises a semiconductor substrate and a color image sensor array on the substrate. The color image sensor array has a first configuration of color pixels for collecting color image data, and at least one crosstalk test pattern on the substrate proximate the color image sensor array. The crosstalk test pattern includes a plurality of color sensing pixels arranged for making color crosstalk measurements. The test pattern configuration is different from the first configuration. | 05-09-2013 |
20130228671 | CMOS SENSOR ARRAY - A CMOS sensor includes a pixel configured to output a voltage based on incident light received by the pixel. A first circuit is coupled to the pixel and is configured to determine a reset voltage of the pixel. A second circuit is coupled to the first circuit and is configured to select a gain level based on the reset voltage of the pixel. A gain circuit is coupled to the second circuit and is configured to set a voltage level of the gain selected by the second circuit. | 09-05-2013 |
20130271626 | METHOD OF REDUCING COLUMN FIXED PATTERN NOISE - A method of reducing column fixed pattern noise including calibrating a readout circuit, wherein the readout circuit is electrically connected to at least one programmable gain amplifier and an analog-to-digital converter. Calibrating the readout circuit includes electrically disconnecting the readout circuit from a pixel output and electrically connecting a pixel reset input of the readout circuit to a pixel output signal input of the readout circuit. Calibrating the readout circuit further includes comparing a measured output of the readout circuit to a predetermined value and storing the comparison result in a non-transitory computer readable medium. The method further includes operating the readout circuit, the operating the readout circuit includes receiving a pixel sample signal and outputting a calibrated output based on an operating output and the stored comparison result. | 10-17-2013 |
20140042303 | CMOS SENSOR WITH LOW PARTITION NOISE AND LOW DISTURBANCE BETWEEN ADJACENT ROW CONTROL SIGNALS IN A PIXEL ARRAY - A CMOS image sensor includes a pixel array including a plurality of unit pixels with individual rows of unit pixels being coupled to respective row control signal lines, and a buffer including plural row control signal drivers. Each driver is coupled to a respective one of the row control signal lines and is configured to provide a row control signal pulse to a respective row control signal line in response to an input pulse when the row control signal line is in an active state and to bias the row control signal line at a ground voltage when the respective row control signal line is in an inactive state. Each driver has a first drive capability when the row control signal line is in the active state and a second drive capability greater than the first drive capability when the row control signal line is in an inactive state. | 02-13-2014 |
20140077057 | 3D-STACKED BACKSIDE ILLUMINATED IMAGE SENSOR AND METHOD OF MAKING THE SAME - A stacked image sensor and method for making the same are provided. The stacked image sensor includes an upper chip with a pixel array thereon. The second chip includes a plurality of column circuits and row circuits associated with the columns and rows of the pixel array and disposed in respective column circuit and row circuit regions that are arranged in multiple groups. Inter-chip bonding pads are formed on each of the chips. The inter-chip bonding pads on the second chip are arranged linearly and are contained within the column circuit regions and row circuit regions in one embodiment. In other embodiments, the inter-chip bonding pads are staggered with respect to each other. In some embodiments, the rows and columns of the pixel array include multiple signal lines and the corresponding column circuit regions and row circuit regions also include multiple inter-chip bonding pads. | 03-20-2014 |
20140184316 | BIAS CONTROL - One or more techniques or systems for bias control are provided herein. In some embodiments, the bias control relates to biasing of a column of one or more pixels for an image sensor. In some embodiments, an associated circuit includes a reset transistor, a source-follower transistor, a first transfer transistor, a first bias transistor, a second bias transistor, and a switch connected to the second bias transistor. In some embodiments, the first bias transistor and the second bias transistor bias a column of pixels at a first time. In some embodiments, the second bias transistor is turned off, thus removing a second bias at a second time. In this way, performance of the image sensor is improved, at least because the second bias transistor enables faster settling time when active, and a wide pixel operation range when switched off. | 07-03-2014 |
20140217263 | IMAGE SENSOR CONFIGURED TO REDUCE BLOOMING DURING IDLE PERIOD - Among other things, techniques and systems are provided for identifying when a pixel of an image sensor is in an idle period. A flag is utilized to differentiate when the pixel is in an idle period and when the pixel is in an integration period. When the flag indicates that the pixel is in an idle period, a blooming operation is performed on the pixel to reduce an amount of electrical charge that has accumulated at the pixel or to mitigate electrical charge from accumulating at the pixel. In this way, the blooming operation reduces a probability that the photosensitive sensor becomes saturated during an idle period of the pixel, and thus reduces the likelihood of electrical charge from a pixel that is not intended contribute to an image from spilling over and potentially contaminating a pixel that is intended to contribute to the image. | 08-07-2014 |
20140217265 | CMOS SENSOR ARRAY - A CMOS sensor includes a pixel configured to output a voltage based on incident light received by the pixel. Circuitry is coupled to the pixel and is configured to determine a reset voltage of the pixel and to select a gain level based on the reset voltage of the pixel. A gain circuit is coupled to the circuitry and is configured to set a voltage level of the gain selected by the circuitry. | 08-07-2014 |
20140252202 | COLUMN ANALOG-TO-DIGITAL CONVERTER FOR CMOS SENSOR - A system and method is disclosed for an imaging device and/or an analog to digital converter which converts an analog input signal to a digital data signal using a comparator which compares the analog input signal to a first ramped reference signal to determine an operating point and then uses the same comparator to compare the analog input signal to a second ramped reference signal multiple times about the determined operating point. | 09-11-2014 |
20140266831 | LOW GLITCH CURRENT DIGITAL-TO-ANALOG CONVERTER - The present disclosure relates to a method and architecture to minimize a transient glitch within a current digital-to-analog converter (DAC) comprising an array of identical current unit cells. The current DAC is configured with individual column decoders for even and odd rows of current unit cells, thus allowing for independent control of adjacent rows. The even row and odd row column decoders further comprise thermal decoders with coupled timing encoding which establishes synergy between an adjacent pair of rows. As current units cells within an active row are activated across the row by a counting up of a first column decoder, the current units cells within a next row adjacent the active row are returned to an initial state of the active row by counting down in a second column decoder. Other devices and methods are also disclosed. | 09-18-2014 |
20140266991 | Systems and Methods to Mitigate Transient Current for Sensors - A sensor system includes a pixel array, column units and a compensation circuit. The pixel array is configured to provide pixel column data. The column units are configured to generate an offset data out signal from the pixel column data. The offset data out signal includes digital offsets. The compensation circuit is configured to remove the digital offsets from the offset data out signal. The compensation circuit is also configured to generate a data out signal. | 09-18-2014 |
20140347535 | APPARATUS WITH CALIBRATED READOUT CIRCUIT - An apparatus comprises a readout circuit configured to be disconnected from a pixel output, and to connect a pixel reset signal received by the readout circuit to a pixel output signal received by the readout circuit. The apparatus also comprises at least one programmable gain amplifier coupled with the readout circuit. The apparatus further comprises an analog-to-digital converter coupled with the programmable gain amplifier. The readout circuit is configured to be calibrated based on a comparison of a measured output of the readout circuit to a predetermined value, the predetermined value being equal to (2 | 11-27-2014 |
20150116506 | NOISE SIMULATION FLOW FOR LOW NOISE CMOS IMAGE SENSOR DESIGN - A method for noise simulation of a CMOS image sensor comprises performing a frequency domain noise simulation for a readout circuit of the CMOS image sensor using a computer, wherein the readout circuit includes a correlated double sampling (CDS) circuit, wherein the frequency domain noise simulation includes a CDS transfer function to refer a noise introduced by the CDS circuit back to an input node of the readout circuit. The method further comprises calculating noise at the input node of the readout circuit based on the referred back noises caused by one or more components in the readout circuit and estimating noise of the CMOS imaging sensor by comparing the calculated noise at the input node of the readout circuit to an original input signal to the readout circuit of the CMOS imaging sensor. | 04-30-2015 |
20150215556 | READOUT DEVICE WITH READOUT CIRCUIT - A readout device comprises a readout circuit having a first switch configured to receive a pixel reset signal, a second switch configured to receive a pixel output signal, and a third switch configured to connect the first switch to the second switch. A first capacitor is connected to the first switch, a second capacitor is connected the second switch, a fourth switch is connected to the first capacitor, and a fifth switch is connected to the second capacitor. The fifth switch is connected to the fourth switch. The readout circuit also comprises a sixth switch connected to the first capacitor and a seventh switch connected to the second capacitor. The sixth switch is configured to provide a first output of the readout circuit, and the seventh is configured to provide a second output of the readout circuit. | 07-30-2015 |
Patent application number | Description | Published |
20090146726 | DELAY CIRCUIT WITH CONSTANT TIME DELAY INDEPENDENT OF TEMPERATURE VARIATIONS - A delay circuit has: an inverting receiver with a resistive element, the inverting receiver having an input node for receiving an input signal and an output node coupled to the resistive element; a capacitive element, coupled to the output node of the inverting receiver and the resistive element; a first transistor, having lower turned ON voltage at higher temperature; a second transistor, used for generating a rail to rail signals on a terminal of the first transistor; and an output inverter, having an input node coupled to the first transistor and an output node for outputting an output signal of the delay circuit. Further, a third transistor is used for enhancing pulling low of the output signal of the delay circuit. | 06-11-2009 |
20090147594 | VOLTAGE REGULATOR FOR SEMICONDUCTOR MEMORY - A voltage regulator in a semiconductor memory has: a comparing unit including first and second bias current sources, for comparing an output voltage with first and second reference voltages under control of a first signal, the second bias current source being ON under control of a second signal; and a driver active element, coupled to the comparing unit, for outputting the output voltage. Before sensing operations, the output voltage is reset to the second reference voltage. During the sensing operations, the output voltage is maintained at the first reference voltage and the second signal is asserted for turning ON the second bias current source for raising speed of the comparing unit. After the sensing operations, the output voltage is reset to the second reference voltage. | 06-11-2009 |
20110188322 | MEMORY DEVICE WITH DATA PATHS FOR OUTPUTTING COMPRESSED DATA - A memory device is provided. The memory device includes a plurality of memory array banks, a bus, a data buffer, and four data paths. The data buffer provides data from the memory array banks to an external node. The first data path includes a first compression module for compressing the data from the memory array banks to the bus. The second data path transmits the data from the memory array banks to the bus. The third data path includes a second compression module for compressing data from the bus to the data buffer. The fourth data path transmits the data from the bus to the data buffer. | 08-04-2011 |
20110211398 | MEMORY DEVICE AND ASSOCIATED MAIN WORD LINE AND WORD LINE DRIVING CIRCUIT - A main word line driving circuit for driving word lines in a memory device comprises first and second level shifting units and an inverting unit. The first level shifting unit is configured to convert a decode signal into a first operative signal, and the second level shifting unit is configured to convert the decode signal into a second operative signal. The inverting unit is configured to receive the first and second operative signals. A supply voltage of the first level shifting unit is selectively switched to a first bias voltage when the plurality of word lines are selected or partially selected and switched the output voltage to a second bias voltage when the plurality of word lines are deselected. | 09-01-2011 |
20110211407 | SEMICONDUCTOR MEMORY DEVICE AND ASSOCIATED LOCAL SENSE AMPLIFIER - A semiconductor memory device comprises a plurality of memory cells, a bit line sense amplifier, a local sense amplifier, and a sense amplifier. The memory cells are connected between a word line and a bit line pair, and the bit line sense amplifier is configured to amplify voltages of data from the bit line pair and then transmits the data to a local data line pair. The local sense amplifier is configured to amplify voltages of the data from the local data line pair and transmit the data to a global data line pair in response to first and second control signals, and the sense amplifier is configured to amplify the voltages of the data from the global data line pair and transmit the data to an input/output line pair during a read operation. The local sense amplifier comprises a first read circuit, a second read circuit, and a write circuit, and when the memory device performs the read operation, the data is transmitted from the first read circuit to the write circuit via the second read circuit. | 09-01-2011 |
20110211417 | MEMORY DEVICE WITH PSEUDO DOUBLE CLOCK SIGNALS AND THE METHOD USING THE SAME - A method for operating a memory device with pseudo double clock signals comprises the steps of: generating an even clock signal and an odd clock signal, wherein the clock rates of both the even clock signal and the odd clock signal are half that of the input clock signal, and the even clock signal is the inverse signal of the odd clock signal; if the logic level of the even clock signal is | 09-01-2011 |
20110227624 | DUTY CYCLE CORRECTION CIRCUIT - A duty cycle correction circuit comprises first and second pulse generators, a clock dividing unit, a detecting unit, and a pulse width control unit. The first pulse generator is configured to generate a first edge of a first pulse signal in synchronization with a first edge of a first clock signal, and the second pulse generator is configured to generate a first edge of a second pulse signal in synchronization with a second edge of the first pulse signal. The clock dividing unit is configured to generate a second clock signal by dividing the frequency of the first clock signal. The detecting unit is configured to generate a detecting signal according to the second clock signal and a time interval between the first edge of the first pulse signal and a second edge of the second pulse signal. In particular, pulse widths of the first and second pulse signals are the same and are adjustable according to a control signal from the pulse width control unit. | 09-22-2011 |
20110228620 | TESTING METHOD FOR SEMICONDUCTOR MEMORY DEVICE - A method comprises simultaneously writing a test bit to a plurality of memory cells in the selected sections of a memory array corresponding to column address signals; individually and successively reading output bits from the memory cells in one of the selected sections of a designated row of the memory array corresponding to column address signals and row address signals; and error-checking the output bits with the test bit, wherein the memory array comprises the plurality of memory cells arranged in rows and columns and the memory cells of each row are divided into a plurality of sections. | 09-22-2011 |
20110235451 | DYNAMIC RANDOM ACCESS MEMORY AND METHOD OF DRIVING DYNAMIC RANDOM ACCESS MEMORY - A dynamic RAM which includes a first inverter, a second inverter, a sense amplifier, a first pair of switches, a pair of bit lines, and a dynamic RAM cell. The first inverter receives a first driving signal. A power end of the first inverter is coupled to a first voltage source. The second inverter receives a second driving signal output from the first inverter. A power end of the second inverter is coupled to a second voltage source. The sense amplifier senses and amplifies a voltage difference between a first sensing signal and a second sensing signal. A power end of the sense amplifier is coupled to a third voltage source, wherein a voltage value of the second voltage source is between a voltage value of the first voltage source and a voltage value of the third voltage source. | 09-29-2011 |
20110239046 | TEST CIRCUIT FOR INPUT/OUTPUT ARRAY AND METHOD AND STORAGE DEVICE THEREOF - The invention provides a test circuit for n input/output arrays. Each of the n input/output arrays has M pairs of input/output. The test circuit includes M write drivers and M comparing circuits. The i | 09-29-2011 |
20130021862 | DRAM AND METHOD FOR TESTING THE SAME IN THE WAFER LEVEL BURN-IN TEST MODE - A dynamic random-access memory (DRAM) and a method for testing the DRAM are provided. The DRAM includes a memory cell, a bit line associated with the memory cell, a local buffer, and a bit line sense amplifier (BLSA). The local buffer receives a first power voltage as power supply. The local buffer provides a ground voltage to the bit line when a data signal is de-asserted and provides the first power voltage to the bit line when the data signal is asserted. The BLSA receives a second power voltage as power supply. The BLSA provides the second power voltage to the bit line when the data signal and a wafer level burn-in test signal are both asserted. The second power voltage may be higher than the first power voltage. The wafer level burn-in test signal is asserted when the DRAM is in a wafer level burn-in test mode. | 01-24-2013 |
20130049830 | DELAY LOCK LOOP CIRCUIT - The invention provides a delay lock loop circuit (DLL) for generating a locked signal, the DLL circuit includes: a phase detector, a first and a second voltage controlled delay chains, a charge pump and a duty cycle detection pump. The phase detector generates a phase detecting result by detecting a phase difference between the clock signal and the locked signal. The first and the second voltage controlled delay chains generate a first and a second delayed signals by delaying the clock signal according to the first and the second control signals, respectively. The charge pump is used for generating the first and the second control signal according to the phase detecting result. The duty cycle detection pump is used for controlling a voltage level of the second control signal according to the first and the second delayed signals. | 02-28-2013 |
20150155873 | INPUT BUFFER WITH CURRENT CONTROL MECHANISM - An input buffer includes a first driving circuit, a second driving circuit, a pull up circuit, and a pull down circuit. The first driving circuit is arranged for driving a first input signal to generate an output signal. The second driving circuit is arranged for driving the output signal. The pull up circuit is arranged for selectively controlling the second driving circuit to pull up the output signal according to the first input signal and a second input signal. The pull down circuit is arranged for selectively controlling the second driving circuit to pull down the output signal according to the first input signal and the second input signal. | 06-04-2015 |
20150162096 | MEMORY TEST SYSTEM AND METHOD - An exemplary embodiment of the present disclosure illustrates a memory test system comprising a memory device, a probe card, and a tester. The memory device comprises a memory die with a plurality of memory banks, a plurality of input circuits, and a plurality of output circuits, wherein each of the input circuits has a first input pin and a second pin, the first input pins of the input circuits are used to read a plurality of patches of data stored in memory cells of the memory banks, and the second input pins are used to receive a compressed result. The output circuits receive compressed signals output from the input circuits, and the probe card mixes the compressed output signals output from the output circuits to output a mixed compressed output signal to the tester. | 06-11-2015 |
Patent application number | Description | Published |
20120243310 | METHOD OF PROGRAMMING A MULTI-BIT PER CELL NON-VOLATILE MEMORY - A method of programming a multi-bit per cell non-volatile memory is disclosed. In one embodiment, the non-volatile memory is read to obtain a first data of a most-significant-bit (MSB) page on a current word line that succeeds in data reading, wherein the current word line follows a preceding word line on which data reading fails. At least one reference voltage is set. The MSB page on the current word line is secondly programmed with a second data according to the reference voltage, the second data being different from the first data. | 09-27-2012 |
20130042051 | PROGRAM METHOD FOR A NON-VOLATILE MEMORY - A program method for a non-volatile memory is disclosed. At least two blocks in the non-volatile memory are configured as 1-bit per cell (1-bpc) blocks. The data of the configured blocks are read and written to a target block in such a way that the data of each said configured block are moved to pages of a same significant bit. In another embodiment, the data of the configured blocks excluding one block are read and written to the excluded block. | 02-14-2013 |
20130044542 | METHOD OF SORTING A MULTI-BIT PER CELL NON-VOLATILE MEMORY AND A MULTI-MODE CONFIGURATION METHOD - A method of sorting a multi-bit per cell non-volatile memory includes programming and reading to test an n-bit-per-cell (n-bpc) non-volatile memory, which has a plurality of m-bpc pages, where m is a positive integer from 1 through n. If the m-bpc page fails the test, counting a block associated with the failed m-bpc page to (m-1)-bpc blocks, wherein each said m-bpc page is subjected to at most one time of programming and reading. When m is equal to 1, the 0-bpc block corresponds to a bad block. | 02-21-2013 |
20130179749 | METHOD AND SYSTEM OF DYNAMIC DATA STORAGE FOR ERROR CORRECTION IN A MEMORY DEVICE - A method of dynamic data storage for error correction in a memory device is disclosed. Data for storage is received, the received data is encoded and error correction code (ECC) is generated. The encoded data is stored in the memory device that includes a plurality of pages each having a plurality of data partitions. More corrected errors a marked page has, a smaller portion with a space of at least one datum of each of the corresponding data partitions associated with the marked page is allocated to store the encoded data, while a size of the ECC is fixed, thereby increasing capability of correcting errors in the marked page. | 07-11-2013 |
20130250682 | METHOD OF PROGRAMMING A MULTI-BIT PER CELL NON-VOLATILE MEMORY - A method of programming a multi-bit per cell non-volatile memory is disclosed. In one embodiment, the non-volatile memory is read to obtain a first data of a most-significant-bit (MSB) page on a current word line that succeeds in data reading, wherein the current word line follows a preceding word line on which data reading fails. At least one reference voltage is set. The MSB page on the current word line is secondly programmed with a second data according to the reference voltage, the second data being different from the first data. | 09-26-2013 |
20130286733 | METHOD OF PROGRAMMING/READING A NON-VOLATILE MEMORY WITH A SEQUENCE - A method of programming/reading a multi-bit per cell non-volatile memory with a sequence is disclosed. A plurality of less-significant-bit pages are programmed, and a plurality of consecutive most-significant-bit pages of a plurality of consecutive word lines are programmed one after the other in a consecutive order. The most-significant-bit pages through all word lines in at least one memory block of the non-volatile memory are programmed or read after the less-significant-bit pages through all the word lines in the at least one memory block are programmed or read. | 10-31-2013 |
20140032813 | METHOD OF ACCESSING A NON-VOLATILE MEMORY - A method of accessing a non-volatile memory is disclosed. Original bits of data are duplicated on a bit level to generate a plurality of duplicated bits corresponding to each original bit. At least one shielding bit is provided between the duplicated bits corresponding to different original bits. The duplicated bits and the at least one shielding bit are programmed to the non-volatile memory. The original bits are generated or determined according to the duplicated bits. | 01-30-2014 |
Patent application number | Description | Published |
20110134280 | SYSTEM AND METHOD FOR CONSTRUCTING HIGH DYNAMIC RANGE IMAGES - A system for constructing a high dynamic range image includes a light generating device, a reflective mirror device, a controller, an image capturing device and an image processing module. The light generating device generates a light beam. The reflective mirror device directs the light beam to an object. The controller generates an intensity controlling signal for controlling the light generating device to modulate an intensity of the light beam in accordance with illuminating parameters, and to generate a direction controlling signal for controlling a reflection direction of the reflective mirror device. The image capturing device obtains an original image of the object or a modulated image of the object. The image processing module analyzes the original image to generate the illuminating parameters, or to construct a high dynamic range image of the object in accordance with the modulated image and the illuminating parameters. | 06-09-2011 |
20120154574 | SYSTEM AND METHOD FOR CONSTRUCTING HIGH RESOLUTION IMAGES - A system for constructing high resolution images includes a beam splitter assembly, a light intensity modulator, an image capturing module and an image processing module. The beam splitter assembly is utilized to reflect a light beam generated from a light source generating device and generate a splitting beam. The light intensity modulator is utilized to modulate the intensity of the splitting beam to generate a modulating beam, which includes a predetermined noise. The modulating beam is emitted onto an object to generate a modulating image. The image capturing module is utilized to obtain a plurality of modulating images. The image processing module is utilized to analyze the modulating images to generate a high resolution image. | 06-21-2012 |
20140175270 | DISPLAY MEASURING DEVICE - A display measuring device for measuring a display, includes a photosensitive unit, a first rotation plane mirror, a second rotation plane mirror, a first lens module, a second lens module, and an optic reflecting unit. The first lens module projects a first incident image from the display to the first rotation plane minor. The first rotation plane minor reflects the projected first incident image from the first lens module to the optic reflecting unit. The second lens module projects a second incident image from the display to the second rotation plane minor. The second rotation plane minor reflects the projected second incident image from the second lens module to the optic reflecting unit. The optic reflecting unit reflects the reflected first incident image to the photosensitive unit, and reflects the reflected second incident image to the photosensitive unit. | 06-26-2014 |
Patent application number | Description | Published |
20090236270 | WATER PURIFICATION SYSTEM - A water purification system performs a water purification process through physical sterilization, and at least includes a compression device and a decompression device. Water is converted into a high-pressure liquid through the compression device, and then is converted into a high-speed fluid by controlling the cross-sectional area of a spout of the decompression device, thus generating physical effects such as pressure drop and shear stress, so as to damage cell walls of bacteria in the liquid to die-off the bacteria. Therefore, purified water is obtained. | 09-24-2009 |
20120251035 | CIRCULAR PHOTONIC CRYSTAL STRUCTURE, LIGHT EMITTING DIODE DEVICE AND PHOTOELECTRIC CONVERSION DEVICE - A method applying a circular photonic crystal structure to improve optical properties of a photoelectric conversion device such as a light emitting diode device, an organic light emitting diode device or a solar cell is provided, wherein the circular photonic crystal structure is configured on a junction surface between two different mediums where passes a light emitted or received by the photoelectric conversion device. The circular photonic crystal structure provides isotropic photonic band gap which conduces high light extraction efficiency. | 10-04-2012 |
20120315724 | METHOD AND APPARATUS FOR DEPOSITION OF SELENIUM THIN-FILM AND PLASMA HEAD THEREOF - A method for deposition of a selenium thin-film includes the following steps. First, a plasma head is provided. Then, a substrate is supported in an atmospheric pressure. Next, a solid-state selenium source is dissociated by the plasma head to deposit the selenium thin-film on the substrate. The plasma head includes a chamber, a housing and the solid-state selenium source. Plasma is produced in the chamber. The chamber is surrounded by the housing. The solid-state selenium source is supported by the housing. | 12-13-2012 |
20130170203 | LIGHT-EMITTING DIODE ARRAY LIGHT SOURCE AND OPTICAL ENGINE HAVING THE SAME - A light-emitting diode (LED) array light source includes a substrate, a meshed light-shielding layer, LED chips, and a micro-lens array. The meshed light-shielding layer includes bar-shaped light-shielding patterns intersected with one another to define openings. Each bar-shaped light-shielding pattern has a bottom surface, a top surface, and two side surfaces. A width of the top surface is smaller than that of the bottom surface. A thickness of the meshed light-shielding layer is T | 07-04-2013 |
20130277195 | TOUCH SENSOR - A touch sensor is provided. The touch sensor includes a first buffer layer disposed on a substrate, a first electrode layer disposed on the first buffer layer, a second buffer layer disposed on the first electrode layer and a second electrode layer disposed on the second buffer layer and electrically connected with the first electrode layer, wherein the first and second buffer layers are formed of the same material including an insulated metal oxide, and the first and second electrode layers are formed of the same material including a doped metal oxide. | 10-24-2013 |
20130312822 | SOLAR-CELL DEVICE - The disclosure provides a solar-cell device, including a substrate, a first electrode layer comprising a first two-dimensional periodic structure disposed on the substrate, a first light conversion layer disposed on the first two-dimensional periodic structure, a second light conversion layer disposed on the first light conversion layer; and a second electrode layer disposed on the second light conversion layer. | 11-28-2013 |
Patent application number | Description | Published |
20120141937 | Photosensitive Composition and Photoresist - A photosensitive composition and a photoresist are provided. The photoresist is formed by compounding a photosensitive composition. The photosensitive composition comprises a binder agent, a photomonomer and a photoinitiator. The binder agent is formed by polymerizing a binder composition. The binder composition comprises a lactic oligomer. The photomonomer has an amount of about 25-95 parts by weight relative to 100 parts by weight of a solid content of the binder agent. The photo initiator has an amount of about 0.5-15 parts by weight relative to 100 parts by weight of the solid content of the binder agent. | 06-07-2012 |
20130137042 | PHOTOSENSITIVE COMPOSITION AND PHOTORESIST - A photosensitive composition and a photoresist are provided. The photoresist is formed by compounding a photosensitive composition. The photosensitive composition comprises a binder agent, a photomonomer and a photoinitiator. The binder agent has a chemical structure comprising following repeating unit: | 05-30-2013 |
20140128528 | WHITE COATING COMPOSITION, AND DEVICE EMPLOYING COATING MADE THEREFROM - The disclosure provides a white coating composition, and a device employing a coating made of the composition. The white coating composition includes 20-55 parts by weight of silicon dioxide particles, 40-75 parts by weight of inorganic material, and 5-40 parts by weight of silsequioxane, wherein the silsequioxane is prepared from monomers comprising a first monomer represented by the Formula (I) and a second monomer represented by the Formula (II) | 05-08-2014 |
20140361836 | CURRENT AMPLIFIER AND TRANSMITTER USING THE SAME - A current amplifier and a transmitter using the same. The current amplifier includes: a first transistor having a gate coupled to a former-stage circuit, a drain coupled to a current source, and a source biased at a constant voltage level; a second transistor having a gate coupled to the current source and having a source and a drain; | 12-11-2014 |
Patent application number | Description | Published |
20100123383 | DUAL-PURPOSE LIGHT-PENETRATING AND LIGHT-EMITTING DEVICE AND LIGHT-PENETRATIVE ILLUMINATING STRUCTURE - A dual-purpose light-penetrating and light-emitting device is provided. The dual-purpose light-penetrating and light-emitting device includes a first transparent substrate, a spacing sidewall, a second transparent substrate, and a light-penetrative illuminating structure. The spacing sidewall is disposed between the first transparent substrate and the second transparent substrate for configuring a hermetic space. The light-penetrative illuminating structure includes a cathode structure, an anode structure, a low pressure gas layer, and a patterned fluorescent layer. The low pressure gas layer is accommodated in the hermetic space. The cathode structure and the anode structure are oppositely disposed on the first transparent substrate and the second transparent substrate, respectively. The patterned fluorescent layer is positioned between the cathode structure and the anode structure, for allowing an ambient natural light penetrating therethrough. | 05-20-2010 |
20100141112 | ELECTRON EMISSION DEVICE AND METHOD OF PACKAGING THE SAME - An electron emission device including a first substrate, a second substrate, a gas, a sealant, and a phosphor layer is provided. The first substrate has a cathode thereon, and the cathode has a patterned profile. The second substrate is opposite to the first substrate and has an anode thereon. The sealant is disposed at edges of the first substrate and the second substrate to assemble the first and second substrates. The gas is disposed between the cathode and the anode and configured to induce a plurality of electrons from the cathode, wherein the pressure of the gas is between 10 torr and 10− | 06-10-2010 |
20100147689 | METHOD FOR MODIFYING SURFACE OF ALUMINUM OXIDE AND ELECTROOSMOSIS PUMP AND ELECTRIC POWER GENERATOR USING MODIFIED ALUMINUM OXIDE MEMBRANE - The invention provides a method for modifying a surface of aluminum oxide. Aluminum oxide is contacted with a hydrogen peroxide aqueous solution having 5-70 volume % of hydrogen peroxide for 20 minutes to 3 hours. The invention also provides an electroosmosis pump and electric power generator having a porous aluminum oxide membrane modified by the above method. | 06-17-2010 |
20100148657 | Plane light source - A plane light source is provided. The plane light source includes an anode layer, a cathode layer, a discharging gas, and at least one fluorescent layer. The discharging gas is between the anode layer and the cathode layer. The fluorescent layer is disposed on the anode layer and located between the anode layer and the cathode layer. In the plane light source, electrons is activated by discharge of the discharging gas and emitted from the cathode layer. The fluorescent layer is adapted for emitting a light when being bombarded by the electrons. | 06-17-2010 |
20110183576 | METHOD OF PACKAGING ELECTRON EMISSION DEVICE - An electron emission device including a first substrate, a second substrate, a gas, a sealant, and a phosphor layer is provided. The first substrate has a cathode thereon, and the cathode has a patterned profile. The second substrate is opposite to the first substrate and has an anode thereon. The sealant is disposed at edges of the first substrate and the second substrate to assemble the first and second substrates. The gas is disposed between the cathode and the anode and configured to induce a plurality of electrons from the cathode, wherein the pressure of the gas is between 10 torr and 10 | 07-28-2011 |
20110227498 | 3-DIMENSION FACET LIGHT-EMITTING SOURCE DEVICE AND STEREOSCOPIC LIGHT-EMITTING SOURCE DEVICE - A 3-dimension facet light-emitting source device including a transparent container, an anode plate, a cathode plate, a plurality of transparent plates and a low-pressure gas layer is provided. The transparent container has a sealed space. The transparent plates are disposed between the anode plate and the cathode plate, and have a fluorescent layer thereon respectively. The lower pressure gas layer is filled in the sealed space to induce electrons emitting from the cathode plate, and the electrons fly in a direction parallel to the transparent plates and hit each fluorescent layer to emit light, so as to form a set of 3-dimension facet patterns. | 09-22-2011 |
Patent application number | Description | Published |
20140030866 | METHOD AND APPARATUS FOR PREPARING POLYSILAZANE ON A SEMICONDUCTOR WAFER - A method for depositing a polysilazane on a semiconductor wafer is provided. The method includes steps of disposing a silazane onto the semiconductor wafer, and heating the silazane to form the polysilazane on the semiconductor wafer. An apparatus for preparing a polysilazane on a semiconductor wafer is also provided. | 01-30-2014 |
20140162534 | POLISHING SYSTEM AND POLISHING METHOD - A polishing system for polishing a semiconductor wafer includes a wafer support for holding the semiconductor wafer, and a first polishing pad for polishing a region of the semiconductor wafer. The semiconductor wafer has a first diameter, and the first polishing pad has a second diameter shorter than the first diameter. | 06-12-2014 |
20150101482 | MECHANISMS FOR CONTROLLING GAS FLOW IN ENCLOSURE - Embodiments of mechanisms for controlling a gas flow in an interface module are provided. A method for controlling a gas flow in an enclosure includes providing the enclosure which is capable of containing a substrate. The method also includes providing a gas into the enclosure. The method further includes cleaning the gas. In addition, the method includes actuating the gas to generate the gas flow, and the gas flow passes through the substrate when the substrate is located in the enclosure. | 04-16-2015 |
20150101703 | ULTRA-LOW OXYGEN AND HUMILITY LOADPORT AND STOCKER SYSTEM - One or more apparatuses for adjusting at least one of an oxygen content or a water content in a pod and methods of their use are provided, where one or more semiconductor wafer are selectively stored within a storage chamber of the pod. The apparatus comprises the pod and a pipeline. The pod comprises the storage chamber and a port. The port comprises a receptacle having a first opening and a constraining ring proximate the first opening. The pipeline comprises a pipe, a diffuser attached to a first end of the pipe and a controller attached to a second end of the pipe. | 04-16-2015 |
20150101959 | ULTRA-LOW OXYGEN AND HUMILITY LOADPORT AND STOCKER SYSTEM - One or more pods for adjusting at least one of an oxygen content or a water content therein and methods of their use are provided, where one or more semiconductor wafer are selectively stored within a storage chamber of the pod. The pod comprises a storage chamber having a side wall surface defining an opening at one side thereof and a pod door fitted to the storage chamber at the opening so as to provide ingress and egress to the storage chamber. The pod door comprises a door body, a first door locking mechanism on the door body and a seal band configured to engage the sidewall surface. The first door locking mechanism comprises a first pressure applicator, a first key assembly and a first connector-rod. | 04-16-2015 |
20150129044 | MECHANISMS FOR PROCESSING WAFER - Embodiments of mechanisms for processing a wafer are provided. A method for processing a wafer includes creating an exhaust flow in a fluid conduit assembly that is connected to a process module used for processing the wafer. The method also includes detecting the exhaust pressure in the fluid conduit assembly. The method further includes determining whether the exhaust pressure meets a set point. In addition, the method includes regulating the exhaust flow if the exhaust pressure fails to meet the set point. | 05-14-2015 |
20150203336 | OVERHEAD CRANE - One or more overhead cranes are provided. The overhead cranes include a first horizontal rail having a first end and a second end, a second horizontal rail having a third end and a fourth end, a first post connected to the first end of the first horizontal rail, a second post connected to the second end of the first horizontal rail, a third post connected to the third end of the second horizontal rail, a fourth post connected to the fourth end of the second horizontal rail and a cross member extending from the first horizontal rail to the second horizontal rail. The cross member includes a center span section, a first side arm and a second side arm. In some embodiments, the center span section is trapezoidialy shaped. In some embodiments, the overhead crane includes a vacuum system. | 07-23-2015 |
20150235956 | SEMICONDUCTOR DEVICE AND FORMATION THEREOF - A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate, the metal plug is over a silicide layer, and the silicide layer is over a metal oxide layer. The metal oxide layer has an oxygen gradient, such that a percentage of oxygen increases from a top surface of the metal oxide layer to a bottom surface of the metal oxide layer. The metal oxide layer unpins the Fermi level of the interface between the metal plug and the substrate, which is exhibited by a lowered Schottky barrier height (SBH) and increased oxygen vacancy states between the V.B. and the C.B. of the metal oxide layer, which decreases the intrinsic resistivity between the metal plug and the substrate as compared to a semiconductor device that lacks such a metal oxide layer. | 08-20-2015 |
Patent application number | Description | Published |
20130027232 | ANALOG-TO-DIGITAL CONVERTERS AND ANALOG-TO-DIGITAL CONVERSION METHODS - An analog-to-digital converter is provided and comprises a most significant bit (MSB) conversion module, a successive approximation register analog-to-digital converter (SAR ADC) module, and an operation module. The MSB conversion module receives an analog signal to be converted, and converts the analog signal to an MSB with M bits, and obtains a redundancy signal. The SAR ADC module is coupled to the MSB conversion module. The SAR ADC receives the redundancy signal and processes the redundancy signal to be a least significant bit (LSB) with N bits. The operation module is coupled to the MSB conversion module and the SAR ADC module. The operation module receives the MSB with the M bits and the LSB with the N bits and generates a first digital signal with (M+N) bits. Each of M and N is positive, and (M+N) is a positive integer. | 01-31-2013 |
20130033391 | MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS AND PIPELINE ANALOG-TO-DIGITAL CONVERTER USING THE SAME - A multiplying digital-to-analog converter (MDAC) is provided. The MDAC includes a sub DAC decoding circuit, a capacitor-switch circuit, and an operation amplifier circuit. The capacitor-switch circuit includes at least two sampling capacitor sets which are coupled in parallel. The number of sampling capacitors in one of the sampling capacitor sets is larger than or equal to two. Each sampling capacitor set is coupled to an analog-signal input quantity through a sampling switch and to a corresponding output terminal of the sub DAC decoding circuit through a decoding switch. The sub DAC decoding circuit decodes a digital quantity and outputs a corresponding analog signal at each output terminal, such that the corresponding analog signals are applied to the respective sampling capacitor sets through the decoding switches and summed by the respective sampling capacitor sets to obtain an analog-signal quantity corresponding to the digital quantity. | 02-07-2013 |
20130038483 | ANALOG-TO-DIGITAL CONVERTERS AND PIPELINE ANALOG-TO-DIGITAL CONVERTERS - An analog-to-digital converter is provided. The analog-to-digital converter includes a sampling-voltage providing circuit, a first comparison circuit, a second comparison circuit, and an encoder circuit. The sampling-voltage providing circuit provides a group of first comparison voltages and a group of second comparison voltages. The first comparison circuit performs a first comparison operation to an analog-signal input quantity according to the group of first comparison voltages to generate a first comparison digital quantity. The second comparison circuit selects second comparison voltages among the group of second comparison voltages according to the first comparison digital quantity and performs a second comparison operation to the analog-signal input quantity according to the selected second comparison voltages to generate a second comparison digital quantity. The encoder circuit encodes the first comparison digital quantity and the second comparison digital quantity and generates a digital quantity corresponding to the analog-signal input quantity. | 02-14-2013 |
20130076325 | VOLTAGE REGULATOR - A voltage regulator includes a pass transistor, an operational amplifier and a voltage divider circuit. The pass transistor receives a supply voltage to generate a regulated output voltage according to a control signal. The operational amplifier generates the control signal according to a feedback voltage. The voltage divider circuit generates the feedback voltage at a feedback node according to the regulated output voltage, and includes a string of resistors and a stabilization element. The string of resistors is coupled to the pass transistor and includes multiple resistors. The stabilization element is coupled to the resistors and receives the regulated output voltage. | 03-28-2013 |
20130201042 | METHOD FOR CONFIGURING ANALOG-TO-DIGITAL CONVERTER KEYS AND NON-TRANSITORY MACHINE READABLE MEDIUM STORING PROGRAM CODE EXECUTED FOR PERFORMING SUCH METHOD - A method for configuring a plurality of analog-to-digital converter (ADC) keys includes: utilizing a processor for determining a plurality of divided-voltages respectively corresponding to the Keys according to a plurality of voltage variation ranges respectively corresponding to the Keys; and calculating a plurality of resistive values of a voltage dividing model according to at least the divided-voltages, wherein the voltage dividing model has a plurality of voltage dividing configurations respectively corresponding to the keys. | 08-08-2013 |
20130293403 | ADC, IC INCLUDING THE SAME, AND ADC METHOD THEREOF - An Analog to Digital Converter (ADC), an analog-to-digital conversion method, and an integrated circuit including the ADC. The ADC includes an input adjustment buffer stage, a sub-ADC, and a sample switch. The sample switch is coupled between the output node of the input adjustment buffer stage and the input node of the sub-ADC. When the sample switch is opened, the input adjustment buffer stage is configured to switch between a first work state and a second work state according to a predetermined rule, and to adjust an input voltage signal of the input adjustment buffer stage based on transitions between the first and second work states. When the sample switch is closed, the input adjustment buffer stage is configured to provide an adjusted voltage signal to the input node of the sub-ADC, and the sub-ADC is configured to perform an analog-to-digital conversion onto the adjusted voltage signal. | 11-07-2013 |
20130314262 | SWITCH-DRIVING CIRCUIT AND DAC USING THE SAME - A switch-driving circuit and a Digital-to-Analog Converter (DAC) using the switch-driving circuit are provided. The switch-driving circuit includes a main cell and a reference cell. The main cell includes a current source and a resistance-control component electronically connected to the current source. The reference cell is coupled to the current source and the resistance-control component, and includes a first loop, the first loop is configured to track a target reference voltage so as to provide at least one first control voltage to control a resistance change of the resistance-control component. The reference cell and the main cell are implemented by MOS transistors in place of capacitors which occupy an increased circuit area, rendering reduced circuit area for the switch-driving circuit, and decreasing manufacturing costs. Further, the switch-driving circuit outputs a voltage signal with reduced noise, increasing the performance of the Digital-to-Analog Converter. | 11-28-2013 |