Patent application number | Description | Published |
20120152686 | Engagement Control Assembly for a Bi-Directional Overrunning Clutch - A bi-directional overrunning clutch differential for controlling torque transmission between a pinion input shaft and at least one output hub. The clutch having a clutch housing and the roll cage mounted within the housing. An engagement control assembly is provided for controlling the relative position of the roll cage with respect to a cam surface on the clutch housing. The engagement control assembly includes an electronically controlled actuation device, such as a coil or solenoid, which when activated causes the roll cage to rotate into a second position relative to the clutch housing to engage the rolls with the cam surface and an outer surface of the hub. A spring is engaged with the clutch housing and has an end engaged with the roll cage for biasing the roll cage into a neutral position when the roll cage is in its second position. | 06-21-2012 |
20130199886 | BI-DIRECTIONAL OVERRUNNING CLUTCH HAVING SPLIT ROLL CAGE - A bi-directional overrunning clutch includes a housing and a pair of hubs substantially coaxially aligned within the housing. A pair of roll cages position a plurality of rollers between each hub and an inner cam surface of the housing. The rollers are positioned to wedge between the hub and the inner cam surface when one of the hub and the housing is rotated with respect to the other. End caps are attached to the housing adjacent to the hubs. A friction disk mechanism includes a friction plate rotating in combination with each the roll cage and a spring compressed between the end cap and the roll cage for biasing the friction member into frictional contact with the hub. An intermittent coupler is located between each roll cage and configured to engage the roll cages so as to permit indexing of one roll cage relative to the other. | 08-08-2013 |
20140038763 | True Four Wheel Drive System for Vehicle - A drive train for a four wheel drive vehicle including a front differential engaged with a front drive shaft and front axles through a front differential gear set. The front differential includes a front bi-directional overrunning clutch that controls transmission of torque transfer between the front drive shaft and the front axles. A rear differential is engaged with rear axles and the transmission through a rear differential gear set. The rear differential includes a rear bi-directional overrunning clutch that controls torque transfer between the transmission and the rear axles. The differentials are configured with a gear ratio that is within five percent of a 1:1 gear ratio. | 02-06-2014 |
20140274530 | Bi-Directional Overrunning Clutch With Improved Indexing Mechanism - A bi-directional overrunning clutch assembly for engaging secondary driven shafts in a four wheel drive vehicle. The assembly includes a differential housing with a pinion input gear rotatably disposed within it that is engaged to a drive shaft. A bi-directional overrunning clutch housing is engaged to the pinion gear. A roll cage assembly is located inside the clutch housing. A pair of hubs are positioned within the roll cage assembly and connected to the secondary driven shafts. An electromagnetic system controls indexes the roll cage in a first direction relative to the clutch housing a first indexing device for coupling the secondary drive shaft to the secondary driven axles when four wheel drive is needed, and in an opposite direction using a second indexing device when an engine braking condition is needed. A spring assembly is preferably used to bias the roll cage back to a neutral position. | 09-18-2014 |
Patent application number | Description | Published |
20110290402 | Handler Attachment for Integrated Circuit Fabrication - A method for attaching a handler to a wafer, the wafer comprising an integrated circuit (IC), includes forming a layer of an adhesive on the wafer, the adhesive comprising a polyimide-based polymer configured to withstand processing at a temperature of over about 280° C.; and adhering a handler to the wafer using the layer of adhesive. A system for attaching a handler to a wafer, the wafer comprising IC, includes a layer of an adhesive located on the wafer, the adhesive comprising a polyimide-based polymer configured to withstand processing at a temperature of over about 280° C.; and a handler adhered to the wafer using the layer of adhesive. | 12-01-2011 |
20110290406 | Laser Ablation for Integrated Circuit Fabrication - A method for releasing a handler from a wafer, the wafer comprising an integrated circuit (IC) includes attaching the handler to the wafer using an adhesive comprising a polymer; performing edge processing to remove an excess portion of the adhesive from an edge of the handler and wafer; ablating the adhesive through the handler using a laser, wherein a wavelength of the laser is selected based on the transparency of the handler material; and separating the handler from the wafer. A system for releasing a handler from a wafer, the wafer comprising an IC includes a handler attached to a wafer using an adhesive comprising a polymer; an edge processing module, the edge processing module configured to remove an excess portion of the adhesive from the edge of the handler and wafer; and a laser, the laser configured to ablate the adhesive through the handler. | 12-01-2011 |
20110290413 | Laser Ablation of Adhesive for Integrated Circuit Fabrication - A method for releasing a handler from a wafer, the wafer comprising an integrated circuit (IC), includes attaching the handler to the wafer using an adhesive comprising a thermoset polymer, the handler comprising a material that is transparent in a wavelength range of about 193 nanometers (nm) to about 400 nm; ablating the adhesive through the handler using a laser, wherein a wavelength of the laser is selected based on the transparency of the handler material; and separating the handler from the wafer. | 12-01-2011 |
Patent application number | Description | Published |
20100276796 | REWORKABLE ELECTRONIC DEVICE ASSEMBLY AND METHOD - An electronic device assembly is provided which includes a substrate, an interposer and an integrated circuit chip. The substrate is fabricated of a first material having a first thermal expansivity, and the interposer and integrated circuit chip are fabricated of a second material having a second thermal expansivity. The second thermal expansivity is different from the first thermal expansivity so that there is a coefficient of thermal expansion mismatch between the substrate and the interposer or chip. The interposer is coupled to the substrate via a first plurality of electrical contacts and an underfill adhesive at least partially surrounding the electrical contacts to bond the interposer to the substrate and thereby reduce strain on the first plurality of electrical contacts. The integrated circuit chip is coupled to the interposer via a second plurality of electrical contacts only, without use of an adhesive surrounding the second plurality of electrical contacts. | 11-04-2010 |
20110042795 | Three-Dimensional Silicon Interposer for Low Voltage Low Power Systems - Scalable silicon (Si) interposer configurations that support low voltage, low power operations are provided. In one aspect, a Si interposer is provided which includes a plurality of through-silicon vias (TSVs) within a first plane thereof adapted to serve as power, ground and signal interconnections throughout the first plane such that the TSVs that serve as the power and ground interconnections are greater in number and/or size than the TSVs that serve as the signal interconnections; and a plurality of lines within a second plane of the interposer in contact with one or more of the TSVs in the first plane, the second plane being adjacent to the first plane, adapted to serve as power, ground and signal interconnections throughout the second plane such that the lines that serve as the power and the ground interconnections are greater in number and/or size than the lines that serve as the signal interconnections. | 02-24-2011 |
20140103499 | ADVANCED HANDLER WAFER BONDING AND DEBONDING - A method for processing a semiconductor wafer includes applying a release layer to a transparent handler. An adhesive layer, that is distinct from the release layer, is applied between a semiconductor wafer and the transparent handler having the release layer applied thereon. The semiconductor wafer is bonded to the transparent handler using the adhesive layer. The semiconductor wafer is processed while it is bonded to the transparent handler. The release layer is ablated by irradiating the release layer through the transparent handler with a laser. The semiconductor wafer is removed from the transparent handler. | 04-17-2014 |
20140106473 | ADVANCED HANDLER WAFER BONDING AND DEBONDING - A method for processing a semiconductor wafer includes applying a release layer to a transparent handler. An adhesive layer, that is distinct from the release layer, is applied between a semiconductor wafer and the transparent handler having the release layer applied thereon. The semiconductor wafer is bonded to the transparent handler using the adhesive layer. The semiconductor wafer is processed while it is bonded to the transparent handler. The release layer is ablated by irradiating the release layer through the transparent handler with a laser. The semiconductor wafer is removed from the transparent handler. | 04-17-2014 |
20150035173 | ADHESIVES FOR BONDING HANDLER WAFERS TO DEVICE WAFERS AND ENABLING MID-WAVELENGTH INFRARED LASER ABLATION RELEASE - Methods are provided to form adhesive materials that are used to temporarily bond handler wafers to device wafers, and which enable mid-wavelength infrared laser ablation release techniques to release handler wafers from device wafers. | 02-05-2015 |
20150035554 | WAFER DEBONDING USING MID-WAVELENGTH INFRARED RADIATION ABLATION - Structures and methods are provided for temporarily bonding handler wafers to device wafers using bonding structures that include one or more releasable layers which are laser-ablatable using mid-wavelength infrared radiation | 02-05-2015 |
Patent application number | Description | Published |
20090020590 | PROCESS FOR MAKING INTERCONNECT SOLDER Pb-FREE BUMPS FREE FROM ORGANO-TIN/TIN DEPOSITS ON THE WAFER SURFACE - A method is provided for making of interconnect solder bumps on a wafer or other electronic device without depositing any significant amount of tin or other solder component from the solder onto the wafer surface which tin can cause shorts or other defects in the wafer. The method is particularly useful for well-known C4NP interconnect technology. In one aspect of the invention, a reducing gas flow rate is used to remove oxides from the solder surfaces and wafer pad surfaces and is of a sufficient determined or pre-determined flow and/or chamber or mold/wafer spacing to provide a gas velocity across the solder surfaces and wafer pad surfaces so that Sn or other contaminants do not deposit on the wafer surface during solder transfer. In another aspect, the transfer contact is performed below the melting point of the solder and subsequently heated to above the melting temperature while in transfer contact. The heated solder in contact with the wafer pads is transferred to the wafer pads. | 01-22-2009 |
20090163019 | FORMING ROBUST SOLDER INTERCONNECT STRUCTURES BY REDUCING EFFECTS OF SEED LAYER UNDERETCHING - A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening of a first diameter, and a solder material is formed over the barrier layer using a second patterned opening of a second diameter. The second patterned opening is configured such that the second diameter is larger than the first diameter. | 06-25-2009 |
20110079702 | FORMING A PROTECTIVE LAYER ON A MOLD AND MOLD HAVING A PROTECTIVE LAYER - A method of forming a mold having a protective layer includes forming a mold substrate having at least one substantially planar surface, depositing a layer of mold protection material onto the at least one substantially planar surface, and etching a plurality of cavities into the at least one substantially planar surface through the mold protection layer. | 04-07-2011 |
20120193014 | REDUCTION OF EDGE CHIPPING DURING WAFER HANDLING - Methods and systems for reinforcing the periphery of a semiconductor wafer bonded to a carrier are disclosed. In one embodiment, additional adhesive is applied to the semiconductor wafer prior to bonding. The additional adhesive seeps into a crevice between the carrier and wafer and provides reinforcement. In another embodiment, adhesive is applied to the crevice by a dispenser after the wafer is bonded to the glass carrier. | 08-02-2012 |
20120207920 | PROTECTING A MOLD HAVING A SUBSTANTIALLY PLANAR SURFACE PROVIDED WITH A PLURALITY OF MOLD CAVITIES - A method of protecting a mold having at least one substantially planar surface provided with a plurality of mold cavities includes inserting a plurality of mandrels into respective ones of the plurality of mold cavities, depositing a layer of mold protection material onto the at least one substantially planar surface and the plurality of mandrels, and removing the plurality of mandrels from the mold substrate. | 08-16-2012 |
20130160705 | REDUCTION OF EDGE CHIPPING DURING WAFER HANDLING - Methods and systems for reinforcing the periphery of a semiconductor wafer bonded to a carrier are disclosed. In one embodiment, additional adhesive is applied to the semiconductor wafer prior to bonding. The additional adhesive seeps into a crevice between the carrier and wafer and provides reinforcement. In another embodiment, adhesive is applied to the crevice by a dispenser after the wafer is bonded to the glass carrier. | 06-27-2013 |
20130164912 | REDUCTION OF EDGE CHIPPING DURING WAFER HANDLING - Methods and systems for reinforcing the periphery of a semiconductor wafer bonded to a carrier are disclosed. In one embodiment, additional adhesive is applied to the semiconductor wafer prior to bonding. The additional adhesive seeps into a crevice between the carrier and wafer and provides reinforcement. In another embodiment, adhesive is applied to the crevice by a dispenser after the wafer is bonded to the glass carrier. | 06-27-2013 |
20140192341 | FIXTURE PLANARITY EVALUATION METHOD - Methods for determining the planarity of two components of a semiconductor processing tool, such as a 3D wafer bonder are disclosed. The two components may be fixtures, chucks, or platens of the tool. A test wafer comprising multiple solder balls is compressed and the deformity of multiple solder balls is measured to assess the planarity of the tool. The measurement of the deformed solder balls may be performed manually, or with an automated wafer inspection tool, which may use lasers to measure the height of each solder ball. The planarity of the two components is computed based on the height of the deformed solder balls. | 07-10-2014 |