Chung-Chi
Chung-Chi Chang, Taipei City TW
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20100006886 | HIGH POWER LIGHT EMITTING DIODE CHIP PACKAGE CARRIER STRUCTURE - A high power LED (light-emitting diode) chip package carrier structure is disclosed and comprises a circuit board, a metal plate and a lid. The circuit board has a perforate groove for positioning a chip, and an electrode contact area formed at two sides or border of the perforate groove. The metal plate is positioned beneath the circuit board. The lid is positioned above the circuit board, and has a through groove with a width larger than the width of the perforate groove of the circuit board such that the electrode contact area can be exposed out in the through groove of the lid. Thus, the manufacturing process can be simplified and helpful to the mass production. | 01-14-2010 |
20100096642 | PACKAGING STRUTURE FOR HIGH POWER LIGHT EMITTING DIODE(LED) CHIP - The present invention relates to a packaging structure for high-power light emitting diode (LED) chip, comprising a metal plate, insulators and a cover plate. The metal plate comprises a containing slot and isolating slots formed on the surface by working, and the insulators can be embedded in the isolating slot. After forming a hollow slot and notches on the surface of the cover plate by working, the cover plate is combined with the metal plate and insulators and at the same time, the hollow slot and the notches are corresponding to the containing slot and the isolating slots on the metal plate to form a hollowness state, followed by application of surface treatment to form soldering portions and an anti-soldering layer at the bottom of the metal plate. Then the metal plate is cut on both sides along free ends of the insulators so as to generate electrode contacts with positive and negative electrodes, and the surface mount technology (SMT) can be adopted for assembly of the packaging structure of high-power LED chip so as to simplify manufacturing processes, facilitate mass production and achieve separation of electricity from heat, etc. | 04-22-2010 |
Chung-Chi Chang, Taipei TW
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20140101704 | CHANNELIZATION METHOD OF DIGITAL CONTENT AND AUDIO-VIDEO SERVER SYSTEM - A channelization method of digital content and an audio-video server system are provided. A received operational behavior is packaged as an execution module, and the execution module is associated with a channel number. A correlation between the channel number and the execution module is recorded in a local channel list. Accordingly, when a switch command that contains the channel number is received, the execution module corresponding to the channel number is obtained from the local channel list, so as to perform the operational behavior to use the digital content. | 04-10-2014 |
20160112766 | AUDIO-VIDEO SERVER SYSTEM - A channelization method of digital content and an audio-video server system are provided. A received operational behavior is packaged as an execution module, and the execution module is associated with a channel number. A correlation between the channel number and the execution module is recorded in a local channel list. Accordingly, when a switch command that contains the channel number is received, the execution module corresponding to the channel number is obtained from the local channel list, so as to perform the operational behavior to use the digital content. | 04-21-2016 |
Chung-Chi Chen, Shuilin Shiang TW
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20100130379 | Weighted Chemiluminescent Chip array Method for Multiple Marker Detection - A gene chip for chemiluminescent detection is obtained. The chip uses multiple markers. Weighted scores are given to genes separately according to their influences on forming a cancer. The present invention provides an objective and accurate disease assistant diagnosis with a low cost, a high sensitivity and a good performance. The present invention can be widely applied to personal medical behaviors, like clinical diagnosis, treatment filtration, prognosis review, preventive medicine, etc. | 05-27-2010 |
Chung-Chi Chen, Hsinchu TW
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20110204514 | PACKAGE DEVICE AND FABRICATION METHOD THEREOF - A package device and a fabrication method thereof comprises providing a plurality of package units each having a plurality of penetrated holes; stacking the plurality of package units in a manner such that the penetrated holes of the plurality of package units are aligned; filling a conductive material into the plurality of penetrated holes substantially, so as to electrically connect the plurality of package units through the conductive material; and disposing a plurality of solder balls on the bottom of the conductive material filling the plurality of penetrated holes, and connecting the plurality of solder balls with the conductive material electrically. | 08-25-2011 |
Chung-Chi Chiang, Miaoli City TW
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20140293586 | Detachable Essential Oil Ring for Lamp and Application Thereof - A detachable essential oil ring for lamp is an open-loop ring and is detachably mounted on the lamp easily. A part of the detachable essential oil ring is used to absorb or contain essential oils and directly contacts a heated portion of the lamp. The detachable essential oil ring contacts the heated portion to auxiliary vaporize the fragrance oils or the essential oils. The structure of the detachable essential oil ring is simple and is easy to manufacture. The detachable essential oil ring can be mounted on the lamp with different types and can auxiliary vaporizes the fragrance oils or the essential oils by the heat generated from the lamp during light, and this is lower cost and environmental friendly. | 10-02-2014 |
Chung-Chi Hsu, Zhunan Town TW
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20160090638 | METHODS OF PROGNOSTICALLY CLASSIFYING AND TREATING GLANDULAR CANCERS - This disclosure includes the identification of molecular markers, including ASPM, ATP9A, ACOX3, CD-C45L, SLC40A1, AGR2, and those found in TABLE 2, that are associated with the differentiation and the clinical prognosis of pancreatic cancer. More specifically, the disclosure includes the identification of sets of gene markers whose expression levels can be used to distinguish pancreatic cancers with higher degrees of differentiation from those with lower degrees of differentiation. These markers can be used to predict clinical prognosis of pancreatic cancer, including disease progression, recurrence or death of the hosts. The disclosure also provides methods of treating glandular cancers and kits for assaying glandular cancers, such as pancreatic cancer, breast cancer, and prostate cancer, by inhibiting the expression of ASPM or its ability to activate or maintain the Wnt signaling activity and/or the cancer stem cell populations of said glandular cancers. | 03-31-2016 |
Chung-Chi Huang, Taipei City TW
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20120037155 | Novel Auxiliary Chamber for Inhaled-Drugs - An auxiliary chamber for inhaled-drugs includes a hollow tube body and a hollow side tube; and a unidirectional air valve which only allows air from an inlet flowing to an outlet end is located at the inlet end of the hollow tube body, wherein the outlet end of the hollow tube body is connected to an endotracheal tube. The hollow side tube connects with a lateral hole of the hollow tube body at one end, and a special universal adapter at the other end. The special universal adapter has a small through hole which is used to accommodate an inhaler therein to release inhaled drugs in the inhaler into the hollow tube body, and the inhaled drugs moves from the inlet end with air flow to the outlet end after entering the hollow tube body to help patients with respiratory failure take medicine. | 02-16-2012 |
Chung-Chi Huang, Hillsboro, OR US
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20080238584 | Reducing crosstalk in electronic devices having microstrip lines - An electronic device may be formed of a printed circuit board having integrated circuits mounted thereon. A backing plate may compress an insulating layer against a microstrip line formed on one surface of said circuit board opposite to the surface that includes integrated circuits. By compressing said backing plate against said insulating layer, less crosstalk may result from the formation of a microstrip on the bottom surface of the printed circuit board. The backing plate may also be used to secure a cooling device, such as a heat sink, on the opposite side of the circuit board. | 10-02-2008 |
20090110042 | Determining a bit error rate (BER) using interpolation and superposition - In one embodiment, the present invention includes a method for receiving a jitter profile and a step response of a channel coupled between a transmitter and a receiver and a bit pattern to be transmitted, transmitting the bit pattern along the channel from the transmitter to the receiver with the jitter profile and the step response, receiving the bit pattern at the receiver and converting the bit pattern to a data stream by interpolating the step response according to a jitter of a current bit to obtain a jittery step response, superposing the jittery step response onto the data stream, calculating the jitter at each transition bit of the bit pattern by determining a time difference between actual and ideal crossing points, incrementing a jitter distribution function with the jitter, and generating a timing curve for the channel using the jitter distribution function. Other embodiments are described and claimed. | 04-30-2009 |
Chung-Chi Huang, Taoyuan County TW
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20150289377 | MANUFACTURING METHOD OF CONNECTOR - The instant disclosure relates to a manufacturing method of connector which comprises the following steps. The first step is to provide a substrate layer and forming a first metal layer on the substrate layer. The next step is to pattern the first metal layer to form a wiring layer. The next step is to form a dielectric layer on the wiring layer, wherein the dielectric layer is formed with at least one via hole to partially expose the wiring layer and a conductive structure arranged on the inner wall of the at least one via hole and electrically connected to the wiring layer. The next step is to form a first protective layer on the dielectric layer and at least one cantilever structure between the first protective layer and the dielectric layer. The last step is to remove the substrate layer. | 10-08-2015 |
Chung-Chi Huang, Taoyuan City TW
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20150289374 | CONNECTOR - The instant disclosure relates to a connector including a wiring layer, a dielectric layer, a conductive structure, a first protective layer and at least one cantilever structure. The dielectric layer is disposed on the wiring layer, wherein the dielectric layer has at least one via hole to partially expose the wiring layer. The conductive structure is disposed on the inner wall of the at least one via hole of the dielectric layer and electrically connected to the wiring layer. The first protective layer is disposed on the dielectric layer. The cantilever structure is disposed between the first protective layer and the dielectric layer, wherein the at least one cantilever structure is electrically connected to the wiring layer via the conductive structure. | 10-08-2015 |
Chung-Chi Ko, Nantou TW
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20080233765 | Method for enhancing adhesion between layers - A novel method for enhancing interface adhesion between adjacent dielectric layers, particularly between an etch stop layer and an overlying dielectric layer having a low dielectric constant (k) in the formation of metal interconnects during the fabrication of integrated circuits on semiconductor wafer substrates. The method may include providing a substrate, providing an etch stop layer on the substrate, providing an oxygen-rich dielectric pre-layer on the etch stop layer and providing a major dielectric layer on the oxygen-rich dielectric pre-layer. Metal interconnects are then formed in the dielectric layers. The oxygen-rich dielectric pre-layer between the etch stop layer and the upper dielectric layer prevents or minimizes peeling and cracking of the layers induced by stresses that are caused by chemical mechanical planarization of metal layers and/or chip packaging. | 09-25-2008 |
20080272493 | Semiconductor device - A semiconductor device is disclosed. The device includes a substrate, a first porous SiCOH dielectric layer, a second porous SiCOH dielectric layer, and an oxide layer. The first porous SiCOH dielectric layer overlies the substrate. The second porous SiCOH dielectric layer overlies the first porous SiCOH dielectric layer. The oxide layer overlies the second porous SiCOH dielectric layer. The atomic percentage of carbon in the second porous SiCOH dielectric layer is between 16% and 22% of that in the first porous SiCOH dielectric layer. | 11-06-2008 |
20090258487 | Method for Improving the Reliability of Low-k Dielectric Materials - A method for forming an integrated circuit structure includes providing a semiconductor substrate; forming a low-k dielectric layer over the semiconductor substrate; generating hydrogen radicals using a remote plasma method; performing a first hydrogen radical treatment to the low-k dielectric layer using the hydrogen radicals; forming an opening in the low-k dielectric layer; filling the opening with a conductive material; and performing a planarization to remove excess conductive material on the low-k dielectric layer. | 10-15-2009 |
20100120253 | Post Etch Dielectric Film Re-Capping Layer - Methods for improving post etch in via or trench formation in semiconductor devices. A preferred embodiment comprises forming a re-capping layer over a dielectric film following an initial etch to form a feature in the dielectric film, followed by additional etch and etch back processing steps. The re-capping method provides protection for underlying films and prevents film damage post etch. Uniform feature profiles are maintained and critical dimension uniformity is obtained by use of the methods of the invention. The time dependent dielectric breakdown performance is increased. | 05-13-2010 |
20100213518 | Impurity Doped UV Protection Layer - An ultra-violet (UV) protection layer is formed over a semiconductor workpiece before depositing a UV curable dielectric layer. The UV protection layer prevents UV light from reaching and damaging underlying material layers and electrical devices. The UV protection layer comprises a layer of silicon doped with an impurity, wherein the impurity comprises O, C, H, N, or combinations thereof. The UV protection layer may comprise SiOC:H, SiON, SiN, SiCO:H, combinations thereof, or multiple layers thereof, as examples. | 08-26-2010 |
20110195576 | DOUBLE PATTERNING STRATEGY FOR CONTACT HOLE AND TRENCH IN PHOTOLITHOGRAPHY - A method of lithography patterning includes forming a first etch stop layer, a second etch stop layer, and a hard mask layer on a material layer. The materials of the first etch stop layer and the second etch stop layer are selected by the way that there is a material gradient composition between the second etch stop layer, the first etch stop layer, and the material layer. Hence, gradient etching rates between the second etch stop layer, the first etch stop layer, and the material layer are achieved in an etching process to form etched patterns with smooth and/or vertical sidewalls within the second and the first etch stop layers and the material layer. | 08-11-2011 |
20110207329 | DOUBLE PATTERNING STRATEGY FOR CONTACT HOLE AND TRENCH IN PHOTOLITHOGRAPHY - A method of lithography patterning includes forming a mask layer on a material layer and forming a capping layer on the mask layer. The capping layer is a boron-containing layer with a higher resistance to an etching reaction of patterning process of the material layer. By adapting the boron-containing layer as the capping layer, the thickness of the mask layer can be thus reduced. Hence, a better gap filling for forming an interconnect metallization in the material layer could be achieved as well. | 08-25-2011 |
20110217840 | Method for Forming Self-Assembled Mono-Layer Liner for Cu/Porous Low-k Interconnections - A method for fabricating an integrated circuit comprises forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, and treating the low-k dielectric layer with a gaseous organic chemical to cause a reaction between the low-k dielectric layer and the gaseous organic chemical. The gaseous organic chemical is free from silicon. | 09-08-2011 |
20110223759 | Low-k Cu Barriers in Damascene Interconnect Structures - In the formation of an interconnect structure, a metal feature is formed in a dielectric layer. An etch stop layer (ESL) is formed over the metal feature and the dielectric layer using a precursor and a carbon-source gas including carbon as precursors. The carbon-source gas is free from carbon dioxide (CO | 09-15-2011 |
20110256715 | BARRIER LAYER FOR COPPER INTERCONNECT - A copper interconnect includes a copper layer formed in a dielectric layer. A liner is formed between the copper layer and the dielectric layer. A barrier layer is formed at the boundary between the liner and the dielectric layer. The barrier layer is a metal oxide. | 10-20-2011 |
20120077339 | METHOD OF AND APPARATUS FOR ACTIVE ENERGY ASSIST BAKING - A method of and apparatus for forming interconnects on a substrate includes etching patterns in ultra-low k dielectric and removing moisture from the ultra-low k dielectric using active energy assist baking. During active energy assist baking, the ultra-low k dielectric is heated and exposed to light having only wavelengths greater than 400 nm for about 1 to about 20 minutes at a temperature of about 300 to about 400 degrees Celsius. The active energy assist baking is performed after wet-cleaning or after chemical mechanical polishing, or both. | 03-29-2012 |
20130052755 | Automatically adjusting baking process for low-k dielectric material - A method includes etching a low-k dielectric layer on a wafer to form an opening in the low-k dielectric layer. An amount of a detrimental substance in the wafer is measured to obtain a measurement result. Process conditions for baking the wafer are determined in response to the measurement result. The wafer is baked using the determined process conditions. | 02-28-2013 |
20130052818 | Methods for Forming Interconnect Structures of Integrated Circuits - A method includes forming a hard mask over a low-k dielectric layer, and patterning the hard mask to form an opening. A stress tuning layer is formed over the low-k dielectric layer and in physical contact with the hard mask. The stress tuning layer has an inherent stress, wherein the inherent stress is a near-zero stress or a tensile stress. The low-k dielectric layer is etched to form a trench aligned to the opening, wherein the step of etching is performed using the hard mask as an etching mask. | 02-28-2013 |
20130062774 | Semiconductor Device and Method for Forming the Same - A method includes forming a metal hard mask over a low-k dielectric layer. The step of forming the metal hard mask includes depositing a sub-layer of the metal hard mask, and performing a plasma treatment on the sub-layer of the metal hard mask. The metal hard mask is patterned to form an opening. The low-k dielectric layer is etched to form a trench, wherein the step of etching is performed using the metal hard mask as an etching mask. | 03-14-2013 |
20130137261 | METHOD OF MODIFYING A LOW K DIELECTRIC LAYER HAVING ETCHED FEATURES AND THE RESULTING PRODUCT - A dielectric layer having features etched thereon and a low dielectric constant, and that is carried by a semiconductor substrate. The etched dielectric layer is modified so its surface energy is reduced by at least one of: (a) applying thermal energy to the layer to cause the layer temperature to be between 100 C and 400 C; (b) irradiating the layer with electromagnetic energy; and/or (c) irradiating the layer with free ions. | 05-30-2013 |
20130273732 | METHOD OF AND APPARATUS FOR ACTIVE ENERGY ASSIST BAKING - An Active Energy Assist (AEA) baking chamber includes an AEA light source assembly and a heater pedestal. The AEA baking chamber further includes a controller for controlling a power input to the AEA light source assembly and a power input to the heater pedestal. A method of forming interconnects on a substrate includes etching a substrate and wet cleaning the etched substrate. The method further includes active energy assist (AEA) baking the substrate after the wet-cleaning. The AEA baking includes placing the substrate on a heater pedestal in an AEA chamber, exposing the substrate to light having a wavelength equal to or greater than 400 nm, wherein said light is emitted by a light source and controlling the light source and the heater pedestal using a controller. | 10-17-2013 |
20130337651 | Double Patterning Strategy for Contact Hole and Trench in Photolithography - A method of lithography patterning includes forming a first etch stop layer, a second etch stop layer, and a hard mask layer on a material layer. The materials of the first etch stop layer and the second etch stop layer are selected by the way that there is a material gradient composition between the second etch stop layer, the first etch stop layer, and the material layer. Hence, gradient etching rates between the second etch stop layer, the first etch stop layer, and the material layer are achieved in an etching process to form etched patterns with smooth and/or vertical sidewalls within the second and the first etch stop layers and the material layer. | 12-19-2013 |
20140264923 | INTERCONNECT STRUCTURE WITH KINKED PROFILE - Among other things, one or more interconnect structures and techniques for forming such interconnect structures within integrated circuits are provided. An interconnect structure comprises one or more kinked structures, such as metal structures or via structures, formed according to a kinked profile. For example, the interconnect structure comprises a first kinked structure having a first tapered portion and a second kinked structure having a second tapered portion. The first tapered portion and the second tapered portion are both situated at an interface between two layers. Current leakage at the interface is mitigated because a length of the interface corresponds to a distance between the first tapered portion and the second tapered portion that is relatively larger than if the first kinked structure and the second kinked structure were merely formed according to a non-tapered shape. | 09-18-2014 |
20150054170 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes conductive features disposed over a workpiece, each conductive feature including a conductive line portion and a via portion. A barrier layer is disposed on sidewalls of each conductive feature and on a bottom surface of the via portion of each conductive feature. The barrier layer includes a dielectric layer. A first insulating material layer is disposed beneath a portion of the conductive line portion of each conductive feature. A second insulating material layer is disposed between the conductive features. A third insulating material layer is disposed beneath the first insulating material layer and the second insulating material layer. A lower portion of the via portion of each of the conductive features is formed within the third insulating material layer. The second insulating material layer has a lower dielectric constant than a dielectric constant of the first insulating material layer and a dielectric constant of the third insulating material layer. | 02-26-2015 |
20150091172 | PORE SEALING TECHNIQUES FOR POROUS LOW-K DIELECTRIC INTERCONNECT - The present disclosure relates to a method of forming pore sealing layer for porous low-k dielectric interconnects. The method is performed by removing hard mask layer before pore sealing and/or applying pore sealing layer before etching etch stop layer (ESL). These methods at least have advantages that aspect ratio is improved, line distortion introduced by the hard mask layer is avoided, and critical dimension is less affected by pore sealing layer. | 04-02-2015 |
20150104953 | HIGH UV CURING EFFICIENCY FOR LOW-K DIELECTRICS - One embodiment is a method for semiconductor processing. In this method, a precursor film is provided over a semiconductor substrate, where the precursor film is made of a structural former and porogen. Prior to cross-linking, the porogen is removed by exposure to UV radiation having one or more wavelengths in the range of 150 nm to 300 nm, while a temperature of 300° C. to 500° C. is applied to the semiconductor substrate. Meanwhile, a Argon:Helium flow rate of 80>Ar>10 slm, 80>He>10 slm is set for the ambient substrate environment where the ratio of Ar:He ranges from 0:1 to 1:0 by volume or molality. | 04-16-2015 |
20150187697 | Interconnect Structure for Semiconductor Devices - An interconnect and a method of forming an interconnect for a semiconductor device is provided. The interconnect is formed by treating an upper surface of a dielectric layer to create a high density layer. The treatment may include, for example, creating a high density monolayer using hexamethyldisilazane (HMDS), trimethylsilydiethylamine (TMSDEA) or trimethylsilylacetate (OTMSA). After treating, the dielectric layer may be patterned to create openings, which are subsequently filled with a conductive material. Excess conductive material may be removed using, for example, a chemical mechanical polishing. | 07-02-2015 |
20150194343 | SELF-ALIGNED REPAIRING PROCESS FOR BARRIER LAYER - A self-aligned repairing process for a barrier layer is provided. A repair layer is formed by chemical vapor deposition using an organometallic compound as a precursor gas. The precursor gas adsorbed on a dielectric layer exposed by defects in a barrier layer is transformed to an insulating metal oxide layer, and the precursor gas adsorbed on the barrier layer is transformed to a metal layer. | 07-09-2015 |
Chung-Chi Ko, Nautou TW
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20090286394 | Method for Forming Self-Assembled Mono-Layer Liner for Cu/Porous Low-k Interconnections - A method for fabricating an integrated circuit comprises forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, and treating the low-k dielectric layer with a gaseous organic chemical to cause a reaction between the low-k dielectric layer and the gaseous organic chemical. The gaseous organic chemical is free from silicon. | 11-19-2009 |
Chung-Chi Ko, Jushan Jen TW
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20150200133 | METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE - Embodiments of the disclosure provide a method for forming a semiconductor device structure. The method includes forming a dielectric layer over a semiconductor substrate. The method also includes applying a carbon-containing material over the dielectric layer. The method further includes irradiating the dielectric layer and the carbon-containing material with a light to repair the dielectric layer, and the light has a wavelength greater than about 450 nm. | 07-16-2015 |
Chung-Chi Ko, Jushan Township TW
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20150201501 | Selective Repairing Process For Barrier Layer - A selectively repairing process for a barrier layer is provided. A repair layer is formed by chemical vapor deposition using an organosilicon compound as a precursor gas. The precursor gas adsorbed on a low-k dielectric layer exposed by defects in a barrier layer is transformed to a porous silicon oxide layer has a density more than the density of the low-k dielectric layer. | 07-16-2015 |
Chung-Chi Ko, Hsin-Chu TW
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20160086865 | Automatically Adjusting Baking Process for Low-k Dielectric Material - A method includes etching a low-k dielectric layer on a wafer to form an opening in the low-k dielectric layer. An amount of a detrimental substance in the wafer is measured to obtain a measurement result. Process conditions for baking the wafer are determined in response to the measurement result. The wafer is baked using the determined process conditions. | 03-24-2016 |
Chung-Chi Lee, Chung-He City TW
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20080255189 | HEPATITIS C VIRUS INHIBITORS - A compound of the following formula: | 10-16-2008 |
20080306090 | THIOUREA DERIVATIVES - Thiourea compounds of the following formula: | 12-11-2008 |
20090176766 | IMIDAZOLIDINONE AND IMIDAZOLIDINETHIONE DERIVATIVES - Imidazolidinone and imidazolinethione compounds of formula (I): | 07-09-2009 |
Chung-Chi Lin, Taichung City TW
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20130315387 | ENCRYPTION METHOD CHARACTERIZED BY THREE DIMENSIONAL COMPUTATION, FEEDBACK CONTROL, AND DYNAMIC TRANSITION BOX - An encryption method adopts an encryption principle based on sequential logic and involves performing three dimensional computation on a plaintext data unit having undergone non-linear transition through a dynamic child transition box, system keys, and dynamic feedback keys together to generate dynamic keys. After undergoing non-linear transition through different dynamic child transition boxes respectively, the dynamic keys undergo the three dimensional computation together with the system keys to generate a ciphertext data unit. Content values of the dynamic feedback keys and dynamic child transition box operating under a feedback control mechanism vary with each instance of feedback, and thus the dynamic keys and the ciphertext data are difficult to crack but effective in resisting violent attacks. | 11-28-2013 |
Chung-Chi Lin, Taipei TW
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20080265113 | DISPLAY DEVICE - A display device includes a display panel having a back cover, a body, a supporting plate and an adjusting mechanism. The adjusting mechanism includes a sliding rail support, a sliding block, a gear and a rotating member. The sliding rail support is fixedly connected to the back cover, and has a guiding structure disposed along the sliding rail support. The sliding block is slidably provided at the sliding rail support to move along thereof. The gear is connected to the sliding block. The gear and the guiding structure are clenched to position the sliding block at the sliding rail support. The rotating member has a first connecting portion and a second connecting portion. The first connecting portion is fixedly connected to the supporting plate, and the second connecting portion is pivotally connected to the sliding block, thereby adjusting the relative angle between the supporting plate and the sliding block. | 10-30-2008 |
Chung-Chi Liu, Shenzhen CN
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20140071670 | LED LAMP CAPABLE OF INCREASING LIGHT SATURATION - An LED lamp capable of increasing light saturation utilizes a mixing layer to be formed on a reflecting layer since the mixing layer is arranged by multiple dots that are distributed at intervals and formed as a dot-matrix layer. At least one color formed on the dots to present the colored dot-matrix display allows the light beams from the LED lamp to be mixed with the color on the dot-matrix layer and then reflected for promoting the color temperature uniformity of the light beams and decreasing the generation of dark zone, which efficiently provides light beams with a uniform saturation for illuminating. | 03-13-2014 |
Chung-Chi Liu, Taipei City TW
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20150131277 | LED TUBE - An LED tube comprises a glass tube, a PCB disposed in the glass tube, a heat-dissipating colloid disposed in the glass tube, a plurality of LED lights disposed on the PCB, and two electrode caps respectively connected to both ends of the glass tube. By densely filling a room between a peripheral wall of the glass tube and a top surface of the PCB with the heat-dissipating colloid, an exhaust heat caused by illuminating the LED lights and a high temperature generated from the PCB are absorbed and dissipated out of the tube, thereby constructing a connective dissipating concatenation of heat conduction. A heat-disipating unit can be preferably disposed at an exterior periphery of the tube to obtain a quick and multiple heat-dissipating effect and decrease the temperature in the glass tube, thereby facilitating the illuminating efficiency and increasing the duration of the LED tube. | 05-14-2015 |
Chung-Chi Wang, Hsinchu County TW
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20150029415 | TOUCH PANEL STRUCTURE, METHOD FOR FORMING THE SAME AND TOUCH DEVICE HAVING THE SAME - The present invention discloses a touch panel structure, a method for forming the same and a touch device having the same. A touch panel structure of the present invention comprises a substrate, a color layer, an inorganic layer, and a photoresist layer. The color layer is disposed on a surface of the substrate. The inorganic layer is disposed on a surface of the color layer which is opposite to the substrate. The photoresist layer is disposed on a surface of the inorganic layer which is opposite to the substrate, wherein the color layer and the photoresist layer have different surface tensions. For electronic products that rely on the Colorful OGS (One Glass Solution) technology, by providing an inorganic layer between the color layer and the photoresist layer, problems related to different surface tensions when the layers are stacked during the manufacturing process of a touch panel can be solved. | 01-29-2015 |
20150044432 | TOUCH PANEL STRUCTURE AND METHOD FOR FORMING THE SAME - The present invention discloses a touch panel structure and a method for forming the same. A touch panel structure according to the present invention comprises a substrate, a first color layer, a second color layer, and an indium tin oxide (ITO) conductive layer. The first color layer is disposed on a surface of the substrate. The second color layer is disposed on a surface of the first color layer which is opposite to the substrate, and a portion of the second color layer extends further to be in contact with the substrate. The ITO conductive layer is disposed on a surface of the second color layer which is opposite to the first color layer and also disposed on the surface of the substrate. With the touch panel structure of the present invention, the conductive layer will not break easily, and the yield rates for touch panels will be improved. | 02-12-2015 |
Chung-Chi Wang, Taipei TW
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20110157583 | METHOD OF CALIBRATING SENSITIVITY GAIN - The present invention is directed to a method of calibrating sensitivity gain. In a preview mode, an imaging device is calibrated by a standard light source, therefore obtaining standard sensitivity gain of the preview mode. In a capture mode, the imaging device is calibrated by the standard light source, therefore obtaining standard sensitivity gain of the capture mode. A gain ratio of the standard sensitivity gain of the capture mode to the standard sensitivity gain of the preview mode is determined, and is then used to deduce the exposure parameters of the capture mode according to the exposure parameters of the preview mode. | 06-30-2011 |
Chung-Chi Yang, Taipei TW
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20140288325 | METHOD FOR PRODUCING DI(2-ETHYLYHEXYL) TEREPHTHALATE - Disclosed is a method for producing di(2-ethylhexyl)terephthalate (DOTP), which comprises subjecting terephthalic acid and 2-ethylhexanol to esterification in the presence of a chelate catalyst. The method of the present invention increases the reaction rate, improves the filtration efficiency of the ester product and yields DOTP with low APHA. | 09-25-2014 |