Patent application number | Description | Published |
20090274063 | MULTI-LEVEL INTERCONNECTION NETWORK - A method and system for providing a multi-level interconnection network is provided. A multi-level interconnection network comprises basic cells that are aggregated into higher level cells at each level of the network. At the first level, the basic cells are aggregated into first level cells. Each first level cell is an aggregation of a number of basic cells that is one more than the number of devices in a basic cell. The basic cells of a first level cell are fully connected; that is, each basic cell has a first level link or connection to each other basic cell. In a first level cell, each device of a basic cell has a first level link to each other basic cell. The multi-level interconnection network has higher level cells that are aggregations of lower level cells in a similar manner. | 11-05-2009 |
20090325690 | Roaming Saved Game - Various systems and methods are disclosed for a roaming saved game function allowing for location independent access to saved game data. In various embodiments, users may upload saved games when they sign in to an online gaming service, and download them later from another console, PC or other device so that they can continue a saved game wherever they have access to the online gaming service. In one embodiment, users may manage saved game files after signing in to the online gaming service. In other embodiments, the roaming saved game function may provide users with ease of managing their saved games. For example, users may be able to compare two saved games by comparing their level, checkpoint number and screenshot listing. The user may then select one of the saved game files to play and upload. | 12-31-2009 |
20090325709 | Game Clan Matchmaking - Various systems, methods, and computer readable instructions are disclosed herein for a video game clan matchmaking service. In an embodiment, a matchmaking service calculates the weighted skill level of all participating members of a clan, along with the preferences of that clan, to find a well-matched clan. The matchmaking service may collect the skill statistics data of various clans and all their members over a number of game sessions. In one embodiment, the service may calculate the weighted skill level of a clan based on the clan's statistics data and the statistics data of current participating members to determine a weighted skill level. The service may then use this weighted skill level, along with preferences, to match this clan with another clan that has similar skill level and preferences. | 12-31-2009 |
20100138211 | ADAPTIVE WEB MINING OF BILINGUAL LEXICON - Embodiments for the adaptive mining of bilingual lexicon are disclosed. In accordance with one embodiment, the adaptive mining of bilingual lexicon includes retrieving one or more bilingual web pages, wherein each of the bilingual web page including a search term and one or more additional terms. The adaptive mining also includes forming a plurality of candidate translation pairs for each of the terms and extracting one or more translation layout patterns from the plurality of candidate translation pairs. The adaptive mining further includes deriving a term translation in a second language for the search term. The term translation being derived based on a hidden conditional random field (HCRF) model that includes the one or more candidate translations, the one or more translation layout patterns, and one or more additional features. The term translation is further stored in a lexicon repository. | 06-03-2010 |
20100286978 | ALIGNING HIERARCHIAL AND SEQUENTIAL DOCUMENT TREES TO IDENTIFY PARALLEL DATA - A set of candidate parallel pages is identified based on trigger words in one or more pages downloaded from a given network location (such as a website). A set of document trees representing each of the candidate pages are aligned to identify translationally parallel content and hyperlinks. The parallel content is further fed into conventional sentence aligner for parallel sentences. And the parallel hyperlinks usually refer to other parallel documents, and lead to a recursive mining of parallel documents. | 11-11-2010 |
20110103262 | MULTI-LEVEL INTERCONNECTION NETWORK - A method and system for providing a multi-level interconnection network is provided. A multi-level interconnection network comprises basic cells that are aggregated into higher level cells at each level of the network. At the first level, the basic cells are aggregated into first level cells. Each first level cell is an aggregation of a number of basic cells that is one more than the number of devices in a basic cell. The basic cells of a first level cell are fully connected; that is, each basic cell has a first level link or connection to each other basic cell. In a first level cell, each device of a basic cell has a first level link to each other basic cell. The multi-level interconnection network has higher level cells that are aggregations of lower level cells in a similar manner. | 05-05-2011 |
20110178792 | Acquisition Of Out-Of-Vocabulary Translations By Dynamically Learning Extraction Rules - A method and apparatus for identifying a set of bilingual term pairs, and from the set of bilingual term pairs, identifying a set of candidate patterns related to the layout of the bilingual term pairs in the bilingual webpage is provided. From the set of candidate patterns, one or more best patterns can be selected based on features identified in the candidate patterns. Using the one or more selected patterns, a set of translation pair candidates can be extracted. The translation pair candidates can be verified to determine the likelihood that each translation pair candidate is an accurate translation. Based on the verification, some or all of the translation pair candidates can be discarded as incorrect translations, and the remaining translation pair candidates can be identified as correct translation pairs. | 07-21-2011 |
20110289207 | METHOD AND APPARATUS FOR PROCESSING NETWORK VISUALIZATION - A method, system and computer program product for processing network visualization. The network visualization processing method includes: obtaining main-information-dimension-based topological data of an analytic object in a network; performing visualization processing to the main-information-dimension-based topological data of the analytic object so as to reveal change of a relationship between an analytic node and a neighboring node in the analytic object along the main information dimension. The network visualization processing method and apparatus according to the present invention can display dynamic change of the network based on main information dimension within a single view, and provide a better graphical resolution, so as to facilitate a user to perform analysis to the network and to reduce comprehension overhead of the user. | 11-24-2011 |
20120197627 | Bootstrapping Text Classifiers By Language Adaptation - Training data in one language is leveraged to develop classifiers for multiple languages under circumstances where all of those classifiers will be performing the same kind of classification task, but relative to linguistically different sets of texts, thereby saving the cost of manually labeling a different set of training data for each language. Classification knowledge is learned for a source language in which training data are available. That knowledge is transferred to another target language's classifier through the integration of language transition knowledge. The transferred model is adjusted to better fit the target language. In one technique, leveraging one language's classification knowledge in order to generate a classifiers for another language involves training a text classifier in a source language, transferring the learned classification knowledge from the source language to another target language using language translation techniques, and further tuning the transferred model to better fit the target language text. | 08-02-2012 |
20120289007 | MANUFACTURING METHOD FOR THIN FILM TRANSISTOR WITH POLYSILICON ACTIVE LAYER - Embodiments of the disclosed technology relate to a method for manufacturing a thin film transistor (TFT) with a polysilicon active layer comprising: depositing an amorphous silicon layer on a substrate, and patterning the amorphous silicon layer so as to form an active layer comprising a source region, a drain region and a channel region; depositing an inducing metal layer on the source region and the drain region; performing a first thermal treatment on the active layer provided with the inducing metal layer so that the active layer is crystallized under the effect of the inducing metal; doping the source region and the drain region with a first impurity for collecting the inducing metal; and performing a second thermal treatment on the doped active layer so that the first impurity absorbs the inducing metal remained in the channel region. | 11-15-2012 |
20120306398 | DRIVING APPARATUS, OLED PANEL AND METHOD FOR DRIVING OLED PANEL - The present disclosure relates to a driving apparatus, an OLED (Organic Light-Emitting Diode) panel, and a method for driving the OLED panel. The driving apparatus can be integrated on a substrate of pixel circuits and is capable of providing fast and stable current driving. The driving apparatus includes a switching module for selecting a voltage signal according to a received clock signal; a conversion module for converting the voltage signal into a current signal; and an output module for outputting the voltage signal or the converted current signal to drive a pixel circuit array, wherein the switching module is connected to the conversion module and the output module, and the conversion module is connected to the switching module and the output module. | 12-06-2012 |
20130007127 | DETERMINATION OF A SPAMMER THROUGH SOCIAL NETWORK CHARACTERIZATION - A method of determining a spammer includes acquiring, by a processor, short message events associated with a user and dividing them into a plurality of sessions in terms of time; building a social network of the user in each of the sessions, and calculating at least one type of social network characteristic in each of the sessions, respectively; and determining whether the user is a spammer or not according to the social network characteristic. | 01-03-2013 |
20130007151 | DETERMINATION OF A SPAMMER THROUGH SOCIAL NETWORK CHARACTERIZATION - A system for determining a spammer includes a session division apparatus configured to acquire short message events associated with a user and divide them into a plurality of sessions in terms of time; a social network building and characteristic calculating apparatus configured to build a social network of the user in each of the sessions, and calculate at least one type of social network characteristic in each of the sessions, respectively; and a determination apparatus configured to determine whether the user is a spammer or not according to the social network characteristic. | 01-03-2013 |
20130071144 | MULTIFUNCTIONAL CARBON POWDER FILLING DEVICE FOR REGENERATION OF CARBON POWDER CARTRIDGE - A multifunctional ink powder filling device for a regenerated powder cartridge box, which includes a bottle body, a powder-leakage prevention bottle plug, a powder filling nozzle and a bottle cover serving as a measuring cup at the same time, wherein the bottle plug is tightly matched and arranged on a bottle mouth of the bottle body and is externally provided with the powder filling nozzle, the inner and the outer peripheries of the pedestal of the powder filling nozzle are respectively provided with inner threads matched with the outer threads of the bottle mouth and outer threads matched with the inner threads on the mouth part of the bottle cover, and the upper end of the powder filling nozzle is provided with a diminishing heavy-caliber powder filling hopper. | 03-21-2013 |
20140145199 | Array Substrate and Method for Fabricating Array Substrate, and Display Device - The present invention discloses an array substrate, a method for fabricating an array substrate, and a display device, the array substrate includes: a base substrate; a TFT, a gate line, a data line and a pixel electrode formed on the base substrate, the TFT includes: a bottom gate, a first gate insulating layer, an active layer, a second gate insulating layer, a top gate, a gate isolation layer and a source electrode and a drain electrode sequentially formed on the base substrate; wherein, the source electrode and the drain electrode are in contact with the active layer through a first via hole and a second via hole passing through the gate isolation layer and the second insulating layer, respectively; the pixel electrode is in contact with the drain electrode. | 05-29-2014 |
20140172923 | METHOD & APARATUS FOR ASYNCHROINZED DE-SERIALIZATION OF E-R MODEL IN A HUGE DATA TRUNK - Embodiments of the present disclosure relate to the field of database technology. More specifically, embodiments of the present disclosure relate to a method and system for importing E-R model data utilizing dependency information in an E-R model data schema. This disclosure provides a method for importing E-R model data, comprising: receiving an imported E-R model data file and a data schema of the E-R model; determining a dependency type of each entity in the data file based on the data schema, wherein the dependency type corresponds to at least one of no correlation, weak correlation, or strong correlation; and correspondingly importing each entity in the E-R model data file based on the determined dependency type. | 06-19-2014 |
20140345510 | MOVEMENT INHIBITING APPARATUS FOR FLOATING OFFSHORE WIND TURBINE AND FLOATING BASE USED FOR OFFSHORE WIND TURBINE - A movement inhibiting apparatus for a floating offshore wind turbine and a floating base with the apparatus. The movement inhibiting apparatus for the floating offshore wind turbine comprises at least one layer of an annular shake-reducing panel placed horizontally and surrounding the floating base. A plurality of shake-reducing fins is further arranged on the shake-reducing panel. The plurality of shake-reducing fins comprises a first set of shake-reducing fins arranged on one side of the shake-reducing panel and the shake-reducing fins of the first set are spaced apart vertically around the floating base. The movement inhibiting apparatus for the floating offshore wind turbine can effectively inhibit the movement of the floating wind turbine and is of low cost. | 11-27-2014 |
20160064418 | ARRAY SUBSTRATE AND METHOD FOR FABRICATING ARRAY SUBSTRATE, AND DISPLAY DEVICE - The present invention discloses an array substrate, a method for fabricating an array substrate, and a display device, the array substrate includes: a base substrate; a TFT, a gate line, a data line and a pixel electrode formed on the base substrate, the TFT includes: a bottom gate, a first gate insulating layer, an active layer, a second gate insulating layer, a top gate, a gate isolation layer and a source electrode and a drain electrode sequentially formed on the base substrate; wherein, the source electrode and the drain electrode are in contact with the active layer through a first via hole and a second via hole passing through the gate isolation layer and the second insulating layer, respectively; the pixel electrode is in contact with the drain electrode. | 03-03-2016 |
Patent application number | Description | Published |
20090111430 | METHOD AND SYSTEM FOR IMPLEMENTING MESSAGING SERVICES AND A MESSAGE APPLICATION SERVER - A method for implementing messaging services includes receiving a message body sent by a calling user, determining whether the calling user and a called user are in the same IP Multimedia Subsystem (IMS) domain according to user registration information, and sending the message body to the called user if the calling user and the called user are in the same IMS domain. An IMS messaging service system includes a Message Application Server (MAS), a Call Session Control Function (CSCF) entity, a calling User Equipment (UE) and a called UE. A MAS includes a user registration information storing unit, a receiving unit, and a determining unit adapted to determine whether the calling user and the called user are in the same IMS domain according to the user registration information stored in the user registration information storing unit when the receiving unit receives the message body from the calling user, and a sending unit. According to embodiments of the present disclosure, when the calling user and the called user are in the same IMS domain, the information interaction process and the message body transmission time may be shortened. | 04-30-2009 |
20090129127 | METHODS AND DEVICES FOR INHIBITING NEGATIVE OUTPUT CURRENT DURING START-UP OF A SWITCH MODE POWER SUPPLY - A method of controlling a freewheel switch during start-up of a switch mode power supply to inhibit negative output current. The switch mode power supply has alternating first and second intervals. The freewheel switch has an ON-time and an OFF-time. The method includes gradually increasing the ON-time of the freewheel switch over a plurality of said intervals during start-up of the switch mode power supply until the ON-time of the freewheel switch is substantially equal to a duration of the second interval. | 05-21-2009 |
20110099548 | METHOD, APPARATUS AND SYSTEM FOR MAKING A DECISION ABOUT VIRTUAL MACHINE MIGRATION - A method, an apparatus, and a system for making a decision about virtual machine migration includes a source host platform, configured to send a migration request to a Migration Authority (MA), and to migrate the virtual machine to a target host platform according to a received migration decision-making result. The MA is configured to perform security checks on the source host platform and the target host platform, to obtain a first evaluation result of the source host platform and a second evaluation result of the target host platform, acquire a third evaluation result of the virtual machine, and return a corresponding migration decision-making result to the source host platform. The corresponding migration decision-making result indicates whether the virtual machine is permitted to be migrated; and the target host platform of the virtual machine to be migrated, is configured to accept the virtual machine to be migrated. | 04-28-2011 |
20120170793 | MICRO-SPEAKER - A micro-speaker includes a yoke, a magnet assembly attached to the yoke, a voice coil, and a diaphragm connected with the voice coil. The yoke defines a bottom wall, and a number of sidewalls extending upwardly from the bottom wall. The magnet assembly includes a main magnet positioned on the bottom wall, and a number of secondary magnets positioned on tops of the sidewalls. | 07-05-2012 |
20120173941 | METHOD, SYSTEM AND PROCESSOR FOR LOADING LOGICAL DEVICES ONLINE - A method, a system, and a processor for loading a logical device online are disclosed. The method for loading a logical device online includes receiving an online loading command; disabling a Joint Test Action Group (JTAG) link of a board on which the logical device is located through a bus between a processor and the logical device according to the online loading command, and enabling a link between an input/output (I/O) interface and a JTAG interface of the logical device through the bus according to the online loading command; and controlling the logical device through the bus so that the logical device is loaded online through the link between the I/O interface and the JTAG interface of the logical device. In this way, the logical device is loaded online without occupying any I/O interface or requiring addition of any I/O device. | 07-05-2012 |
20120177245 | MULTI-MAGNETIC SPEAKER - A multi-magnet speaker is disclosed. The multi-magnet speaker includes a frame defining a hollow space, a magnetic system defining a yoke and a plurality of magnetic gaps positioned in the hollow space, a diaphragm mounted on the frame and a plurality of coils attached to the bottom of the diaphragm. The diaphragm includes a plurality of vibrating membranes each defining a dome part and an arcuate portion radially extending from the periphery of the dome part. Each of the coils is received in the corresponding magnetic gap to drive the corresponding vibrating membrane to vibrate. | 07-12-2012 |
20120177246 | MULTI-MAGNET SYSTEM AND SPEAKER USING SAME - Disclosed is a multi-magnet system for speaker. The multi-magnet system includes a yoke having a bottom, a pair of main magnets separated from each other and mounted on the bottom of the yoke, respectively, a mid-magnet mounted on the bottom of the yoke and located between the pair of main magnets, and a pair of auxiliary magnets attached to two ends of the yoke. Wherein, the first main magnet together with the first auxiliary magnet and the mid-magnet defines a first magnetic gap and the second main magnet together with the second auxiliary magnet and the mid-magnet defines a second magnetic gap. By virtue of place the magnets at appropriate locations, the sensitivity of the speaker is effectively enhanced. | 07-12-2012 |
20130162435 | ALARM SYSTEM AND METHOD FOR FANS - An alarm system for a fan includes a first obtaining unit, a second obtaining unit, a storage unit, a control unit, and an alarm unit. The first obtaining unit is configured to obtain a temperature of a chip at a regular time interval. When the temperature of the chip is greater than a first predetermined value, the control unit obtains a standard speed of the fan corresponding to the temperature through the second obtaining unit, and obtains a standard speed of the fan corresponding to the temperature from the storage unit. When the number of times the speed of the fan is not in synchronization with the temperature of the CPU reaches a third predetermined value, the alarm unit sends alarm information. | 06-27-2013 |
20130259284 | Speaker-box - Disclosed is a speaker-box. The speaker-box includes a case, a speaker unit received in the case and a heat radiating portion attached on the base and directly connecting to a part of the speaker unit for dissipating the heat generated by the speaker unit. | 10-03-2013 |
20130279737 | MICRO-SPEAKER - A micro-speaker includes a yoke, a magnet assembly attached to the yoke, a voice coil, and a diaphragm connected with the voice coil. The yoke defines a bottom wall, and a number of sidewalls extending upwards from the bottom wall. The magnet assembly includes a main magnet positioned on the bottom wall, and a number of secondary magnets positioned on tops of the sidewalls. | 10-24-2013 |
20130322679 | Micro-Speaker - Disclosed is a micro-speaker. A micro-speaker includes a frame forming a receiving space, a vibrating unit, a magnetic circuit unit, a number of contacts, a front cover and a back cover. The contacts include a first contact and a second contact retained by the frame and partially exposed out of the frame, and a third contact disposed within the receiving space. The vibrating unit includes a diaphragm and a voice coil with a first terminal and a second terminal. The first terminal is electrically connected to the first contact, the second terminal is electrically connected to the third contact. An FPC is provided to electrically connect the third contact to the second contact. | 12-05-2013 |
20140184104 | DIMMING SYSTEM AND DIMMING CONVERTER AND LOAD DIMMING METHOD THEREOF - A dimming system and a dimming converter and load dimming method thereof are provided. In the dimming converter, a cutting phase determination unit is connected with an input terminal and configured to determine phase angle information of a power supply signal of an output of a load terminal in a dimmer; an output unit is configured to output a dimming signal corresponding to the phase angle information determined by the cutting phase determination unit from a dimming output terminal to a load of the dimming system according to a correspondence relationship between the phase angle information and the dimming signal stored in a storage unit and to output a phase-cut power source signal from a supply output terminal to the load. The dimming system can be compatible with a large number of loads with different dimming requirements to thereby improve the dimming efficiency of the loads. | 07-03-2014 |
20140319951 | SLOTLESS AMORPHOUS FERROALLOY ELECTRIC MACHINE WITH RADIAL MAGNETIC CIRCUIT AND ITS MANUFACTURING METHOD - A slotless amorphous ferroalloy electric machine with radial magnetic circuit and a manufacturing method. The invention includes a stator iron core ( | 10-30-2014 |
20150008779 | DISC-TYPE ELECTRIC MACHINE WITH AMORPHOUS IRON ALLOY AXIAL MAGNETIC CIRCUIT AS WELL AS ITS MANUFACTURING METHOD AND STATOR ASSEMBLY - A disc-type electric machine with amorphous iron alloy axial magnetic circuit, its stator iron core with an axial center through hole is processed into a cylinder made from amorphous iron alloy lamination, and its outer cylindrical surface is uniformly processed with a plurality of equi-spaced axial armature slots towards the center axial line. In the stator iron core embedded winding assemblies with the same number as the armature slots, each winding assembly comprises a winding wire frame matched with the armature slot, each stator winding arranged respectively in a slot of the winding wire frame and a magnetic conducting body arranged in a through hole of the winding wire frame. The said disc-type electric machine has short axial size, less moving components, small eddy current loss, excellent high-frequency characteristic, low temperature rising, high efficiency, high power density, high material utilization rate and high efficient energy-saving. | 01-08-2015 |
20150365414 | Method and Device for Authenticating Static User Terminal - Provided are a method and device for authenticating a static user terminal. The method comprises: an identity request message used for acquiring a user identity of the static user terminal is sent to the static user terminal; a response message is received from the static user terminal, wherein the response message carries the user identity of the static user terminal; and, an Extensible Authentication Protocol (EAP) authentication is performed on the static user terminal according to the user identity of the static user terminal. The present disclosure solves the problem in the related art of low security in the authentication on the static user terminal access the network, thus achieving the effects of increasing the security and reliability in the authentication on the static user terminal accessing the network and improving the WLAN service using experience of the static user. | 12-17-2015 |
Patent application number | Description | Published |
20090073331 | TUNABLE LIQUID CRYSTAL DEVICES, DEVICES USING SAME, AND METHODS OF MAKING AND USING SAME - An electro-optical device comprises a liquid crystal material disposed in a cell and electrodes configured to bias the liquid crystal material into a generally in-plane director configuration having a non-constant spatial pattern selectable or adjustable by an in-plane component of the biasing to produce a desired refractive of diffractive optical effect. | 03-19-2009 |
20090290078 | BISTABLE SWITCHABLE LIQUID CRYSTAL WINDOW - A bistable switchable liquid crystal device is provided in which the device can be switched between a transparent and an opaque state by a predetermined voltage pulse. The device is based on polymer stabilized cholesteric materials. No additional amount of voltage has to be applied to the device in order to sustain the optical states. Therefore, the device is energy-saving. | 11-26-2009 |
20100051194 | POLYMER ENHANCED CHOLESTERIC ELECTRO-OPTICAL DEVICES - The present invention provides liquid crystal devices comprised of a composite of an internal polymer network localized on the substrate surfaces and short-pitch dual-frequency switchable cholesteric liquid crystal that operate in two different modes including in-plane switching (amplitude modulation) and out-of-plane switching (phase modulation). The invention further provides a method of making a liquid crystal device demonstrating uniform lying helical axis where the device comprises a composite of an internal spatially ordered polymer network localized by in-situ photo-polymerization at the surface of the substrate. The invention can be used for flat panel displays, as well as spatial light modulators for applications such as optical waveguides, optical beam scanners, computer-generated holograms, and adaptive optics. | 03-04-2010 |
20110025955 | Tunable electro-optic liquid crystal lenses and methods for forming the lenses - Electro-optic lenses, including liquid crystals, wherein the power of the lenses can be modified by application of an electric field. In one embodiment, the liquid crystal-based lenses include ring electrodes having a resistive bridge located between adjacent electrodes, and in a preferred embodiment, input connections for several electrode rings are spaced on the lens. In a further embodiment, liquid crystal-based lenses are provided that can increase optical power through the use of phase resets, wherein in one embodiment, a lens includes ring electrodes on surfaces of the substrates on opposite sides of the liquid crystal cell such that a fixed phase term can be added to each set of electrodes that allows for phase change across each group of electrodes to be the same and also be matched with respect to a previous group. | 02-03-2011 |
20140132904 | TUNABLE ELECTRO-OPTIC LIQUID CRYSTAL LENSES AND METHODS FOR FORMING THE LENSES - Electro-optic lenses, including liquid crystals, wherein the power of the lenses can be modified by application of an electric field. In one embodiment, the liquid crystal-based lenses include ring electrodes having a resistive bridge located between adjacent electrodes, and in a preferred embodiment, input connections for several electrode rings are spaced on the lens. In a further embodiment, liquid crystal-based lenses are provided that can increase optical power through the use of phase resets, wherein in one embodiment, a lens includes ring electrodes on surfaces of the substrates on opposite sides of the liquid crystal cell such that a fixed phase term can be added to each set of electrodes that allows for phase change across each group of electrodes to be the same and also be matched with respect to a previous group. | 05-15-2014 |
Patent application number | Description | Published |
20080255178 | Azaadamantane Ester and Carbamate Derivatives and Methods of Use Thereof - The invention relates to compounds that are substituted azaadamantane ester and carbamate derivatives, compositions comprising such compounds, and methods of using such compounds and compositions. | 10-16-2008 |
20080255179 | Acetamide and Carboxamide Derivatives of Azaadamantane and Methods of Use Thereof - The invention relates to compounds that are acetamide and carboxamide derivatives of azaadamantane, compositions comprising such compounds, and methods of using such compounds and compositions. | 10-16-2008 |
20080262023 | Aminomethyl Azaadamantane Derivatives and Methods of Use Thereof - The invention relates to compounds that are substituted aminomethyl azaadamantane derivatives, compositions comprising such compounds, and methods of using such compounds and compositions. | 10-23-2008 |
20090281118 | Selective Ligands for the Neuronal Nicotinic Receptors and Uses Thereof - The present application describes selective ligands of formula (I) | 11-12-2009 |
20100087471 | INDOLE AND INDOLINE DERIVATIVES AND METHODS OF USE THEREOF - The present application relates to indole and indoline derivatives of formula (I), (II), (III), (IV), (V), or (VI) | 04-08-2010 |
20100249105 | INDOLE AND INDOLINE DERIVATIVES AND METHODS OF USE THEREOF - The present application relates to indole and indoline derivatives of formula (I), (II), (III), (IV), (V), or (VI) | 09-30-2010 |
20100305109 | POTASSIUM CHANNEL MODULATORS - Disclosed herein are KCNQ potassium channels modulators of formula (I) | 12-02-2010 |
20110152248 | BRIDGEHEAD AMINE RING-FUSED INDOLES AND INDOLINES - The present application relates to indole and indoline derivatives of formula (I), formula (II), formula (III), or formula (IV) | 06-23-2011 |
20110152306 | AZA-BRIDGED RING-FUSED INDOLES AND INDOLINES - The present application relates to indole and indoline derivatives of formula (I) | 06-23-2011 |
20110152308 | AZA-RING FUSED INDOLE AND INDOLINE DERIVATIVES - The present application relates to indole and indoline derivatives of formula (I) | 06-23-2011 |
20120122888 | Potassium Channel Modulators - Disclosed herein are KCNQ potassium channels modulators of formula (I) | 05-17-2012 |
20120190692 | SELECTIVE SUBSTITUTED PYRIDINE LIGANDS FOR NEURONAL NICOTINIC RECEPTORS - The present application describes selective ligands of formula (I) | 07-26-2012 |
20120190704 | AZAADAMANTANE ESTER AND CARBAMATE DERIVATIVES AND METHODS OF USE THEREOF - The invention relates to compounds that are substituted azaadamantane ester and carbamate derivatives, compositions comprising such compounds, and methods of using such compounds and compositions. | 07-26-2012 |
20120190706 | ACETAMIDE AND CARBOXAMIDE DERIVATIVES OF AZAADAMANTANE AND METHODS OF USE THEREOF - The invention relates to compounds that are acetamide and carboxamide derivatives of azaadamantane, compositions comprising such compounds, and methods of using such compounds and compositions. | 07-26-2012 |
20130096132 | AZAADAMANTANE DERIVATIVES AND METHODS OF USE - The invention relates to compounds that are azaadamantane derivatives, particularly ether- or amine-substituted azaadamantane derivatives and salts and prodrugs thereof, compositions comprising such compounds, methods of using such compounds and compositions, processes for preparing such compounds, and intermediates obtained during such processes. | 04-18-2013 |
20150158867 | AZAADAMANTANE DERIVATIVES AND METHODS OF USE - The invention relates to compounds that are azaadamantane derivatives, particularly ether- or amine-substituted azaadamantane derivatives and salts and prodrugs thereof, compositions comprising such compounds, methods of using such compounds and compositions, processes for preparing such compounds, and intermediates obtained during such processes. | 06-11-2015 |
20150353550 | INDOLE AND INDOLINE DERIVATIVES AND METHODS OF USE THEREOF - The present application relates to indole and indoline derivatives of formula (I), (II), (III), (IV), (V), or (VI) | 12-10-2015 |
Patent application number | Description | Published |
20080197458 | Small Outline Package in Which Mosfet and Schottky Diode Being Co-Packaged - The present invention provides a thin small outline package in which MOSPET and Schottky diode being co-packaged, which comprises a electrode S of MOSFET, a electrode | 08-21-2008 |
20090218673 | Semiconductor package having a bridge plate connection - A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metalized source areas and a metalized gate area, a patterned source connection having a plurality of dimples formed thereon coupling the source lead to the semiconductor die metalized source areas, a patterned gate connection having a dimple formed thereon coupling the gate lead to the semiconductor die metalized gate area, a semiconductor die drain area coupled to the drain lead, and an encapsulant covering at least a portion of the semiconductor die and drain, source and gate leads. | 09-03-2009 |
20090236708 | SEMICONDUCTOR PACKAGE HAVING A BRIDGED PLATE INTERCONNECTION - A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, and a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metallized source contacts. A bridged source plate interconnection has a bridge portion, valley portions disposed on either side of the bridge portion, plane portions disposed on either side of the valley portions and the bridge portion, and a connection portion depending from one of the plane portions, the bridged source plate interconnection connecting the source lead with the plurality of metallized source contacts. The bridge portion is disposed in a plane above the plane of the valley portions while the plane portions are disposed in a plane intermediate the plane of the bridge portion and the plane of the valley portions. | 09-24-2009 |
20090294934 | CONDUCTIVE CLIP FOR SEMICONDUCTOR DEVICE PACKAGE - A clip for a semiconductor device package may include two or more separate electrically conductive fingers electrically connected to each other by one or more electrically conductive bridges. A first end of at least finger is adapted for electrical contact with a lead frame. The bridges are adapted to provide electrical connection to a top semiconductor region of a semiconductor device and may also to provide heat dissipation path when a top surface of the fingers is exposed. A semiconductor device package may include the clip along with a semiconductor device and a lead frame. The semiconductor device may have a first and semiconductor regions on top and bottom surfaces respectively. The clip may be electrically connected to the top semiconductor region at the bridges and electrically connected to the lead frame at a first end of at least one of the fingers. | 12-03-2009 |
20100072585 | TOP EXPOSED CLIP WITH WINDOW ARRAY - A clip for a semiconductor device package may include a metal sheet including an array of windows and one or more conductive fingers. Each of the conductive fingers has a first end and a second end. The first end is electrically connected to the metal sheet at one of the windows. Each of the conductive fingers is adapted to provide electrical connection to a top semiconductor region of a semiconductor device or a lead frame at the second end. | 03-25-2010 |
20100197927 | Protein Tyrosine Phosphatase 1B Inhibitor, Preparation Methods and Uses Thereof - PTP1B inhibitors with the following structure (formula I). Experiments indicate that these inhibitors can effectively inhibit the activity of protein tyrosine phosphatase 1B (PTP1B). They can be used as insulin sensitisers. They can be used to prevent, delay or treat diseases which are related to insulin antagonism mediated by PTP1B, especially diabetes type II and obesity. The invention also provides methods for preparing these inhibitors. | 08-05-2010 |
20110227205 | MULTI-LAYER LEAD FRAME PACKAGE AND METHOD OF FABRICATION - The present invention features a lead-frame package, having a first, second, third and fourth electrically conductive structures with a pair of semiconductor dies disposed therebetween defining a stacked structure. The first and second structures are spaced-apart from and in superimposition with the first structure. A semiconductor die is disposed between the first and second structures. The semiconductor die has contacts electrically connected to the first and second structures. A part of the third structure lies in a common plane with a portion of the second structure. The third structure is coupled to the semiconductor die. An additional semiconductor die is attached to one of the first and second structures. The fourth structure is in electrical contact with the additional semiconductor die. A molding compound is disposed to encapsulate a portion of said package with a sub-portion of the molding compound being disposed in the volume. | 09-22-2011 |
20110233746 | Dual-leadframe Multi-chip Package and Method of Manufacture - A dual-leadframe multi-chip package comprises a first leadframe with a first die pad, and a second leadframe with a second die pad; a first chip mounted on the first die pad functioning as a high-side MOSFET and second chip mounted on the second die pad functioning as a low-side MOSFET. The package may further comprises a bypass capacity configured as a third chip mounted on the first die pad or integrated with the first chip. The package may further comprise a three-dimensional connecting plate formed as an integrated structure as the second die pad for electrically connecting a top contact area of the first chip to a bottom contact area of the second chip. A top connecting plate connects a top contact area of the second chip and a top contact area of the third chip to an outer pin of the first leadframe. | 09-29-2011 |
20110268803 | LUNG TARGETING DUAL DRUG DELIVERY SYSTEM - The American Cancer Society estimated that in 2009, 1,479,350 new cancer cases would be diagnosed in the United States of which 219,440 would be lung and bronchus related. The standard treatments for NSCLC include surgery, chemotherapy, radiation, laser and photodynamic therapy, all with various success rates depending on the stage of the cancer. National Cancer Institute assesses, however, that results of standard treatment are generally poor with only a 15 percent 5-year survival rate for combined cancer stages. Challenges facing the current chemotherapy drugs include excessive toxicity to healthy tissues and limited ability to prevent metastases. A dual drug delivery system described herein selectively targets the lung to deliver anti-cancer drugs and inhibit the formation of metastases. | 11-03-2011 |
20120104580 | SUBSTRATELESS POWER DEVICE PACKAGES - A substrate-less composite power semiconductor device may include a thin substrate and a top metal layer located on a top surface of the substrate. A total thickness of the substrate and the epitaxial layer may be less than 25 microns. Solder bumps are formed on top of the top metal layer and molding compound surrounds the solder bumps and leaves the solder bumps at least partly exposed. | 05-03-2012 |
20120155059 | LIGHT SOURCE COMPRISING A LIGHT EMITTER ARRANGED INSIDE A TRANSLUCENT OUTER ENVELOPE - The invention relates to a light source ( | 06-21-2012 |
20120161304 | Dual-leadframe Multi-chip Package and Method of Manufacture - A dual-leadframe multi-chip package comprises a first leadframe with a first die pad, and a second leadframe with a second die pad; a first chip mounted on the first die pad functioning as a high-side MOSFET and second chip mounted on the second die pad functioning as a low-side MOSFET. The package may further comprises a bypass capacity configured as a third chip mounted on the first die pad or integrated with the first chip. The package may further comprise a three-dimensional connecting plate formed as an integrated structure as the second die pad for electrically connecting a top contact area of the first chip to a bottom contact area of the second chip. A top connecting plate connects a top contact area of the second chip and a top contact area of the third chip to an outer pin of the first leadframe. | 06-28-2012 |
20120164793 | Power Semiconductor Device Package Method - Preparation methods of forming packaged semiconductor device, specifically for flip-chip vertical power device, are disclosed. In these methods, a vertical semiconductor chip is flip-chip attached to a lead frame and then encapsulated with plastic packing materials. Encapsulated chip is then thinned to a predetermined thickness. Contact terminals connecting the chip with external circuit are formed by etching at least a bottom portion of the lead frame connected. | 06-28-2012 |
20130099364 | Top-side Cooled Semiconductor Package with Stacked Interconnection Plates and Method - A top-side cooled semiconductor package with stacked interconnection plate is disclosed. The semiconductor package includes a circuit substrate with terminal leads, a semiconductor die atop the circuit substrate, a low thermal resistance intimate interconnection plate for bonding and interconnecting a top contact area of the semiconductor die with the circuit substrate, a low thermal resistance stacked interconnection plate atop the intimate interconnection plate for top-side cooling, a molding encapsulant for encapsulating the package except for exposing a top surface of the stacked interconnection plate to maintain effective top-side cooling. The top portion of the stacked interconnection plate can include a peripheral overhang above the intimate interconnection plate. The peripheral overhang allows for a maximized exposed top surface area for heat dissipation independent of otherwise areal constraints applicable to the intimate interconnection plate. The stacked interconnection plate can be partially etched or three dimensionally formed to create the peripheral overhang. | 04-25-2013 |
20130302946 | MULTI-LAYER LEAD FRAME PACKAGE AND METHOD OF FABRICATION - The present invention features a method for fabricating a lead-frame package, having a first, second, third and fourth electrically conductive structures with a pair of semiconductor dies disposed therebetween defining a stacked structure. The first and second structures are spaced-apart from and in superimposition with the first structure. A semiconductor die is disposed between the first and second structures. The semiconductor die has contacts electrically connected to the first and second structures. A part of the third structure lies in a common plane with a portion of the second structure. The third structure is coupled to the semiconductor die. | 11-14-2013 |
20140103512 | Dual-leadframe Multi-chip Package - A dual-leadframe multi-chip package comprises a first leadframe with a first die pad, and a second leadframe with a second die pad; a first chip mounted on the first die pad functioning as a high-side MOSFET and second chip mounted on the second die pad functioning as a low-side MOSFET. The package may further comprises a bypass capacity configured as a third chip mounted on the first die pad or integrated with the first chip. The package may further comprise a three-dimensional connecting plate formed as an integrated structure as the second die pad for electrically connecting a top contact area of the first chip to a bottom contact area of the second chip. A top connecting plate connects a top contact area of the second chip and a top contact area of the third chip to an outer pin of the first leadframe. | 04-17-2014 |
20140154843 | Method for Top-side Cooled Semiconductor Package with Stacked Interconnection Plates - A top-side cooled semiconductor package with stacked interconnection plate is disclosed. The semiconductor package includes a circuit substrate with terminal leads, a semiconductor die atop the circuit substrate, a low thermal resistance intimate interconnection plate for bonding and interconnecting a top contact area of the semiconductor die with the circuit substrate, a low thermal resistance stacked interconnection plate atop the intimate interconnection plate for top-side cooling, a molding encapsulant for encapsulating the package except for exposing a top surface of the stacked interconnection plate to maintain effective top-side cooling. The top portion of the stacked interconnection plate can include a peripheral overhang above the intimate interconnection plate. The peripheral overhang allows for a maximized exposed top surface area for heat dissipation independent of otherwise areal constraints applicable to the intimate interconnection plate. The stacked interconnection plate can be partially etched or three dimensionally formed to create the peripheral overhang. | 06-05-2014 |
20140193415 | BISPECIFIC ANTI-EGFR/ANTI IGF-1R ANTIBODIES - The present invention relates to bispecific anti-EGFR/anti IGF-1R antibodies, methods for their production, pharmaceutical compositions containing said antibodies, and uses thereof. | 07-10-2014 |
20140242756 | METHOD FOR PREPARING SEMICONDUCTOR DEVICES APPLIED IN FLIP CHIP TECHNOLOGY - A method for preparing semiconductor devices in a flip chip process comprises forming deep grooves surrounding each of the semiconductor chips; depositing a first plastic package material to form a first plastic package layer covering front surface of the semiconductor wafer and filling the deep grooves; depositing a metal layer at back surface of the semiconductor wafer after grinding; grinding an outermost portion of the metal layer thus forming a ring area located at back surface around edge of the semiconductor wafer not covered by the metal layer; cutting the first plastic package layer, the semiconductor wafer, the metal layer and the first plastic package material filled in the deep grooves along a straight line formed by two ends of each of the deep grooves filled with the first plastic package material; and picking up the semiconductor devices and mounting on a substrate without flipping the semiconductor devices. | 08-28-2014 |
20140264805 | Semiconductor Package And Fabrication Method Thereof - A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with top surfaces of conductive contact bodies electrically connected to electrodes on the top surface of the semiconductor chip exposed and plating conductive pads on a top surface of the assembly structure to provide external electrical connections to the electrodes through the conductive contact bodies. | 09-18-2014 |
20150021753 | PACKAGING STRUCTURE OF A SEMICONDUCTOR DEVICE - A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with top surfaces of conductive contact bodies electrically connected to electrodes on the top surface of the semiconductor chip exposed and plating conductive pads on a top surface of the assembly structure to provide external electrical connections to the electrodes through the conductive contact bodies. | 01-22-2015 |
20150056752 | SUBSTRATELESS POWER DEVICE PACKAGES - A substrate-less composite power semiconductor device may be fabricated from a vertical conductive power semiconductor device wafer that includes a top metal layer located on a top surface of the wafer by a) forming solder bumps on top of the top metal layer; b) forming wafer level molding around the solder bumps such that the solder bumps are exposed through a top of the wafer level molding; c) grinding a back side of the device wafer to reduce a total thickness of a semiconductor material portion of the device wafer to a final thickness; and d) forming a back metal on a back surface of the wafer. | 02-26-2015 |
20150062984 | POWER CONVERSION CIRCUIT AND POWER CONVERSION SYSTEM - A power converter, includes a first terminal and a second terminal which are connected to a direct current; a third terminal connected to an alternating current; N multi-level bridge arms connected in parallel to the first terminal and the second terminal, where the N multi-level bridge arms work in a parallel-interleaved manner, each multi-level bridge arm of the N multi-level bridge arms includes an alternating current node, and multiple time-varying levels are generated at the alternating current node, where the multiple levels are more than two levels; and a coupling inductor, including N windings coupled by one common magnetic core, where one end of each winding of the N windings is connected to an alternating current node of one multi-level bridge arm of the N multi-level bridge arms, and the other end of each winding of the N windings is connected to the third terminal. | 03-05-2015 |
20150087114 | METHOD FOR PACKAGING A POWER DEVICE WITH BOTTOM SOURCE ELECTRODE - A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process. | 03-26-2015 |
20150270789 | Multilevel Converter and Power Supply System - A multilevel converter includes at least one converting unit, where the converting unit includes N interleaved parallel bridge arms which enable the converting unit to output 2[(M−1×)N]+1 level signals, where N is an integer greater than or equal to 3, M is the number of levels received by the converting unit, and M is an integer greater than or equal to 3; a direct current inputting unit that supplies the direct current to the converting unit; a voltage dividing unit, where an input end of the voltage dividing unit is connected to an output of the direct current inputting unit, and an output end of the voltage dividing unit is connected to an input end of the converting unit; and at least one filtering unit, where the filtering unit is connected to the converting unit to output an alternating current. | 09-24-2015 |
20150340301 | SUBSTRATELESS POWER DEVICE PACKAGES - A vertical conductive power semiconductor device may include a substrate with a top metal layer located on a top surface of the substrate, solder bumps deposited on top of the top metal layer, and wafer level molding surrounding the solder bumps and leaving the solder bumps at least partly exposed. | 11-26-2015 |
Patent application number | Description | Published |
20090319809 | POWER SUPPLY CIRCUIT FOR CENTRAL PROCESSING UNIT - A power supply circuit for a CPU includes a first control circuit, a switch circuit, an operational amplifying circuit, and a second control circuit. The first control circuit is connected to a BIOS to receive a CPU identification signal. The switch circuit is connected to the first control circuit, and also connected between a CPU and a PSI pin of a VRM. The operational amplifying circuit is connected to the VRM to receive a current monitor signal output from the VRM. The second control circuit is connected to the operational amplifying circuit, the first control circuit and the PSI pin of the VRM. When the CPU identification signal is at a high level and the current monitor signal output from the VRM is lower than a reference voltage of the operational amplifying circuit, the switch circuit turns off, and the operational amplifying circuit outputs a second control signal to make the PSI pin of the VRM grounded. | 12-24-2009 |
20100001589 | POWER SUPPLY CIRCUIT FOR MOTHERBOARD - An exemplary power supply circuit for a motherboard includes a control circuit, a self-locking circuit, and an unlocking circuit. The control circuit is configured for receiving a working mode signal. The self-locking circuit is arranged to receive a power ok signal and a power supply on signal from a power supply, and is connected to the control circuit and a standby power. The unlocking circuit is connected to the control circuit, the self-locking circuit and the standby power, and is also arranged to receive the power ok signal. When the motherboard is placed in an energy-saving mode, the unlocking circuit unlocks the standby power from the motherboard when the computer is turned off to achieve energy savings. | 01-07-2010 |
20100090729 | CIRCUIT FOR CLEARING CMOS INFORMATION - A circuit for clearing complementary metal oxide semiconductor (CMOS) information of a CMOS chip of a computer includes a resistor and an electronic switch. The electronic switch includes a first terminal, a second terminal, and a third terminal. The first terminal is connected to a standby power supply of the computer. The second terminal is connected to a software reset pin of the CMOS chip. The third terminal is connected to a dual power supply of the computer via the resistor, and is connected to a hardware reset pin of the computer. The standby power supply is provided, and the first electronic switch is turned on before the computer is booted up. The software reset pin may be triggered to clear CMOS information of the CMOS chip upon the condition that the hardware reset pin is triggered. | 04-15-2010 |
20120254973 | DATA PROTECTION DEVICE FOR COMPUTERS - A data protection device includes a storage unit, a hard disk drive (HDD) controller, a switch, a network card; and a main control unit. The main control unit prevents the network card from communicating with communication networks when the first switch connects the HDD controller to the storage unit, and directs the first switch to disconnect the HDD controller from the storage unit when the network card is allowed to communicate with the communication networks. | 10-04-2012 |
20130147855 | ELECTRONIC DEVICE HAVING DISPLAY AND METHOD FOR ADJUSTING BRIGHTNESS OF DISPLAY - An electronic device includes a display, an illumination sensor, a distance detecting unit, a storage unit and a control unit. The illumination sensor periodically detects a current ambient illumination. The distance detecting unit periodically detects a current distance between a user and the electronic device. The control unit determines a corresponding current illumination level, and compares the current illumination level with a historical illumination level. If the current illumination level differs from the historical illumination level, the control unit further compares the current distance with a historical distance. If the current distance differs from the historical distance, the control unit maintains the brightness of the display; otherwise, the control unit adjusts the brightness of the display according to the illumination level. Then, the control unit stores the current illumination level and the current distance in the storage unit to update the historical illumination level and the historical distance. | 06-13-2013 |
Patent application number | Description | Published |
20110279744 | Short wave infrared multi-conjugate liquid crystal tunable filter - A SWIR hyperspectral imaging filter has serial stages along an optical signal path with angularly distributed birefringent retarders and polarizers. The retarders can include active retarders such as tunable liquid crystal birefringent elements, passive retarders such as fixed retarders, and/or combinations thereof. Distinctly different periodic transmission spectra are provided by different filter stages, each having multiple retarders, in particular with some stages having broad bandpass peaks at wide spectral spacing and other stages have very narrow closely spaced peaks. The respective spectra include at least one tunably selectable band at which the transmission spectra of the filter stages coincide, whereby the salutary narrow bandpass and wide spectral spacing ranges of different stages apply together, resulting in a high finesse wavelength filter suitable for spectral imaging. The filter may be configured to provide faster switching speed and increased angle of acceptance and may operate in the rage of approximately 850-1700 nm. | 11-17-2011 |
20120062888 | Method for operating an optical filter in multiple modes - A method for operating an optical filter in multiple modes. In one embodiment, an optical filter may be operated in a sensitivity mode to thereby generate a white light image representative of a region of interest. The optical filter may then be operated in a specificity mode to thereby generate a hyperspectral image representative of said region of interest. The white light image and the hyperspectral image may be fused to generate a hybrid image that provides morphological and hyperspectral data. The white light image and the hyperspectral image may be generated using a single detector, eliminating the need for image realignment. | 03-15-2012 |
20120300143 | VIS-SNIR multi-conjugate liquid crystal tunable filter - A VIS-NIR hyperspectral imaging filter has serial stages along an optical signal path with angularly distributed birefringent retarders and polarizers. The retarders can include active retarders such as tunable liquid crystal birefringent elements, passive retarders such as fixed retarders, and/or combinations thereof. Distinctly different periodic transmission spectra are provided by different filter stages, each having multiple retarders, in particular with some stages having broad bandpass peaks at wide spectral spacing and other stages have very narrow closely spaced peaks. The respective spectra include at least one tunably selectable band at which the transmission spectra of the filter stages coincide, whereby the salutary narrow bandpass and wide spectral spacing ranges of different stages apply together, resulting in a high finesse wavelength filter suitable for spectral imaging. The filter may be configured to provide faster switching speed and increased angle of acceptance and may operate in the rage of approximately 400-1100 nm. | 11-29-2012 |
20140098309 | Short-Wavelength Infrared (SWIR) Multi-Conjugate Liquid Crystal Tunable Filter - A SWIR hyperspectral imaging filter has serial stages along an optical signal path with angularly distributed birefringent retarders and polarizers. The retarders can include active retarders such as tunable liquid crystal birefringent elements, passive retarders such as fixed retarders, and/or combinations thereof. Distinctly different periodic transmission spectra are provided by different filter stages, each having multiple retarders, in particular with some stages having broad bandpass peaks at wide spectral spacing and other stages have very narrow closely spaced peaks. The respective spectra include at least one tunably selectable band at which the transmission spectra of the filter stages coincide, whereby the salutary narrow bandpass and wide spectral spacing ranges of different stages apply together, resulting in a high finesse wavelength filter suitable for spectral imaging. The filter may be configured to provide faster switching speed and increased angle of acceptance and may operate in the rage of approximately 850-1700 nm. | 04-10-2014 |
20140362331 | Short-Wavelength Infrared (SWIR) Multi-Conjugate Liquid Crystal Tunable Filter - A SWIR hyperspectral imaging filter has serial stages along an optical signal path with angularly distributed birefringent retarders and polarizers. The retarders can include active retarders such as tunable liquid crystal birefringent elements, passive retarders such as fixed retarders, and/or combinations thereof. Distinctly different periodic transmission spectra are provided by different filter stages, each having multiple retarders, in particular with some stages having broad bandpass peaks at wide spectral spacing and other stages have very narrow closely spaced peaks. The respective spectra include at least one tunably selectable band at which the transmission spectra of the filter stages coincide, whereby the salutary narrow bandpass and wide spectral spacing ranges of different stages apply together, resulting in a high finesse wavelength filter suitable for spectral imaging. The filter may be configured to provide faster switching speed and increased angle of acceptance and may operate in the rage of approximately 850-1700 nm. | 12-11-2014 |
Patent application number | Description | Published |
20130224910 | METHOD FOR CHIP PACKAGE - Provided is a method for chip packaging, including the steps of: providing a semi-packaged wafer which has a cutting trail and a metal bonding pad of the chip; forming on the metal bonding pad a sub-ball metal electrode, using a selective formation process; forming a protective layer on the wafer in a region not including the sub-ball metal electrode, with the protective layer covering the cutting trail; forming a solder ball on the sub-ball metal electrode; dicing the wafer along the cutting trail. The present invention can prevent metal in the cutting trail from being affected during the production of the sub-ball metal electrode, and protect the lateral sides of a discrete chip after cutting. The process flow thereof is simple, and enhances the efficiency of the packaging as well as its yield. | 08-29-2013 |
20130280904 | METHOD FOR CHIP PACKAGING - Provided is a method for chip packaging, including the steps of: providing a semi-packaged wafer which has a cutting trail and a metal bonding pad of the chip; forming a first protective layer on the cutting trail; forming on the metal bonding pad a sub-ball metal electrode; forming a solder ball on the sub-ball metal electrode; dicing the wafer along the cutting trail. The first protective layer according to the present invention can prevent the metal in the cutting trail from being separated by electroplating, and protect the lateral sides of a discrete chip after cutting. The process flow thereof is simple, and enhances the efficiency of the packaging as well as its yield. | 10-24-2013 |
20130301228 | PACKAGING STRUCTURE - The present invention relates a packaging structure including: a carrier board and a cementing layer on the surface of the carrier board; chips and passive devices having functional side thereof attached to the cementing layer; and a sealing material layer for packaging and curing, the sealing material being formed on the carrier board on the side attached to the chips and the passive devices. The present invention integrates chips and passive devices and then packages the chips and the passive devices together, and is therefore a packaged product having not single-chip functionality but integrated-system functionality. The present invention is highly integrated, reduces interfering factors such as system-internal electric resistance and inductance, and accommodates growing demand for lighter, thinner, shorter, and smaller semiconductor packaging. | 11-14-2013 |
20130302947 | PACKAGING METHOD - The present invention relates to a packaging method including the steps: a cementing layer is formed on a carrier board; the functional sides of chips and passive devices are attached to the cementing layer; a sealing material layer is formed on the side of the carrier board to which the chips and the passive devices are attached, and packaging and curing are performed; and the carrier board and the cementing layer are removed. Compared to the prior art, the system-level fan-out wafer packaging method claimed by the present invention first integrates chips and passive devices and then packages the chips and the passive devices together, thereby forming a final packaged product having not single-chip functionality but integrated-system functionality. Compared to current system-level packaging, highly integrated wafer-level packaging reduces such interfering factors as system-internal electric resistance and inductance, and accommodates the growing demand for lighter, thinner, shorter, and smaller semiconductor packaging. | 11-14-2013 |
20130313699 | FAN-OUT HIGH-DENSITY PACKAGING METHODS AND STRUCTURES - A fan-out high-density packaging method includes providing a packaging substrate, forming a stripping film on the packaging substrate, and forming a first protection layer on the stripping film and pre-designed photolithography pattern openings on the first protection layer. The method also includes forming a metal redistribution layer on the surface of the first protection layer and in the photolithography pattern openings, forming a second protection layer on the first protection layer and partially exposing the metal redistribution layer, and forming at least one package layer on the second protection layer. Each of at least one package layer includes a straight mounting layer, a sealant layer, and a wiring layer formed in sequence, and the package layer connects the metal redistribution layer through the wiring layer. Further, the method includes forming at least one top-level package layer on top of the at least one package layer, removing the packaging substrate and the stripping film to expose the metal redistribution layer in the first protection layer, and planting metal solder balls on the exposed metal redistribution layer. | 11-28-2013 |
20130320533 | 3D SYSTEM-LEVEL PACKAGING METHODS AND STRUCTURES - A 3D system-level packaging method includes providing a packaging substrate having a first functional surface and a second surface with wiring arrangement within the packaging substrate and between the first functional surface and the second surface. The method also includes forming at least one flip package layer on the first functional surface of the packaging substrate and forming at least one wiring and package layer on the flip package layer. The flip package layer is formed by subsequently forming a flip mounting layer, an underfill, a sealant layer, and a wiring layer; and the wiring and package layer is formed by subsequently forming a straight mounting layer, a sealant layer, and a wiring layer. Further, the method includes planting connection balls on the second functional surface of the packaging substrate. | 12-05-2013 |
20130320534 | SYSTEM-LEVEL PACKAGING METHODS AND STRUCTURES - A system-level packaging method includes providing a packaging substrate having a first functional surface and a second surface with wiring arrangement within the packaging substrate and between the first functional surface and the second surface. The method also includes forming at least two package layers on the first functional surface of the packaging substrate, wherein each package layer is formed by subsequently forming a mounting layer, a sealant layer, and a wiring layer. Further, the method includes forming a top sealant layer and planting connection balls on the second functional surface of the packaging substrate. | 12-05-2013 |
20130320535 | THREE-DIMENSIONAL SYSTEM-LEVEL PACKAGING METHODS AND STRUCTURES - A 3D system-level packaging method includes providing a packaging substrate, forming a glue layer on the substrate, and attaching a first chip layer at an opposite side of a functional surface of the first chip layer on the packaging substrate through the glue layer. The method also includes forming a first sealant layer on the packaging substrate at a same side attached with the first chip layer and exposing bonding pads of the first chip layer. The method also includes forming first vias in the first sealant layer, forming first vertical metal wiring in the first vias, and forming a first horizontal wiring layer on the sealant layer interconnecting the first chip layer and the first vertical metal wiring. Further, the method includes forming a plurality of package layers on the first sealant layer, and each of the plurality of package layers includes a chip layer, a sealant layer covering the chip layer, and vertical metal wiring and a horizontal wiring layer interconnecting adjacent package layers. | 12-05-2013 |
20140124927 | SEMICONDUCTOR IC PACKAGING METHODS AND STRUCTURES - An IC packaging method is provided. The method includes providing a semiconductor substrate. The semiconductor substrate has a metal pad and an insulating layer and the insulating layer has an opening to expose the meal pad. The method also includes forming an under-the-ball meal electrode on the exposed metal pad. The under-the-ball metal electrode has an electrode body and an electrode tail, the electrode body is located at a bottom portion of the under-the-ball metal electrode and is in contact with the metal pad, and the electrode tail is located at a top portion of the under-the-ball meal electrode. Further, the method includes forming a solder ball on the under-the-ball metal electrode. | 05-08-2014 |
20140124929 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD - Semiconductor devices and methods are provided. The semiconductor device can include a semiconductor substrate, a plurality of solder pads disposed on the semiconductor substrate, a first insulating layer disposed over the semiconductor substrate, a columnar electrode disposed over the solder pad, and a solder ball disposed on the columnar electrode. The first insulating layer can include a first opening to expose a solder pad of the plurality of solder pads. The columnar electrode can include a bulk material and a through hole in the bulk material. The through hole can expose at least a surface portion of the solder pad. The solder ball can include a convex metal head on a top surface of the bulk material of the columnar electrode, and a filling part filled in the through hole. | 05-08-2014 |
20150228568 | FAN-OUT HIGH-DENSITY PACKAGING METHODS AND STRUCTURES - A fan-out high-density packaging method includes providing a packaging substrate, forming a stripping film on the packaging substrate, and forming a first protection layer on the stripping film and pre-designed photolithography pattern openings on the first protection layer. The method also includes forming a metal redistribution layer on the surface of the first protection layer and in the photolithography pattern openings, forming a second protection layer on the first protection layer and partially exposing the metal redistribution layer, and forming at least one package layer on the second protection layer. Each of at least one package layer includes a straight mounting layer, a sealant layer, and a wiring layer formed in sequence, and the package layer connects the metal redistribution layer through the wiring layer. Further, the method includes forming at least one top-level package layer on top of the at least one package layer, removing the packaging substrate and the stripping film to expose the metal redistribution layer in the first protection layer, and planting metal solder balls on the exposed metal redistribution layer. | 08-13-2015 |
20150287688 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and a manufacturing method thereof. The semiconductor device includes a semiconductor substrate ( | 10-08-2015 |
20150294949 | CHIP PACKAGING STRUCTURE AND PACKAGING METHOD - A chip packaging structure and packaging method. The packaging structure comprises: a semiconductor substrate; a metal pad provided inside the semiconductor substrate; an insulating layer provided on the semiconductor substrate, the insulating layer having an opening for exposing the metal pad; a sub-ball metal electrode provided on the metal pad; a solder ball provided on the surface of the sub-ball metal electrode, the solder ball having a first apron structure and the first apron structure covering partial metal pad on the periphery of the bottom of the under-ball metal electrode. The chip packaging structure of the present invention enhances the adhesion between the solder ball and the metal pad, and improves the reliability in chip packaging. | 10-15-2015 |