Patent application number | Description | Published |
20100165075 | METHOD FOR AUTOMATICALLY SHOOTING PANORAMIC IMAGE BY DIGITAL IMAGE PICKUP DEVICE - A method for automatically shooting a panoramic image by a digital image pickup device is described. In the method, a pixel error value between a real-time image and an alignment image overlapped with each other is continuously compared and calculated. When the pixel error value is smaller than a preset threshold value, the digital image pickup device is automatically driven to shoot a second image to be stitched and blended with a previous image into a panoramic image. The shooting of the panoramic image is simplified by using automatic image capturing. | 07-01-2010 |
20100194852 | AUTOMATIC CAPTURING METHOD OF A PANORAMIC IMAGE FOR A DIGITAL CAMERA - An automatic capturing method of a panoramic image for a digital camera panoramic image is presented. In the method, a motion vector value of an alignment image selected from a first image captured by the digital camera in a real-time image is continuously tracked, calculated, and accumulated to obtain an accumulated motion vector value. When the accumulated motion vector value reaches a preset threshold value, the digital camera is automatically driven to capture a second image, so as to stitch and blend the first image and the second image into a panoramic image. Through the automatic image capture mode, operations for capturing the panoramic image are simplified. | 08-05-2010 |
20110012989 | GUIDING METHOD FOR PHOTOGRAPHING PANORAMA IMAGE - A guiding method for photographing a panorama image is described. A motion vector between a current position of an alignment image in a real-time image and a joint position of the alignment image in the real-time image, and a direction indicator relative to the motion vector is displayed, such that when the digital camera device displays the real-time image, the digital camera device may display the direction indicator to guide a photographing position of a next image for a user, thereby simplifying the photographing of a panorama image and greatly decreasing an incidence that the user fails to photographing a panorama image. | 01-20-2011 |
20110019013 | METHOD FOR ADJUSTING PHOTOGRAPHING SETTINGS OF DIGITAL CAMERA THROUGH MOTION DETECTION - A method for adjusting photographing settings of a digital camera through motion detection, for determine to adjust the photographing settings of the digital camera according to vibrations of the digital camera or shaking of a photographed object. The adjusting method includes the following steps. At least two continuous pre-photographed images are captured. A central area and an edge area are set at same positions in the pre-photographed images respectively. Feature points are found in the pre-photographed images. A local motion vector and a camera motion vector are respectively determined according to a relation of the feature points on the central area and the edge area. A subject motion vector is generated according to a difference between the local motion vector and the camera motion vector. Adjustment of the photographing settings of the digital camera is determined according to a maximum value in the subject motion vector and camera motion vector. | 01-27-2011 |
20110157392 | METHOD FOR ADJUSTING SHOOTING CONDITION OF DIGITAL CAMERA THROUGH MOTION DETECTION - A method for adjusting a shooting condition of a digital camera through motion detection is applied to determine a shooting parameter of the digital camera. The adjusting method includes the following steps. At least two consecutive images, namely a first pre-capture image and a second pre-capture image, are selected. The first pre-capture image and the second pre-capture image are divided into a plurality of selection blocks. A motion vector of each selection block is calculated. The motion vector of each selection block is used to generate a background dominant motion vector of the camera sloshing and a self-movement vector of the shot object. The background dominant motion vector is subtracted from the self-movement vector of the shot object, so as to obtain a corrected foreground motion vector. According to the size of the corrected foreground motion vector, the corresponding shooting parameter is determined. | 06-30-2011 |
20120177253 | METHOD AND APPARATUS FOR GENERATING PANORAMA - A method and an apparatus for generating a panorama are provided. In the present method, a plurality of raw images of a scene is captured. A coarse motion estimation is executed on the raw images to obtain a coarse motion estimation result of the scene. In the meantime, the raw images inside a window of interest (WOI) are cropped to obtain a plurality of cropped images, and a fine motion estimation is executed on the cropped images according to the coarse motion estimation result of the scene, so as to obtain a fine motion estimation result of the scene. The raw images are stitched and blended according to the fine motion estimation result, so as to generate the panorama. | 07-12-2012 |
20130188874 | METHOD FOR IMAGE PROCESSING AND APPARATUS USING THE SAME - An image processing method and an apparatus using the same are provided. The method includes the following steps: deriving a global motion vector between a first image and a second image and providing the first image, the second image and the global motion vector to a first application process, wherein the first image is the previous image of the second image; deriving a first compensated image and a second compensated image by performing a lens distortion compensation process on the first image and the second image respectively; deriving a compensated global motion vector corresponding to the first compensated image and the second compensated image by transforming and correcting the global motion vector; and providing the first compensated image, the second compensated image, and the compensated global motion vector to a second application process. | 07-25-2013 |
20130250041 | IMAGE CAPTURE DEVICE AND IMAGE SYNTHESIS METHOD THEREOF - This invention discloses an image capture device and an image synthesis method thereof. The image capture device comprises an image pickup module and a processing module. The image pickup module scans a plurality of visual angles of a scene in advance to obtain a plurality of temporary images. Each of the temporary images has a scanning focal length value. The processing module analyzes the plurality of temporary image of each of the visual angles to obtain a temporary focal length value. The processing module obtains a weighting focal length value by each temporary focal length value by using a function to control the image pickup module in order to perform a panorama image capturing process according to the weighting focal length value. | 09-26-2013 |
20130250136 | IMAGE PICKUP DEVICE AND IMAGE PREVIEW SYSTEM AND IMAGE PREVIEW METHOD THEREOF - The present invention discloses an image pickup device, an image preview system and an image preview method thereof. The image pickup device comprises an image pickup module, an image processing module and a display module. The image pickup module is arranged for capturing a plurality of images. The image processing module is arranged for scaling down pixels of each image to generate a plurality of adjusted images, and combining the plurality of adjusted images to generate a preview image. The display module is arranged for displaying the preview image. Wherein, the image processing module is arranged for rendering a high dynamic range image according to the plurality of images while the plurality of adjusted images is blended. | 09-26-2013 |
20130307922 | IMAGE PICKUP DEVICE AND IMAGE SYNTHESIS METHOD THEREOF - This invention discloses an image pickup device and an image synthesis method thereof The image pickup device comprises an image-pickup module, an image-synthesis module, a database and a processing module. The image-pickup module captures a plurality of temporary images of a scene. The image-synthesis module extracts a part of each temporary image and combines the parts to form a panorama temporary image, and splits the panorama temporary image into a plurality of zone-areas according to at least one threshold value and a panorama luminosity histogram. The database stores a lookup table for recording a plurality of exposure values. The plurality of the exposure values correspond to luminance values of the zone-areas respectively. The processing module obtains the plurality of exposure values corresponding to the luminance values and obtains a weighting-exposure value by an equation, and controls the image-pickup module to capture the panorama image according to the weighting-exposure value. | 11-21-2013 |
Patent application number | Description | Published |
20080240026 | DISTRIBUTED CHANNEL ALLOCATION METHOD AND WIRELESS MESH NETWORK THEREWITH - A distributed channel allocation method and a wireless mesh network with the same are provided herein. By the distributed channel allocation, interference situations are avoided in a wireless network communication, and the allocated bandwidth can then be fully utilized. Besides, unnecessary depletion of an allocated bandwidth due to the interference can be avoided. By this method, a time division technique is applied for dividing a transmission time of each wireless NIC, and different non-overlapping channels can be assigned to different timeslots. Different from other researches that require a symmetrical number of the NICs between a receiving node and a transmitting node, in this method, a unique wireless NIC may communicate with the wireless NICs. The method provides the feature that the number of the NICs on a certain node can be adjusted to meet a communication requirement, by which the efficiency of a network flow is also significantly improved. | 10-02-2008 |
20090054036 | GROUP AUTHENTICATION METHOD - A group authentication method adaptable to a communication system is disclosed. The communication system includes a user group, a serving network, and a home network. The user group includes at least one mobile station. The home network pre-distributes a group authentication key to itself and all the mobile stations in the same user group and generates a mobile station authentication key for each mobile station. The home network generates a group list for recording related information of the user group. The home network has a database for recording the group list. The serving network has a database for recording the group list and a group authentication data received from the home network. The group authentication method includes following steps. The serving network performs an identification action to a mobile station. The communication system performs a full authentication action or a local authentication action according to the result of the identification action. | 02-26-2009 |
20100110963 | SYSTEM AND METHOD FOR MULTICAST/ BROADCAST SERVICE ZONE BOUNDARY DETECTION - A wireless communication method for providing zone boundary detection performed by a controller managing communications within a multicast/broadcast service (MBS) zone. The method includes assigning to a boundary paging group a first base station communicating within the MBS zone and near a boundary of the MBS zone. The method further includes transmitting, through a second base station which covers a mobile station, to the mobile station information indicating that the boundary paging group corresponds to locations near the boundary of the MBS zone. | 05-06-2010 |
20100260071 | ROUTING METHOD AND ROUTING PATH RECOVERY MECHANISM IN WIRELESS SENSOR NETWORK ENVIRONMENT - The present invention discloses an asymmetric routing method and routing path recovery mechanism. The wireless sensor network environment includes at least a management unit, at least a gateway, and mobile nodes. When joining, each mobile node obtains an unique ID code and, additionally, a depth as the gradient to the management unit. Accordingly, a mobile node sends an uplink packet via a nearby node with lower depth to the management unit; while the management unit transmits a downlink packet to a mobile node by utilizing the source route method. When the parent node of a mobile node is damaged or moves to another position or said mobile node with its sub-tree descendants changes their position together, the uplink routing path is recovered via selecting a nearby node of the sub-tree as relay node and the downlink routing path is recovered via sending a control message to the management unit. | 10-14-2010 |
20110047382 | FAST AUTHENTICATION BETWEEN HETEROGENEOUS WIRELESS NETWORKS - A method for preparing for handover of an apparatus from a first wireless network to a second, different wireless network, a master session key (MSK) having been generated during establishment of a connectivity of the apparatus to the first wireless network includes detecting signals of the second wireless network. In response thereto, establishing a connectivity of the apparatus to the second wireless network, using a pairwise master key (PMK) derived from the MSK generated during establishment of the connectivity to the first wireless network, one or more encryption keys being derivable from the PMK to support secure communication over the second wireless network. | 02-24-2011 |
20110051644 | POWER-EFFICIENT BACKBONE-ORIENTED WIRELESS SENSOR NETWORK, METHOD FOR CONSTRUCTING THE SAME AND METHOD FOR REPAIRING THE SAME - The present invention discloses a power-efficient backbone-oriented wireless sensor network, a method for constructing the same and a method for repairing the same, wherein energy-rich nodes are used to form backbones linking to a server, and wherein regular nodes having limited energy storage link to the backbones. When one energy-rich node malfunctions, the energy-rich node, which is posterior to the malfunctioning energy-rich node, searches for and links to a linkable neighboring energy-rich node on the backbone. If there is none linkable neighboring energy-rich node, the regular nodes are used to form a temporary tunnel until the malfunctioning energy-rich node has been repaired. The present invention can relieve the influence of hot spots, increase the robustness of the wireless sensor network, and prolong the service life of the wireless sensor network. | 03-03-2011 |
20120131430 | MULTIMEDIA BOOKMARK METHOD AND SYSTEM THEREOF - The present invention discloses a multimedia bookmark method and a system thereof. The method of the present invention comprises steps: providing a plurality of digital annotations for an information object; creating a bookmark containing an ordered set organized according to a time relativity, a file relativity or a user-defined attribute of the digital annotations; and presenting the bookmark and the information object corresponding to the bookmark. Thereby, the present invention provides complete, meaningful and multi-aspect bookmarks, enabling users to easily understand and conveniently use the annotations. | 05-24-2012 |
20120331295 | METHOD FOR KEY GENERATION, MEMBER AUTHENTICATION, AND COMMUNICATION SECURITY IN DYNAMIC GROUP - The present invention provides a method for keys generation, member authentication and communication security in a dynamic group, which comprises steps: assigning each member an identification vector containing common group identification vector elements and an individual identification vector element, and generating an authentication vector and an access control vector for each member according to the identification vector; using the identification vector elements to generate public key elements and establish an authentication public key and an access control public key; and using a polynomial and the identification vector to generate a private key. The present invention uses these public keys and private keys, which are generated from the identification vectors, to implement serverless member authentication and data access control, whereby is protected privacy of members and promoted security of communication. | 12-27-2012 |
20130117437 | METHOD FOR ESTABLISING TCP CONNECTING ACCORDING TO NAT BEHAVIORS - The present invention is to provide a method for establishing TCP connection according to NAT (Network Address Translation) behaviors, which is applied to a network system having a NBA (NAT Behavior Aware Server) located in the Internet and connected to two NATs in two private networks respectively. The method enables two network devices in the respective private networks to send testing messages to the NBA via the respective NATs. In response, the NBA sends reply messages to each network device to test the behaviors of the NATs respectively. Afterward, each network device generates a test result message according to each behavior of the corresponding NAT and sends the same to the NBA. Based on the test result messages, the NBA selects an optimal traversal technique from candidate traversal techniques, thereby allowing the network devices to respectively and directly traverse the NATs and establish a direct TCP connection therebetween. | 05-09-2013 |
20130132809 | STRUCTURE AND METHOD FOR WIDGET PERSONALIZATION AND WIDGET INTERACTION - The present invention provides a structure and method for widget personalization and widget interaction, wherein user preference keys and user preference values are generated according to user profiles and binding configurations of a plurality of widgets, and wherein the keys and values of a widget are added to URL of the widget, whereby a personalized widget is attained after the widget is reloaded. The setting data of a widget, including a plurality of element values, are stored in a document object model (DOM). When relativities exist between widgets, the related element values are transferred from one widget to other widgets through a transfer module to replace the element values in DOM of the other widgets and update the other widgets. | 05-23-2013 |
20140052939 | INTEGRATED STORAGE PLATFORM SYSTEM AND METHOD THEREOF - The present invention discloses an integrated storage platform system and a method thereof. The system comprises at least one adaption module respectively connecting with at least one storage space and each performing a plurality of adaption settings corresponding to one storage space; a storage administration module connecting with the adaption modules and processing the files of the storage spaces; and an access interface connecting the storage administration module, operated by a user to access the storage space through the storage administration module and the adaption module, and presenting access results to the user. The present invention establishes different adaption modules to enable the user to link to and access different types of storage spaces. | 02-20-2014 |
20140310356 | METHOD FOR EXCHANGING NETWORK MESSAGES IN DISTRIBUTED MANNER - The present invention is to provide a method for enabling a tracker/coordinator in a P2P system to receive server address queries from network devices through Internet; provide address of a protocol server to the network devices according to the server address queries, so as for the network devices to conduct NAT behavior tests on NAT routers connected therewith through the protocol server; assigning a first network device with the router incapable of forwarding messages to a second network device with the router capable of forwarding messages according to the test results; providing a mapped address of a port of the second network device to a third network device, when receiving a port query from the third network device and determining that the port query corresponds to the first network device, so as for the third network device to directly connect with the first network device through the second network device. | 10-16-2014 |
20140310397 | NETWORK SYSTEM CAPABLE OF IMPLEMENTING STUN WITH THE ASSISTANCE OF TWO NETWORK DEVICES AND METHOD THEREOF - The present invention is to provide a network system, which comprises a coordinator server located in a public network; first and second NATs (Network Address Translators) located in first and second private networks and configured as a full-cone NAT, respectively; first and second network devices located in the first and second private networks and connected to the public network through the first and second NATs, respectively, wherein each of the first and second network devices has registered two mapped addresses with the coordinator server, respectively; a third NAT located in a third private network; and a third network device located in the third private network and connected to the public network through the third NAT, wherein the third network device can obtain the mapped addresses from the coordinator server and, based on the mapped addresses, conduct NAT behavior tests on the third NAT through the first and second network devices. | 10-16-2014 |
20140362822 | SYSTEM ARCHITECTURE AND METHOD FOR SERVICE CONTINUITY IN HETEROGENEOUS WIRELESS NETWORK - The present invention provides a system architecture and a method for service continuity in heterogeneous wireless networks, which comprises a handover decision module and a session continuity module. The handover decision module is responsible for maintaining link layer association and network layer reachability in according to the underlying network conditions to fulfill the service requirement of applications. When acting as a sender, the session continuity module will select transmission path(s), reestablish the transport connection(s) and tag packets with session IDs and sequence numbers. When acting as a receiver, the session continuity module will identify and reorder packets using session IDs and sequence numbers, regardless of the IP addresses and ports of the packets. To sum up, the present invention can provide service continuity and multipath transmission for network devices. | 12-11-2014 |
20150271135 | SESSION-AWARE NETWORK ADDRESS TRANSLATION TRAVERSAL METHOD - The session-aware NAT traversal method is used to establish network communication between two hosts, wherein a first and a second host are located behind a first and a second NAT router, respectively. First, these hosts conduct a standard NAT traversal to establish a session. Then, the second host sends a registration request message to the first NAT router for session registration. Upon receiving the registration request message, the first NAT router generates a session ID for this session and replies to the second host. As the second host moves to a private network behind a third NAT router, the second host only needs to send a new registration request message with the session ID to the first NAT router. The first NAT router observes a new mapped address of the second host and allows inbound traffic from the new mapped address without further NAT traversal. | 09-24-2015 |
Patent application number | Description | Published |
20120026449 | LIQUID CRYSTAL DISPLAY PANEL - A liquid crystal display (LCD) panel including a first substrate, a second substrate, a liquid crystal layer, a photo-curable sealant, and a first light-shielding pattern is provided. The liquid crystal layer is disposed between the first substrate and the second substrate. The photo-curable sealant is disposed between the first substrate and the second substrate, wherein the photo-curable sealant surrounds and is in contact with the liquid crystal layer. The first light-shielding pattern is disposed on the first substrate, wherein a portion of the sidewall of the first light-shielding pattern is substantially aligned with a portion of the sidewall of the first substrate, and the first light-shielding pattern is only overlapped with an outer edge of the photo-curable sealant or is not overlapped with the photo-curable sealant. | 02-02-2012 |
20120135181 | SUBSTRATE STRUCTURE AND PANEL STRUCTURE - A substrate structure including an upper surface, a lower surface and a plurality of side surfaces is provided. The lower surface is opposite to the upper surface. The side surfaces connect to the upper surface and the lower surface. Each side surface has a perpendicular surface, a first corner surface and a second corner surface. The perpendicular surface is perpendicular to the upper surface and the lower surface. The first corner surface is located between the perpendicular surface and the upper surface. The second corner surface is located between the perpendicular surface and the lower surface. The roughness of the first corner surface and the second corner surface are smaller than or equal to that of the perpendicular surface. | 05-31-2012 |
20120171425 | DISPLAY PANEL - A display panel has a display region and a peripheral region that surrounds the display region. The display panel includes a first substrate, a second substrate, a display medium, and a sealant. The first substrate has a first trench in the peripheral region, and the first trench has at least one sidewall. The second substrate is located opposite to the first substrate. The display medium is located between the first substrate and the second substrate. The sealant is located in the peripheral region between the first substrate and the second substrate. Specifically, the sealant is located in the first trench, and a distance between a sidewall of the sealant and the sidewall of the first trench ranges from about 0 um to about 700 um. | 07-05-2012 |
20150132531 | SUBSTRATE STRUCTURE AND PANEL STRUCTURE - A substrate structure including an upper surface, a lower surface and a plurality of side surfaces is provided. The lower surface is opposite to the upper surface. The side surfaces connect to the upper surface and the lower surface. Each side surface has a perpendicular surface, a first corner surface and a second corner surface. The perpendicular surface is perpendicular to the upper surface and the lower surface. The first corner surface is located between the perpendicular surface and the upper surface. The second corner surface is located between the perpendicular surface and the lower surface. The roughness of the first corner surface and the second corner surface are smaller than or equal to that of the perpendicular surface. | 05-14-2015 |
Patent application number | Description | Published |
20100295583 | Apparatus for awaking an electronic device from a standby mode - An apparatus is used to awake an electronic device to an active mode from a standby mode in case of change in the voltage of a power supply of the electronic device. The apparatus includes a power supply for supplying electricity, a switch connected to the power supply, a low-voltage reset unit connected to the switch, a micro-controller unit connected to the switch and a monitoring and awaking unit. The monitoring and awaking unit includes an actuator connected to the switch, a bias generator connected to the actuator and a comparator connected to the bias generator. The control over the power supply by the switch causes change in the voltage of the actuator which cooperates with the bias generator and the comparator to generate an awaking signal to awake the micro-processing unit. | 11-25-2010 |
20110050436 | Wakeup Device Detecting Voltage Variation in Standby Mode - A resume device is provided. The device detects voltage variation in standby mode. When a big voltage variation is detected, a resume process is run and a sound is played. Volume of the sound is adjustable and power is maintained within a proper range. Thus, power consumption is saved, efficiency is improved and resume process is enhanced. | 03-03-2011 |
20150028895 | INTEGRATABLE CAPACITIVE TOUCH SENSING CIRCUIT THROUGH CHARGE SHARING - An integratable capacitive touch sensing circuit through charge sharing is provided, including a charge sharing circuit, voltage-controlled oscillator, reference frequency generator, switch clock generator and frequency compare circuit; wherein charge sharing circuit further including a sensing capacitor, touch capacitor, share capacitor, charging switch, charge sharing switch and discharging switch, for sharing charge from charged sensing capacitor with discharged share capacitor through charge sharing to accumulate voltage on share capacitor. The capacitance of share capacitor is adjustable for applications generating different sensing capacitance. The charging switch, charge sharing switch and discharging switch are controlled by non-overlapping clocks. Prolonging close duration of charging switch and minimizing close duration of charge sharing switch and discharging switch can minimize interference from ambient noise. The charge sharing circuit finishes charge sharing in a clock cycle and voltage of share capacitor are linear to sensing capacitance and touch capacitance. | 01-29-2015 |
Patent application number | Description | Published |
20110291200 | INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF - An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure. | 12-01-2011 |
20130130456 | INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF - A method of forming an integrated circuit including forming a first diffusion area and a second diffusion area on a substrate, wherein the first diffusion area is configured for a first type transistor, the second diffusion area is configured for a second type transistor. The method further includes forming first source and drain regions in the first diffusion area. The method further includes forming second source and drain regions in the second diffusion area. The method further includes forming a gate electrode extending across the first diffusion area and the second diffusion area. The method further includes forming a first metallic layer, a second metallic layer, and a third metallic layer. The first metallic layer is electrically coupled with the first source region. The second metallic layer is electrically coupled with the first and second drain regions. The third metallic layer is electrically coupled with the second source region. | 05-23-2013 |
20140195997 | METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT - An integrated circuit layout includes a P-type active region, an N-type active region, a first metal connection, a second metal connection and a plurality of trunks. The plurality of trunks is formed substantially side-by-side, and in parallel with each other. The first metal connection is substantially disposed over the P-type active region, and is electrically connected with drain regions of PMOS transistors in the P-type active region. The second metal connection is substantially disposed over the N-type active region, and is electrically connected with drain regions of NMOS transistors in the N-type active region. The plurality of trunks is electrically connected with and is substantially perpendicular to the first metal connection and the second metal connection. A first trunk of the plurality of trunks has a width wider than a width of other trunks of the plurality of trunks and is arranged to be located between two groups of trunks. | 07-10-2014 |
20140327050 | STANDARD CELL HAVING CELL HEIGHT BEING NON-INTEGRAL MULTIPLE OF NOMINAL MINIMUM PITCH - An integrated circuit, manufactured by a process having a nominal minimum pitch of metal lines, includes a plurality of metal lines and a plurality of standard cells under the plurality of metal lines. The plurality of metal lines extends along a first direction, and the plurality of metal lines are separated, in a second direction perpendicular to the first direction, by integral multiples of the nominal minimum pitch. At least one of the plurality of standard cells has a cell height along the second direction, and the cell height is a non-integral multiple of the nominal minimum pitch. | 11-06-2014 |
20140327081 | STANDARD CELL METAL STRUCTURE DIRECTLY OVER POLYSILICON STRUCTURE - A semiconductor structure includes a first active area structure, an isolation structure surrounding the first active area structure, a first polysilicon structure, a first metal structure, and a second metal structure. The first polysilicon structure is over the first active area structure. The first metal structure is directly over a first portion of the first active area structure. The second metal structure is directly over and in contact with a portion of the first polysilicon structure and in contact with the first metal structure. | 11-06-2014 |
20140327471 | STANDARD CELLS FOR PREDETERMINED FUNCTION HAVING DIFFERENT TYPES OF LAYOUT - An integrated circuit is manufactured by a predetermined manufacturing process having a nominal minimum pitch of metal lines. The integrated circuit includes a plurality of metal lines extending along a first direction and a plurality of standard cells under the plurality of metal lines. The plurality of metal lines is separated, in a second direction perpendicular to the first direction, by integral multiples of the nominal minimum pitch. The plurality of standard cells includes a first standard cell configured to perform a predetermined function and having a first layout and a second standard cell configured to perform the predetermined function and having a second layout different than the first layout. The first and second standard cells have a cell height (H) along the second direction, and the cell height being a non-integral multiple of the nominal minimum pitch. | 11-06-2014 |
20140332971 | METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT - An integrated circuit layout includes a P-type active region and an N-type active region, and a plurality of trunks. The integrated circuit layout further includes a first metal connection connected to the P-type active region; and a second metal connection connected to the N-type active region. Each trunk of the plurality of trunks is electrically connected with the first metal connection and the second metal connection. Each trunk of the plurality of trunks is substantially perpendicular to the first metal connection and the second metal connection. A first trunk of the plurality of trunks has a width wider than a width of other trunks of the plurality of trunks. | 11-13-2014 |
20150035070 | METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT - An integrated circuit layout includes a first active region, a second active region, a first PODE (poly on OD edge), a second PODE, a first transistor and a second transistor. The first transistor, on the first active region, includes a gate electrode, a source region and a drain region. The second transistor, on the second active region, includes a gate electrode, a source region and a drain region. The first active region and the second active region are adjacent and electrically disconnected with each other. The first PODE and the second PODE are on respective adjacent edges of the first active region and the second active region. The source regions of the first and second transistor are adjacent with the first PODE and the second PODE respectively. The first PODE and the second PODE are sandwiched between source regions of the first transistor and the second transistor. | 02-05-2015 |
20150048424 | STANDARD CELL LAYOUT, SEMICONDUCTOR DEVICE HAVING ENGINEERING CHANGE ORDER (ECO) CELLS AND METHOD - A layout of a standard cell is stored on a non-transitory computer-readable medium and includes a first conductive pattern, a second conductive pattern, a plurality of active area patterns and a first central conductive pattern. The plurality of active area patterns is isolated from each other and arranged in a first row and a second row between the first and second conductive patterns. The first row is adjacent the first conductive pattern and includes a first active area pattern and a second active area pattern among the plurality of active area patterns. The second row is adjacent the second conductive pattern and includes a third active area pattern and a fourth active area pattern among the plurality of active area patterns. The first central conductive pattern is arranged between the first and second active area patterns. The first central conductive pattern overlaps the first conductive pattern. | 02-19-2015 |
20150162295 | CONNECTING TECHNIQUES FOR STACKED CMOS DEVICES - A stacked integrated circuit includes multiple tiers vertically connecting together. A multi-layer horizontal connecting structure is fabricated inside a substrate of a tier. Layers of the horizontal connecting structure have different patterns as viewed from above the substrate. | 06-11-2015 |
Patent application number | Description | Published |
20120092806 | PROTECTION STRUCTURE FOR METAL-OXIDE-METAL CAPACITOR - A capacitor structure includes first and second sets of electrodes and a plurality of line plugs. The first set of electrodes has a first electrode and a second electrode formed in a first metallization layer among a plurality of metallization layers, wherein the first electrode and the second electrode are separated by an insulation material. The second set of electrodes has a third electrode and a fourth electrode formed in a second metallization layer among the plurality of metallization layers, wherein the third electrode and the fourth electrode are separated by the insulation material. The line plugs connect the second set of electrodes to the first set of electrodes. | 04-19-2012 |
20120119306 | METAL GATE TRANSISTOR, INTEGRATED CIRCUITS, SYSTEMS, AND FABRICATION METHODS THEREOF - A method of forming an integrated circuit structure includes providing a gate strip in an inter-layer dielectric (ILD) layer. The gate strip comprises a metal gate electrode over a high-k gate dielectric. An electrical transmission structure is formed over the gate strip and a conductive strip is formed over the electrical transmission structure. The conductive strip has a width greater than a width of the gate strip. A contact plug is formed above the conductive strip and surrounded by an additional ILD layer. | 05-17-2012 |
20130161739 | DUMMY GATE FOR A HIGH VOLTAGE TRANSISTOR DEVICE - A semiconductor device and methods for forming the same are provided. The semiconductor device includes a first doped region and a second, oppositely doped, region both formed in a substrate, a first gate formed overlying a portion of the first doped region and a portion of the second doped region, two or more second gates formed over the substrate overlying a different portion of the second doped region, one or more third doped regions in the second doped region disposed only between the two or more second gates such that the third doped region and the second doped region having opposite conductivity types, a source region in the first doped region, and a drain region in the second doped region disposed across the second gates from the first gate. | 06-27-2013 |
20140264618 | ISOLATION STRUCTURE - A structure comprises a p-type substrate, a deep n-type well and a deep p-type well. The deep n-type well is adjacent to the p-type substrate and has a first conductive path to a first terminal. The deep p-type well is in the deep n-type well, is separated from the p-type substrate by the deep n-type well, and has a second conductive path to a second terminal. A first n-type well is over the deep p-type well. A first p-type well is over the deep p-type well. | 09-18-2014 |
20140361367 | SEMICONDUCTOR DEVICE HAVING A DOUBLE DEEP WELL AND METHOD OF MANUFACTURING SAME - A semiconductor device includes a substrate having a first type doping. The semiconductor device further includes a first deep well in the substrate, the first deep well having a second type doping. The semiconductor device further includes a second deep well in the substrate, the second deep well having the second type doping and being separated and above the first deep well. The semiconductor device further includes a first well over the second deep well, the first well having the first type doping and a gate structure over the first well. | 12-11-2014 |
20150155096 | METHOD OF FORMING CAPACITOR STRUCTURE - A method of forming a capacitor structure includes forming a first set of electrodes having a first electrode and a second electrode, wherein each electrode of the first set of electrodes has an L-shaped portion. The method further includes forming a second set of electrodes having a third electrode and a fourth electrode, wherein each electrode of the second set of electrodes has an L-shaped portion. The method further includes forming insulation layers between the first set of electrodes and the second set of electrodes. The method further includes forming a first L-shaped line plug connecting the first electrode to the third electrode, wherein an entirety of an outer surface of the first L-shaped line plug is recessed with respect to an outer surface of the L-shaped portion of the first electrode. The method further includes forming a second line plug connecting the second electrode to the fourth electrode. | 06-04-2015 |
20150162198 | SEMICONDUCTOR DEVICE HAVING A DOUBLE DEEP WELL AND METHOD OF MANUFACTURING SAME - A method of forming a semiconductor device includes patterning a first mask over a substrate defining a first opening. The substrate includes a first dopant type. The method includes implanting ions having a second dopant type through the first opening to form a first deep well. The method includes patterning a second mask over the substrate defining a second opening. The method includes implanting ions having the second dopant type through the second opening to form a second deep well, wherein an energy for implanting ions to form the second deep well is lower than an energy for implanting ions to form the first deep well. The method includes implanting ions having the first dopant type into the substrate to form a first well, wherein the energy for implanting ions to form the second deep well is greater than an energy for implanting ions to form the first well. | 06-11-2015 |
Patent application number | Description | Published |
20130015877 | METHOD AND APPARATUS FOR TESTING A SEMICONDUCTOR DEVICEAANM Shao; Jhih JieAACI Toufen TownshipAACO TWAAGP Shao; Jhih Jie Toufen Township TWAANM Huang; Szu-ChiaAACI Hsinchu CityAACO TWAAGP Huang; Szu-Chia Hsinchu City TWAANM Chung; Tang-HsuanAACI Kaohsiung CityAACO TWAAGP Chung; Tang-Hsuan Kaohsiung City TWAANM Tseng; Huan ChiAACI Hsinchu CityAACO TWAAGP Tseng; Huan Chi Hsinchu City TW - The present disclosure provides a method for testing a semiconductor device. The method includes providing a testing unit and an electronic circuit coupled to the testing unit and applying a first electrical signal to the testing unit. The method includes sweeping a second electrical signal across a range of values, the second electrical signal supplying power to the electronic circuit, wherein the sweeping is performed while a value of the first electrical signal remains the same. The method includes measuring a third electrical signal during the sweeping, the measured third electrical signal having a range of values that each correspond to one of the values of the second electrical signal. The method includes adopting an optimum value of the second electrical signal that yields a minimum value of the third electrical signal. The method includes testing the testing unit while the second electrical signal is set to the optimum value. | 01-17-2013 |
20130027075 | METHOD AND APPARATUS FOR TESTING A SEMICONDUCTOR DEVICE - The present disclosure provides an apparatus testing a semiconductor device. The apparatus includes a plurality of testing pads. The apparatus includes a plurality of testing units. The apparatus includes a switching circuit coupled between the testing pads and the testing units. The switching circuit contains a plurality of switching devices. The apparatus includes a control circuit coupled to the switching circuit. The control circuit is operable to establish electrical coupling between a selected testing unit and one or more of the testing pads by selectively activating a subset of the switching devices. | 01-31-2013 |
20130057306 | METHOD AND APPARATUS FOR TESTING A SEMICONDUCTOR DEVICE - The present disclosure provides a method for testing a semiconductor device. The method includes providing a test unit and an electronic circuit that is electrically coupled to the test unit. The method includes performing a multi-dimensional sweeping process. The multi-dimensional sweeping process includes sweeping a plurality of different electrical parameters across their respective ranges. The method includes monitoring a performance of the electronic circuit during the multi-dimensional sweeping process. The monitoring includes identifying optimum values of the different electrical parameters that yield a satisfactory performance of the electronic circuit. The method includes testing the test unit using the optimum values of the different electrical parameters. | 03-07-2013 |
20130139120 | COMPUTER IMPLEMENTED SYSTEM AND METHOD FOR LEAKAGE CALCULATION - A tool includes one or more machine readable storage mediums encoded with data. The data include a list of standard cells included in an integrated circuit (IC) design The data include a nominal leakage value approximating a respective median leakage value for each of the plurality of standard cells at a predetermined temperature and voltage. The data include at least one table including adjustment factors for calculating leakage based on voltage, temperature and process variations. The table includes a respective statistical scaling factor, for computing a mean leakage corresponding to a given median leakage. A processor is programmed to calculate and output a total IC leakage for the IC design at an input voltage and input temperature, based on the list, the nominal leakage values, the input voltage, the input temperature and at least one of the adjustment factors. | 05-30-2013 |
20140002127 | Method and Apparatus for Testing a Semiconductor Device | 01-02-2014 |
20150095869 | METHOD OF MAKING SEMICONDUCTOR DEVICE AND A CONTROL SYSTEM FOR PERFORMING THE SAME - A method of making a semiconductor device includes arranging a first cell and a second cell, determining, by a processor, a first pattern density of a first cell, determining a second pattern density of a second cell, determining a pattern density gradient from the first pattern density to the second pattern density, determining whether the pattern density gradient exceeds a pattern density gradient threshold, and indicating a design change if the pattern density gradient exceeds than the pattern density gradient threshold. | 04-02-2015 |
20150161318 | METHOD OF MAKING SEMICONDUCTOR DEVICE AND SYSTEM FOR PERFORMING THE SAME - A method of making a semiconductor device includes determining, by a processor, a first pattern density of a first region, determining a second pattern density of a second region, determining a pattern density gradient from the first region to the second region, determining whether the pattern density gradient exceeds a pattern density gradient threshold and performing a placement or a routing of the semiconductor device if the pattern density gradient is less than or equal to the pattern density gradient threshold. | 06-11-2015 |
20150268271 | MULTIDIRECTIONAL SEMICONDUCTOR ARRANGEMENT TESTING - One or more probe cards, wafer testers, and techniques for testing a semiconductor arrangement are provided. Testline arrangements are formed within scribe lines of a semiconductor wafer, in multiple directions, such as an x-direction and a y-direction. A wafer tester is configured to concurrently test the semiconductor arrangement in multiple directions using a multidirectional probe arrangement of a probe card. In some embodiments, a first pin arrangement of the multidirectional probe arrangement is mated with a first testline arrangement in a first direction, and a second pin arrangement of the multidirectional probe arrangement is mated with a second testline arrangement in a second direction. The wafer tester concurrently tests the semiconductor arrangement in multiple directions, such as in the first direction and the second direction, through the pin arrangements mated with the testline arrangements. | 09-24-2015 |
Patent application number | Description | Published |
20080284319 | WHITE LIGHT ORGANIC ELECTROLUMINESCENT ELEMENT - A white light organic electroluminescent element is provided. The white organic electroluminescent element comprises an anode, a hole transporting layer on the anode, an orange light emitting layer on the hole transporting layer, a blue light emitting layer on the orange light emitting layer, an electron transporting layer on the blue light emitting layer, and a cathode on the electron transporting layer, wherein the orange light emitting layer is formed by co-evaporation of a host-emitting material, a blue guest-emitting material, and an orange guest-emitting material. | 11-20-2008 |
20090017295 | FLUORINATED CYCLIC OLEFIN ELECTRET FILM - The present invention provides a fluorinated cyclic olefin electret film including a fluorinated cyclic olefin polymer film characterized by having a cyclic olefin polymer grafted with a fluorocarbon alkyl group, and a parylene film over the fluorinated cyclic olefin polymer film. | 01-15-2009 |
20100019658 | ORGANIC COMPOUND AND ORGANIC ELECTROLUMINESCENCE DEVICE EMPLOYING THE SAME - Organic compounds and organic electroluminescence devices employing the same are provided. The organic compound has a chemical structure represented as follows: | 01-28-2010 |
20110285275 | ORGANOMETALLIC COMPOUND, ORGANIC ELECTROLUMINESCENCE DEVICE AND COMPOSITION EMPLOYING THE SAME - Organometallic compounds and organic electroluminescence devices and compositions employing the same are provided. The organic metal compound has a chemical structure represented by formula (I) or formula (II): | 11-24-2011 |
20120001537 | ORGANIC COMPOUND AND ORGANIC ELECTROLUMINESCENCE DEVICE EMPLOYING THE SAME - Organic compounds and organic electroluminescence devices employing the same are provided. The organic compound has a chemical structure represented as follows: | 01-05-2012 |
20130105767 | CARBAZOLE DERIVATIVES AND ORGANIC LIGHT EMITTING DIODES COMPRISING THE SAME | 05-02-2013 |
20140097412 | BRIGHTNESS ENHANCED SELF-LUMINOUS DISPLAY - A brightness enhanced self-luminous type display including a self-luminous display panel and a brightness enhancement stacked layer is provided. The self-luminous display panel includes pixels arranged in array, wherein each pixel includes light-emitting sub-pixels displaying different colors. The brightness enhancement stacked layer is disposed on the self-luminous display panel. The brightness enhancement stacked layer includes an absorptive polarizer layer, a phase retardation layer and a reflective polarizer layer. The reflective polarizer layer is between the self-luminous display panel and the phase retardation layer. The phase retardation layer is between the absorptive polarizer layer and the reflective polarizer layer. The reflective polarizer layer includes reflective polarizer blocks arranged in array. Each reflective polarizer block is disposed over one of the light-emitting sub-pixels correspondingly, and a wavelength of maximum intensity of each light-emitting sub-pixel is respectively within a wavelength band of light effectively reflected and polarized by the corresponding reflective polarizer block. | 04-10-2014 |
20140166993 | ORGANIC LIGHT EMITTING DIODE - Disclosed is an organic light emitting diode (OLED), including a flexible substrate having a surface with a bulge and groove structure. The OLED also includes a first electrode on the flexible substrate, an organic light emitting layer on the first electrode, and a second electrode on the organic light emitting layer. The flexible substrate includes polyimide. | 06-19-2014 |
20150123082 | ORGANOMETALLIC COMPOUND, ORGANIC LIGHT-EMITTING DEVICE, AND LIGHTING DEVICE EMPLOYING THE SAME - Organometallic compounds, organic light-emitting devices, and lighting devices employing the same are provided. The organometallic compound has a chemical structure represented by formula (I) or (II): | 05-07-2015 |
Patent application number | Description | Published |
20130246732 | METHOD OF PROGRAMMING MEMORY CELLS AND READING DATA, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS USING THE SAME - A method of programming memory cells for a rewritable non-volatile memory module is provided. The method includes: receiving a command which indicates performing an update operation to a logical page; and identifying valid logical access addresses and invalid logical access addresses in the logical page according to the command. The method also includes: selecting a physical page; setting flags corresponding to the valid logical access addresses in a valid state, setting flags corresponding to the invalid logical access in an invalid state; programming the flags and data belonging to the valid logical access addresses to the selected physical page based on the update operation; and mapping the selected physical page to the logical page. Accordingly, the method can effectively increase the speed of programming the memory cells. | 09-19-2013 |
20140101367 | CONTROLLING METHOD FOR CONNECTOR, CONNECTOR AND MEMORY STORAGE DEVICE - A controlling method for connector is provided, which includes: receiving a first signal stream under a condition that a squelch detector is turned-off; determining whether the first signal stream contains a burst signal under a first operating frequency; if the first signal stream contains the burst signal, turning on the squelch detector and determining by the squelch detector under a second operating frequency whether a second signal stream is a waking signal, wherein the second signal stream is received after receiving the first signal stream and the second operating frequency is greater than the first operating frequency. The controlling method further includes: if the second signal stream is the waking signal, changing an operating state of the connector to an active state. In this way, the power consumption of the connector is reduced. | 04-10-2014 |
20140192608 | CONTROLLING METHOD OF CONNECTOR, CONNECTOR, AND MEMORY STORAGE DEVICE - A controlling method of a connector, the connector, and a memory storage device are provided. The controlling method includes following steps. A first clock signal generated by a first oscillator in the connector is obtained. A second clock signal generated by a second oscillator in the connector is obtained. A frequency shift of the first oscillator is smaller than a frequency shift of the second oscillator. A detection window information corresponding to the second clock signal is corrected according to the first clock signal and the second clock signal. The first oscillator is turned off. A signal stream including a first signal is received. A detection window is generated according to the corrected detection window information and the second clock signal, and whether the first signal is a burst signal is determined according to the detection window. Thereby, the power consumption of the connector is reduced. | 07-10-2014 |
20140223076 | CONTROLLING METHOD, CONNECTOR, AND MEMORY STORAGE DEVICE - A controlling method, a connector, and a memory storage device are provided. The controlling method includes following steps. A connection between the memory storage device and a host system is established. A first command is received from the host system and stored into a command queue. The command queue includes at least one second command after the first command is stored into the command queue. Whether a command number of the second commands is greater than a threshold is determined. The threshold is greater than 1. If the command number is greater than the threshold, a using right of the connection is obtained and a second command is executed by the memory storage device. If the command number is not greater than the threshold, a command from the host system is waited for. The using right of the connection belongs to the host system. Thereby, the system efficiency is improved. | 08-07-2014 |
20150039909 | COMMAND EXECUTING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS - A command executing method for a memory storage apparatus is provided. The method includes grouping logical addresses into logical address groups and assigning a key for each of the logical address groups independently. The method also includes receiving a write command and write data corresponding to the write command and temporarily storing the write data into a buffer memory. The method further includes executing the write command, enabling a direct memory access once to transfer the write data from the buffer memory to a writable non-volatile memory module of the memory apparatus and encrypting each sector data of the write data with keys corresponding to the logical address groups that the logical address storing the sector data belong to. | 02-05-2015 |
20150095663 | DATA PROCESSING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT - A data processing method, a memory storage device, and a memory control circuit unit are provided. Here, each physical address corresponds to one flag. The data processing method includes: receiving a reading command; reading first data stored in the physical addresses of a physical programming unit; determining whether a first flag in the physical programming unit is in a first status or a second status; transmitting decrypted first data or decrypted specific-format data to a host system according to whether the first flag is in the first status or the second status. Accordingly, the encryption operation may be simplified. | 04-02-2015 |
Patent application number | Description | Published |
20090310717 | SIGNAL CONVERTERS - A signal converter. The signal converter converts an analog inphase signal and an analog quasdrature phase signal into a digital baseband inphase signal and a digital baseband quadrature phase signal. The analog inphase signal and the analog quadrature phase signal are orthogonal to each other and are carried in a predetermined intermediate frequency. The digital baseband inphase signal and the digital baseband quadrature phase signal are carried in zero frequency. The signal converter comprises a signal combiner combining the analog inphase signal and the analog quadrature phase signal to obtain an analog combined signal, an analog to digital converter converting the analog combined signal to a digital combined signal, and a signal separator separating the digital combined signal to obtain the digital baseband inphase signal and the digital baseband quadrature phase signal. | 12-17-2009 |
20110009060 | Systems and Methods for Reducing Interference Between a Plurality of Wireless Communications Modules - A wireless communications system is provided with a first wireless communications and a second wireless communications. The first wireless communications module transmits or receives a first wireless signal in a first frequency band selected from a first frequency range. The second wireless communications module transmits or receives a second wireless signal in a second frequency band selected from a second frequency range, and adjusts a transmission power of the second wireless signal in response to that a frequency offset between the first frequency band and the second frequency band falls within a predetermined range. | 01-13-2011 |
20110051635 | COMMUNICATION METHODS EMPLOYED IN COMMUNICATION SYSTEM ASSOCIATED WITH PROGRAMMABLE COMMUNICATION PROTOCOLS, AND RELATED TRANSMITTING METHODS, RECEIVING METHODS AND COMMUNICATION DEVICE - A communication method employed in a wireless communication system including a first communication device and a second communication device is provided. The communication method includes: setting up a connection between the first and second communication devices; after the connection is set up, checking if both the first and second communication devices provide a symbol mapping function for converting a first modulation/demodulation to a second modulation/demodulation different from the first modulation/demodulation; and when both the first and second communication devices provide the symbol mapping function, using the second modulation/demodulation to replace the first modulation/demodulation so that each of the first and second communication devices communicates with each other by using the second modulation/demodulation. | 03-03-2011 |
20110255413 | Communication Apparatus and ID Packet Recognition Method Thereof - A communication apparatus is provided. The communication apparatus includes an RF module and a scan module coupled to the RF module. The RF module receives an RF signal and generates an intermediary signal corresponding to the RF signal. The scan module recognizes a time-domain pattern corresponding to the intermediary signal, and determines whether the RF signal comprises an ID packet according to the recognized time-domain pattern. | 10-20-2011 |
20110255414 | Communication Apparatus and Bluetooth ID Packet Recognition Method Thereof - A communication apparatus is provided. The communication apparatus includes an RF module, a down converter coupled to the RF module and a detector coupled to the down converter. The RF module receives an RF signal. The down converter down converts the RF signal in response to a channel select signal to generate a converted signal, wherein the channel select signal controls the down converter to alternately sweep a plurality of scan trains during a scan frame, and each of the scan trains comprises a plurality of channels. The power detector determines whether the RF signal comprises an ID packet according to the converted signal corresponding to the channels of the plurality of scan trains. | 10-20-2011 |
20120033762 | METHOD FOR DYNAMICALLY ADJUSTING ONE OR MORE RF PARAMETERS AND COMMUNICATIONS APPARATUSE UTILIZING THE SAME - A communications apparatus is provided. A radio frequency (RF) circuit is arranged to receive an RF signal from an antenna and process the RF signal according to one or more RF parameters to generate an intermediate signal. A signal processing unit is arranged to process the intermediate signal to generate a processed signal and generates signal processing information regarding requirements for processing the intermediate signal. An RF circuit controller is coupled to the RF circuit and the signal processing unit and arranged to dynamically adjust the RF parameters according to the signal processing information. | 02-09-2012 |
20120034891 | METHOD FOR DYNAMICALLY ADJUSTING SIGNAL PROCESSING PARAMETERS FOR PROCESSING WANTED SIGNAL AND COMMUNICATIONS APPARATUS UTILIZING THE SAME - A communications apparatus is provided. A signal processing device receives an RF signal comprising a wanted signal complying with a first wireless communications protocol from an air interface and processes the RF signal according to one or more signal processing parameter(s) to obtain the wanted signal. An interference detector analyzes one or more characteristic(s) of an interference signal of the wanted signal. The interference signal complies with a second wireless communications protocol different from the first wireless communication protocol. A coexistence optimization controller is coupled to the signal processing device and the interference detector, obtains information regarding the characteristic(s) of the interference signal from the interference detector and dynamically adjusts the signal processing parameter(s) according to the characteristic(s) of the interference signal. | 02-09-2012 |
20140254634 | SYSTEMS AND METHODS FOR REDUCING INTERFERENCE BETWEEN A PLURALITY OF WIRELESS COMMUNICATIONS MODULES - A wireless communications includes a first wireless communications and a second wireless communications. The first wireless communications module transmits or receives a first wireless signal in a first frequency band selected from a first frequency range. The second wireless communications module transmits or receives a second wireless signal in a second frequency band selected from a second frequency range, and adjusts a transmission power of the second wireless signal in response to that a frequency offset between the first frequency band and the second frequency band falls within a predetermined range. The first wireless communications module is further configured to determine an in-band range in the overlapping part of the first and second frequency ranges, and a transmission power of the second wireless signal is adjusted in response to a frequency offset between the first frequency band and the second frequency band. | 09-11-2014 |
20150195783 | COMMUNICATION APPARATUS AND BLUETOOTH ID PACKET RECOGNITION METHOD THEREOF - A communication apparatus is provided. The communication apparatus includes an RF module for receiving an RF signal, and a down converter, coupled to the RF module, for down converting the RF signal in response to a channel select signal to generate a converted signal. The channel select signal controls the down converter to sweep a plurality of scan trains during a scan frame, and each of the scan trains comprises a plurality of channels, wherein a total channel number of the plurality of scan trains is N, where 32≦N≦78. The communication apparatus also includes a detector, coupled to the down converter, for determining whether the RF signal comprises an ID packet according to the converted signal corresponding to the channels of the plurality of scan trains. | 07-09-2015 |
Patent application number | Description | Published |
20090215316 | SOCKET FOR FAIRY LIGHT - A socket for a fairy light has a light-emitting diode (LED) recess being formed in an outer end of the socket and a partition being formed on a bottom of the LED recess. Any LED can be mounted on the partition and protrude out of the socket. Therefore, the LED recess will not limit a lighting range of the LED, and the fairy light with small LEDs saves manufacturing costs and energy. | 08-27-2009 |
20090318027 | LIGHT-EMITTING DIODE AND A FAIRY LIGHT WITH THE LIGHT-EMITTING DIODE - A light-emitting diode (LED) has a body and two terminals protruding from a bottom of the body. Each terminal has at least one distal and proximal positioning protrusions. A fairy light of the LED has a casing, two wires being mounted in the casing and a partition being mounted between the wires. The distal and proximal positioning protrusions of the terminals of the LED hold insulating shells and electric cords of the wires. Thus, the LED is easily, securely and stably to be electrically connected to the wires so an assembling procedure can be done with automatic machines. Furthermore, the LED is held in position with the partition being mounted between the wires. Therefore, not only assembling processes but also assembling components of the LED and the fairy light with the LED are saved. Consequently, manufacturing costs are saved. | 12-24-2009 |
20100097790 | Lamp - A lamp has a socket and a holder having a plug and a lens. The plug has a top surface, a light emitting diode (LED) mount and an LED. The LED mount is formed centrally on the top surface of the plug. The LED is mounted in the LED mount of the holder. The lens is mounted around the LED mount and has at least one auxiliary lens and a holding lens. Each auxiliary lens has an annulus and multiple decorative protrusions. The holding lens is mounted through the annulus of the auxiliary lens. Therefore, the holding lens and at least one auxiliary lens are manufactured individually to reduce manufacturing costs and complexity and attain easily adaptable designs. | 04-22-2010 |
20130322087 | WATERPROOF FAIRY LIGHT - A waterproof fairy light has a housing, a socket and a lighting assembly. The housing has an assembling hole defined therein. The socket is mounted in the assembling hole and has a cavity defined through the socket and having an inner surface and a partition formed in the cavity on the inner surface, dividing the cavity into two spaces and having two opposite side edges formed integrally on the inner surface of the cavity so that no gap is formed between each side edge and the inner surface. The lighting assembly is mounted in the cavity of the socket and has a lighting element and two contacting pins. The integrally formed partition prevents rain from contacting both the contacting pins and causing short circuit. | 12-05-2013 |