Patent application number | Description | Published |
20100268906 | HIGH BANDWIDTH MEMORY INTERFACE - This invention describes an improved high bandwidth chip-to-chip interface for memory devices, which is capable of operating at higher speeds, while maintaining error free data transmission, consuming lower power, and supporting more load. Accordingly, the invention provides a memory subsystem comprising at least two semiconductor devices; a main bus containing a plurality of bus lines for carrying substantially all data and command information needed by the devices, the semiconductor devices including at least one memory device connected in parallel to the bus; the bus lines including respective row command lines and column command lines; a clock generator for coupling to a clock line, the devices including clock inputs for coupling to the clock line; and the devices including programmable delay elements coupled to the clock inputs to delay the clock edges for setting an input data sampling time of the memory device. | 10-21-2010 |
20130134607 | INTERPOSER FOR STACKED SEMICONDUCTOR DEVICES - A semiconductor device is disclosed, comprising a substrate having at least one substrate bonding pad. A plurality of semiconductor dies are stacked on the substrate. Each semiconductor die has at least one die bonding pad located on an active surface of the die. A plurality of interposers are each mounted on a corresponding one of the semiconductor dies. Each interposer has an aperture formed therethrough in alignment with the at least one die bonding pad. An electrical connection between the at least one die bonding pad and the at least one substrate bonding pad is formed at least in part by the interposer. The electrical connection includes at least one wire bond. | 05-30-2013 |
20130169343 | USING INTERRUPTED THROUGH-SILICON-VIAS IN INTEGRATED CIRCUITS ADAPTED FOR STACKING - In an integrated circuit (IC) adapted for use in a stack of interconnected ICs, interrupted through-silicon-vias (TSVs) are provided in addition to uninterrupted TSVs. The interrupted TSVs provide signal paths other than common parallel paths between the ICs of the stack. This permits IC identification schemes and other functionalities to be implemented using TSVs, without requiring angular rotation of alternate ICs of the stack. | 07-04-2013 |
20130309810 | MULTI-CHIP PACKAGE WITH OFFSET DIE STACKING AND METHOD OF MAKING SAME - A semiconductor device has a plurality of stacked semiconductor dice mounted on a substrate. Each die has similar dimensions. Each die has a first plurality of bonding pads arranged along a bonding edge of the die. A first group of the dice are mounted to the substrate with the bonding edge oriented in a first direction. A second group of the dice are mounted to the substrate with the bonding edge oriented in a second direction opposite the first direction. Each die is laterally offset in the second direction relative to the remaining dice by a respective lateral offset distance such that the bonding pads of each die are not disposed between the substrate and any portion of the remaining dice in a direction perpendicular to the substrate. A plurality of bonding wires connects the bonding pads to the substrate. A method of manufacturing a semiconductor device is also disclosed. | 11-21-2013 |
20130322173 | CONFIGURABLE MODULE AND MEMORY SUBSYSTEM - A configurable memory subsystem includes a memory module with a circuit board having a first and a second memory-containing device (MCD) pair mounted thereto. Each MCD pair has a first MCD in communication with a second MCD. Each MCD has an input port, an output port, and a memory each communicating with a bridge. In response to a command, the bridge transfers at least one of a portion of a data packet from the input port to the output port or to the memory, or transfers a portion of a memory packet from the memory to the output port. A loop-back device receives the command and the data packet form the first MCD pair and transmits the command and data packet to the second MCD pair. | 12-05-2013 |
20130326090 | RING TOPOLOGY STATUS INDICATION - A semiconductor device includes a bridging device having an external data interface, an external status interface, and a plurality of internal data interfaces. A plurality of memory devices are each connected to the bridging device via one of the internal data interfaces. Each of the memory devices has a ready/busy output connected to an input of the bridging device. The bridging device is configured to output a current state of each ready/busy output in a packetized format on the external status interface in response to a status request command received on the external status interface; and read information from a status register of a selected memory device over one of the internal data interfaces and provide the information on the external data interface in response to a status read command received on the external data interface. A method of operating a semiconductor device is also disclosed. | 12-05-2013 |
20130343125 | APPARATUS AND METHODS FOR CARRYING OUT OPERATIONS IN A NON-VOLATILE MEMORY CELL HAVING MULTIPLE MEMORY STATES - Apparatus and methods for carrying out operations in a non-volatile memory cell having multiple memory states are disclosed. One of the methods is a method for programming N bits in a non-volatile memory cell configured to store up to N+1 bits, where N is an integer greater than zero. The method for programming includes programming N bits of data in the cell. The method for programming also includes programming an additional bit of data that is a logical function of the N bits of data in the cell. The cell is configured to provide 2N+1 threshold voltage ranges for bit storage and, in accordance with the logical function: i) a first set of 2N threshold voltage ranges of the 2N+1 threshold voltage ranges are used to store the N bits of data; and ii) a remaining second set of 2N threshold voltage ranges alternating with the first set are unused. | 12-26-2013 |
20140119136 | METHOD AND APPARATUS FOR SHARING INTERNAL POWER SUPPLIES IN INTEGRATED CIRCUIT DEVICES - A method, system and apparatus for sharing internal power supplies in integrated circuit devices is described. A multiple device integrated circuit | 05-01-2014 |
Patent application number | Description | Published |
20090039927 | CLOCK MODE DETERMINATION IN A MEMORY SYSTEM - A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device. | 02-12-2009 |
20090316514 | Delay Locked Loop Implementation in a Synchronous Dynamic Random Access Memory - A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal. | 12-24-2009 |
20100049870 | DENSE MODE CODING SCHEME - A lookup table for searching for a longest prefix match for a key is disclosed. The lookup table provides a match for a key in a single search cycle. The number of matches stored in the lookup table is maximized by storing each match in only one location in the lookup table. The binary tree is divided into a plurality of levels and each level has a plurality of subtrees. A subtree descriptor stored for a subtree includes a field for each node in the subtree. The state of the field indicates whether an entry for the node is stored in the table. The bit vector allows indexing of the single match stored for the key. | 02-25-2010 |
20100115172 | BRIDGE DEVICE HAVING A VIRTUAL PAGE BUFFER - A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. The bridge device has a virtual page buffer corresponding to each discrete memory device for storing read data from the discrete memory device, or write data from an external device. The virtual page buffer is configurable to have a size up to the maximum physical size of the page buffer of a discrete memory device. The page buffer is then logically divided into page segments, where each page segment corresponds in size to the configured virtual page buffer size. By storing read or write data in the virtual page buffer, both the discrete memory device and the external device can operate to provide or receive data at different data rates to maximize the performance of both devices. | 05-06-2010 |
20110050320 | USING INTERRUPTED THROUGH-SILICON-VIAS IN INTEGRATED CIRCUITS ADAPTED FOR STACKING - In an integrated circuit (IC) adapted for use in a stack of interconnected ICs, interrupted through-silicon-vias (TSVs) are provided in addition to uninterrupted TSVs. The interrupted TSVs provide signal paths other than common parallel paths between the ICs of the stack. This permits IC identification schemes and other functionalities to be implemented using TSVs, without requiring angular rotation of alternate ICs of the stack. | 03-03-2011 |
20110317704 | DENSE MODE CODING SCHEME - A lookup table for searching for a longest prefix match for a key is disclosed. The lookup table provides a match for a key in a single search cycle. The number of matches stored in the lookup table is maximized by storing each match in only one location in the lookup table. The binary tree is divided into a plurality of levels and each level has a plurality of subtrees. A subtree descriptor stored for a subtree includes a field for each node in the subtree. The state of the field indicates whether an entry for the node is stored in the table. The bit vector allows indexing of the single match stored for the key. | 12-29-2011 |
20120056335 | MULTI-CHIP PACKAGE WITH OFFSET DIE STACKING - A semiconductor device has a plurality of stacked semiconductor dice mounted on a substrate. Each die has similar dimensions. Each die has a first plurality of bonding pads arranged along a bonding edge of the die. A first group of the dice are mounted to the substrate with the bonding edge oriented in a first direction. A second group of the dice are mounted to the substrate with the bonding edge oriented in a second direction opposite the first direction. Each die is laterally offset in the second direction relative to the remaining dice by a respective lateral offset distance such that the bonding pads of each die are not disposed between the substrate and any portion of the remaining dice in a direction perpendicular to the substrate. A plurality of bonding wires connects the bonding pads to the substrate. A method of manufacturing a semiconductor device is also disclosed. | 03-08-2012 |
20120127798 | METHOD AND APPARATUS FOR SHARING INTERNAL POWER SUPPLIES IN INTEGRATED CIRCUIT DEVICES - A method, system and apparatus for sharing internal power supplies in integrated circuit devices is described. A multiple device integrated circuit | 05-24-2012 |
20130121096 | Delay Locked Loop Implementation In A Synchronous Dynamic Random Access Memory - A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal. | 05-16-2013 |
20130249592 | TERMINATION CIRCUIT FOR ON-DIE TERMINATION - In a semiconductor device having a terminal connected to an internal portion, a termination circuit for providing on-die termination for the terminal of the device. The termination circuit comprises a plurality of transistors, including at least one NMOS transistor and at least one PMOS transistor, connected between the terminal and a power supply; and control circuitry for driving a gate of each of NMOS transistor with a corresponding NMOS gate voltage and for driving a gate of each PMOS transistor with a corresponding PMOS gate voltage, the control circuitry being configured to control the NMOS and PMOS gate voltages so as to place the transistors in an ohmic region of operation when on-die termination is enabled. The power supply supplies a voltage that is less than each said NMOS gate voltage and greater than each said PMOS gate voltage. | 09-26-2013 |
20140104969 | Delay Locked Loop Implementation In A Synchronous Dynamic Random Access Memory - A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal. | 04-17-2014 |
Patent application number | Description | Published |
20100327923 | BRIDGING DEVICE HAVING A FREQUENCY CONFIGURABLE CLOCK DOMAIN - A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. A configurable clock controller receives a system clock and generates a memory clock having a frequency that is a predetermined ratio of the system clock. The system clock frequency is dynamically variable between a maximum and a minimum value, and the ratio of the memory clock frequency relative to the system clock frequency is set by loading a frequency register with a Frequency Divide Ratio (FDR) code any time during operation of the composite memory device. In response to the FDR code, the configurable clock controller changes the memory clock frequency. | 12-30-2010 |
20110016279 | SIMULTANEOUS READ AND WRITE DATA TRANSFER - A controller for an arrangement of memory devices may issue a write command without waiting for the receipt of a previously issued read command. An addressed memory device may read data out onto the data bus according to a read command while, simultaneously, writing data according to a write command received subsequent to the read command. | 01-20-2011 |
20120087182 | PHASE-CHANGE MEMORY WITH MULTIPLE POLARITY BITS HAVING ENHANCED ENDURANCE AND ERROR TOLERANCE - A Phase-Change Memory (PCM) apparatus including a data field for storing a data bits representing a data value or an inversion of the data value and a polarity field for storing a plurality of polarity bits for indicating that the data bits stored in the data field represent the data value or the inversion of the data value. In one embodiment an odd number of set polarity bits indicates that the data bits represent the inversion of the data value and an even number of set polarity bits indicates that the data bits represent the data value. The PCM apparatus has enhanced endurance and improved error tolerance. | 04-12-2012 |
20130132761 | MEMORY MODULE INCLUDING A PLURALITY OF SYNCHRONOUS MEMORY DEVICES - A memory module that includes a buffer and a plurality of synchronous memory devices. The memory module also includes bidirectional bus lines, and each of the synchronous memory devices has bidirectional data terminals. The buffer is configured to regenerate signals received on the bus lines for receipt by the synchronous memory devices, and to regenerate signals received from any one of the synchronous memory devices for receipt by the bus lines. The memory module may further include command lines and a clock line for providing commands and a clock signal to the synchronous memory devices via a command buffer. The combined data bus width of the memory module may be greater than the data bus width of any single one of synchronous memory device, and the total address space provided by the memory module may be larger than the data space for any single synchronous memory device. | 05-23-2013 |
20130215677 | PHASE-CHANGE MEMORY WITH MULTIPLE POLARITY BITS HAVING ENHANCED ENDURANCE AND ERROR TOLERANCE - A Phase-Change Memory (PCM) apparatus including a data field for storing a data bits representing a data value or an inversion of the data value and a polarity field for storing a plurality of polarity bits for indicating that the data bits stored in the data field represent the data value or the inversion of the data value. In one embodiment an odd number of set polarity bits indicates that the data bits represent the inversion of the data value and an even number of set polarity bits indicates that the data bits represent the data value. The PCM apparatus has enhanced endurance and improved error tolerance. | 08-22-2013 |
20130235659 | CLOCK MODE DETERMINATION IN A MEMORY SYSTEM - A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device. | 09-12-2013 |
20130318287 | BRIDGING DEVICE HAVING A FREQUENCY CONFIGURABLE CLOCK DOMAIN - A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. A configurable clock controller receives a system clock and generates a memory clock having a frequency that is a predetermined ratio of the system clock. The system clock frequency is dynamically variable between a maximum and a minimum value, and the ratio of the memory clock frequency relative to the system clock frequency is set by loading a frequency register with a Frequency Divide Ratio (FDR) code any time during operation of the composite memory device. In response to the FDR code, the configurable clock controller changes the memory clock frequency. | 11-28-2013 |
20130329482 | HIGH BANDWIDTH MEMORY INTERFACE - A memory module that includes a buffer and a plurality of synchronous memory devices. The memory module also includes bidirectional bus lines, and each of the synchronous memory devices has bidirectional data terminals. The buffer is configured to regenerate signals received on the bus lines for receipt by the synchronous memory devices, and to regenerate signals received from any one of the synchronous memory devices for receipt by the bus lines. The memory module may further include command lines and a clock line for providing commands and a clock signal to the synchronous memory devices via a command buffer. The combined data bus width of the memory module may be greater than the data bus width of any single one of synchronous memory device, and the total address space provided by the memory module may be larger than the data space for any single synchronous memory device. | 12-12-2013 |
20140013041 | SIMULTANEOUS READ AND WRITE DATA TRANSFER - A controller for an arrangement of memory devices may issue a write command without waiting for the receipt of a previously issued read command. An addressed memory device may read data out onto the data bus according to a read command while, simultaneously, writing data according to a write command received subsequent to the read command. | 01-09-2014 |
20140019705 | BRIDGING DEVICE HAVING A CONFIGURABLE VIRTUAL PAGE SIZE - A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. The bridge device has memory organized as banks, where each bank is configured to have a virtual page size that is less than the maximum physical size of the page buffer. Therefore only a segment of data corresponding to the virtual page size stored in the page buffer is transferred to the bank. The virtual page size of the banks is provided in a virtual page size (VPS) configuration command having an ordered structure where the position of VPS data fields containing VPS configuration codes in the command correspond to different banks which are ordered from a least significant bank to a most significant bank. The VPS configuration command is variable in size, and includes only the VPS configuration codes for the highest significant bank being configured and the lower significant banks. | 01-16-2014 |
20140133243 | CLOCK MODE DETERMINATION IN A MEMORY SYSTEM - A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device. | 05-15-2014 |
20140293705 | ASYNCHRONOUS BRIDGE CHIP - A memory device multi-chip package containing conventional parallel bus flash memory dies interfacing to an external parallel bus having the same format and protocol. A bridge chip within the memory device interfaces internally over one or more internal parallel bus interfaces to the flash dies within the package. The bridge chip presents a single load on the external bus interface so that several memory device multi-chip packages (MCPs) can be connected to a controller, thereby increasing the number of flash dies supported by a single controller channel operating at full performance. | 10-02-2014 |
20150019936 | ERROR DETECTION METHOD AND A SYSTEM INCLUDING ONE OR MORE MEMORY DEVICE - In accordance with various embodiments, a memory device and method of error detection and correction are disclosed. A memory device may include an input for receiving a command packet including an error detection code to facilitate command error detection. The memory device may include an error manager configured to detect, based on the error detection code, whether an error occurred in transmission of the command packet, a command register configured to store the command packet and configured to provide the command packet to the error manager, and an output to transmit the command packet to a subsequent device of the point-to-point ring topology. | 01-15-2015 |
20150078057 | HIGH BANDWIDTH MEMORY INTERFACE - A memory module that includes a buffer and a plurality of synchronous memory devices. The memory module also includes bidirectional bus lines, and each of the synchronous memory devices has bidirectional data terminals. The buffer is configured to regenerate signals received on the bus lines for receipt by the synchronous memory devices, and to regenerate signals received from any one of the synchronous memory devices for receipt by the bus lines. The memory module may further include command lines and a clock line for providing commands and a clock signal to the synchronous memory devices via a command buffer. The combined data bus width of the memory module may be greater than the data bus width of any single one of synchronous memory device, and the total address space provided by the memory module may be larger than the data space for any single synchronous memory device. | 03-19-2015 |