Patent application number | Description | Published |
20140065828 | SELECTIVE FIN CUT PROCESS - A process is provided for selective removal of one or more unwanted fins during FINFET device fabrication. In one aspect, the process includes: providing a conformal protective layer over multiple fin structures on a substrate; patterning one or more openings over the unwanted fin structure(s); and removing at least a top portion of the unwanted fin structure(s) exposed through the opening(s), the removing including removing at least a portion of the conformal protective layer over the unwanted fin structure(s) exposed through the opening(s). In enhanced aspects, the removing includes removing a hard mask from the at least one unwanted fin structure(s) exposed through the opening(s), and selectively removing semiconductor material of at least one unwanted fin structure(s). The conformal protective layer protects one or more remaining fin structures during the selective removal of the semiconductor material of the unwanted fin structure(s). | 03-06-2014 |
20140179093 | GATE STRUCTURE FORMATION PROCESSES - Gate structures and methods of fabricating gate structures of semiconductor devices are provided. One method includes, for instance: providing a sacrificial layer over a substrate; patterning the sacrificial layer to form a gate opening within the sacrificial layer; providing a gate structure within the gate opening in the sacrificial layer; and removing the sacrificial layer, leaving the gate structure over the substrate. In enhanced aspects, the method includes: forming a reverse sidewall-spacer within the gate opening within the sacrificial layer, and after providing the gate structure, recessing the gate structure within the gate opening, and providing a gate cap within the gate recess in the gate structure. | 06-26-2014 |
20140199845 | SELECTIVE REMOVAL OF GATE STRUCTURE SIDEWALL(S) TO FACILITATE SIDEWALL SPACER PROTECTION - Methods are provided for facilitating fabricating a semiconductor device by selectively etching a gate structure sidewall(s) to facilitate subsequent sidewall spacer isolation. The method includes, for instance: providing a gate structure with a protective layer(s) over the gate structure, the gate structure including one or more sidewalls; selectively removing a portion of the gate structure along at least one sidewall to partially undercut the protective layer(s); and forming a sidewall spacer(s) over the sidewall(s) of the gate structure, with a portion of the sidewall spacer at least partially filling the partial undercut of the protective layer(s), and residing below the protective layer(s). In certain embodiments, the selectively removing includes implanting the sidewall(s) with a dopant to produce a doped region(s) of the gate structure, and subsequently, at least partially removing the doped region(s) of the gate structure selective to an undoped region of the gate structure. | 07-17-2014 |
20140291735 | DOUBLE PATTERNING VIA TRIANGULAR SHAPED SIDEWALL SPACERS - An intermediate semiconductor structure in fabrication includes a silicon semiconductor substrate, a hard mask of silicon nitride (SiN) over the substrate and a sacrificial layer of polysilicon or amorphous silicon over the hard mask. The sacrificial layer is patterned into sidewall spacers for mandrels of a filler material substantially different in composition from the sidewall spacers, such as a flowable oxide. The mandrels are removed such that the sidewall spacers have vertically tapered inner and outer sidewalls providing a rough triangular shape. The rough triangular sidewall spacers are used as a hard mask to pattern the SiN hard mask below. | 10-02-2014 |
20150115418 | DEVICES AND METHODS OF FORMING FINS AT TIGHT FIN PITCHES - Devices and methods for forming semiconductor devices with fins at tight fin pitches are provided. One method includes, for instance: obtaining an intermediate semiconductor device; growing an epi layer over the substrate; forming a doped layer below the epi layer; depositing a first oxide layer on the epi layer; applying a dielectric material on the first oxide layer; and depositing a lithography stack on the dielectric material. One intermediate semiconductor device includes, for instance: a substrate with at least one n-well region and at least one p-well region; a doped layer over the substrate; an epi layer over the doped layer; a first oxide layer over the epi layer; a dielectric layer over the first oxide layer; and a lithography stack over the dielectric layer. | 04-30-2015 |
20150132962 | FACILITATING MASK PATTERN FORMATION - Mask pattern formation is facilitated by: providing a mask structure including at least one sacrificial spacing structure disposed above a substrate structure; disposing a spacer layer conformally over the mask structure; selectively removing the spacer layer, leaving, at least in part, sidewall spacers along sidewalls of the at least one sacrificial spacing structure, and providing at least one additional sacrificial spacer over the substrate structure, one additional sacrificial spacer of the at least one additional sacrificial spacer being disposed in set spaced relation to the at least one sacrificial spacing structure; and removing the at least one sacrificial spacing structure, leaving the sidewall spacers and the at least one additional sacrificial spacer over the substrate structure as part of a mask pattern. | 05-14-2015 |
20150255353 | FORMING SOURCE/DRAIN REGIONS WITH SINGLE RETICLE AND RESULTING DEVICE - Methods for forming FinFET source/drain regions with a single reticle and the resulting devices are disclosed. Embodiments may include forming a first fin and a second fin above a substrate, forming a gate crossing over the first fin and the second fin, removing portions of the first fin and the second fin on both sides the gate, forming silicon phosphorous tops on the first fin and the second fin in place of the portions, removing the silicon phosphorous tops on the first fin, and forming silicon germanium tops on the first fin in place of the silicon phosphorous tops. | 09-10-2015 |
20150270175 | PARTIALLY CRYSTALLIZED FIN HARD MASK FOR FIN FIELD-EFFECT-TRANSISTOR (FINFET) DEVICE - Provided herein are approaches for forming a fin field-effect-transistor (FinFET) device using a partially crystallized fin hard mask. Specifically, a hard mask is patterned over a substrate, and the FinFET device is annealed to form a set of crystallized hard mask elements adjacent a set of non-crystallized hard mask elements. A masking structure is provided over a first section of the patterned hard mask to prevent the set of non-crystallized hard mask elements from being crystallized during the anneal. During a subsequent fin cut process, the non-crystallized mask elements are removed, while crystallized mask elements remain. A set of fins is then formed in the FinFET device according to the location(s) of the crystallized mask elements. | 09-24-2015 |
20150279684 | METHOD OF FORMING SEMICONDUCTOR FINS - Embodiments of the present invention provide methods of removing fin portions from a finFET. At a starting point, a high-K dielectric layer is disposed on a substrate. A fin hardmask and lithography stack is deposited on the high-k dielectric. A fin hardmask is exposed, and a first portion of the fin hardmark is removed. The lithography stack is removed. A second portion of the fin hardmask is removed. Fins are formed. A gap fill dielectric is deposited and recessed. | 10-01-2015 |
20150287595 | DEVICES AND METHODS OF FORMING FINS AT TIGHT FIN PITCHES - Devices and methods for forming semiconductor devices with fins at tight fin pitches are provided. One method includes, for instance: obtaining an intermediate semiconductor device; growing an epi layer over the substrate; forming a doped layer below the epi layer; depositing a first oxide layer on the epi layer; applying a dielectric material on the first oxide layer; and depositing a lithography stack on the dielectric material. One intermediate semiconductor device includes, for instance: a substrate with at least one n-well region and at least one p-well region; a doped layer over the substrate; an epi layer over the doped layer; a first oxide layer over the epi layer; a dielectric layer over the first oxide layer; and a lithography stack over the dielectric layer. | 10-08-2015 |
20160005868 | FINFET WITH CONFINED EPITAXY - Embodiments of the present invention provide a fin-type field effect transistor (finFET) with confined epitaxy. A protective layer is formed on a fin. The protective layer is recessed to expose the fin top. A fin cavity is formed in the fin. An epitaxial region is formed in the fin cavity. The epitaxial region has a confined portion and a diamond-shaped portion, resulting in increased epitaxial volume. The increased epitaxial volume can result in enhanced carrier mobility and improved device performance. | 01-07-2016 |
Patent application number | Description | Published |
20090194936 | METHOD AND APPARATUS FOR RELIEVING STRESS IN A PRE-REGISTRATION NIP - A method of using a buckle for relieving the stresses in sheets caused by differential displacements of drive nips during the registration process includes creating a buckle between pre-registration nips and registration nips. The velocities of the pre-registration nips and registration nips are closely controlled so that the magnitude of buckle between them is large enough to relieve the stresses in the sheet during the registration process, yet small enough to not interfere with the registration process. | 08-06-2009 |
20100096795 | FRICTION RETARD FEEDER WITH IMPROVED SHEET SEPARATION - A substrate feeding apparatus and a printing machine is provided herein for feeding substrates from a substrate stack having a nudger roll being selectively movable between a first position and a second position. In the first position, the nudger roll is in contiguous contact with a first substrate of the substrate stack for advancing the first substrate from the substrate stack. The first substrate having a lead edge and a trail edge, with the lead edge leading in a direction of advancement. In the second position, the nudger roll is not in contiguous contact with the substrate stack or the first substrate. A feed roll for further advancing the first substrate in the direction of advancement. A retard member forming a nip with the feed roll. The retard member is used for separating the first substrate from an adjacent second substrate. A guide baffle extending between the substrate stack and the nip, with the guide baffle configured to contact, and to guide, the first substrate as it advances in the direction of advancement from the nudger roll to the nip. The guide baffle provides an angular change in direction to the first substrate as the first substrate advances from the substrate stack to the nip. The guide baffle is configured such that as the lead edge of the first substrate enters the nip, the first substrate has portions thereof spaced from the guide baffle, with the spaced portions sagging towards the guide baffle to provide the first substrate with a concave profile. The nudger roll moves from the first position to the second position after the lead edge of the first substrate enters the nip. | 04-22-2010 |
20110089627 | GATE SYSTEM DIVERTING SHEETS INTO MULTI-WAYS - According to aspects illustrated herein, there are provided systems for conveying a sheet article into an intended pathway. The multi-way gate system for diverting sheets into multiple pathways in a sheet conveying device includes at least three pathways for directing the sheet from the sheet conveying member in a particular direction. A single gate plate is between the sheet conveying member and the pathways. The single gate plate is rotatable about a single axis to direct the sheet exiting the sheet conveying member toward one of the pathways. | 04-21-2011 |
20110135371 | Printing system architecture with center cross-over and interposer by-pass path - A printing system comprises a paper path architecture for parallel printing using multiple marking engines. The media path configuration enables all the media feed trays to be located in one place, relative to the marking engines. A cross-over module is located between marking engines. The cross-over module can interleave media sheets that are being transported away from a first marking engine with the sheets being transported to the second marking engine. The cross-over module also includes a straight through path that enables media sheets to be transported directly to a finishing device without going through either marking engine. The marking engines include internal duplex loops such that media can be supplied to each engine in alternate groups. A merge module selectively merges the media which can then be further processed in a finishing transition module prior to communication to a finishing device. | 06-09-2011 |
20120032389 | GATE SYSTEM DIVERTING SHEETS INTO MULTI-WAYS - According to aspects illustrated herein, there are provided systems for conveying a sheet article into an intended pathway. The multi-way gate system for diverting sheets into multiple pathways in a sheet conveying device includes at least three pathways for directing the sheet from the sheet conveying member in a particular direction. A single gate plate is between the sheet conveying member and the pathways. The single gate plate is rotatable about a single axis to direct the sheet exiting the sheet conveying member toward one of the pathways. | 02-09-2012 |
20120098879 | SUBSTRATE MEDIA REGISTRATION SYSTEM AND METHOD IN A PRINTING SYSTEM - Embodiments described herein include a substrate media registration system in a printing system. The registration system can include a deskewing system, a reflexive system, and a controller. The deskewing system is configured to deskew substrate media. The reflexive system is configured to detect the lateral position of the substrate media and at least one of a lead edge and a trail edge of the substrate media being transported in the process direction. The controller is operatively coupled to the reflexive system and is configured to control ejection of ink from a print head system in response to detecting the lateral position of the substrate media and at least one of the lead edge and the trail edge of the substrate media. | 04-26-2012 |
20130200564 | INVERTER WITH ADJUSTABLE REVERSING ROLL POSITION - A reversing apparatus within a media path comprises an input nip moving sheets of media in a first direction, and a reversing nip positioned to receive the sheets of media from the input nip. The reversing nip stops the sheets and moves the sheets in a second direction opposite the first direction. Also included is an output nip positioned to receive the sheets of media from the reversing nip, and an actuator connected to the reversing nip. The actuator moves the reversing nip relative to a position of the input nip and the output nip, based on a characteristic of the sheets of media. | 08-08-2013 |
20130207341 | MEDIA CURLING APPARATUS AND SYSTEMS INCLUDING TRI-ROLL MEDIA CURLER - A tri-roll curler apparatus includes an inlet roll, and exit roll, and a penetrating roll. The three rolls have substantially equal radii. At least one of the penetrating roll, and the inlet and exit rolls may be movable. Distances between the penetrating roll and the inlet roll, and the penetrating roll and the exit roll are substantially equal. | 08-15-2013 |
20130209152 | QUAD-ROLL MEDIA CURLING APPARATUS, SYSTEMS, AND METHODS - A quad-roll curler apparatus includes a first roll, a second roll, a third roll, and a fourth roll. The curler apparatus is adjustable to a first processing configuration wherein three of the four rolls are engaged to impart a curl in a sheet in a first direction. The curler apparatus is adjustable to a second sheet processing configuration wherein three of the four rolls are engaged to impart a curl in a sheet in a second direction that is different from the first direction. | 08-15-2013 |
Patent application number | Description | Published |
20090039441 | MOSFET WITH METAL GATE ELECTRODE - Devices comprising, and method for fabricating, a MOSFET with a metal gate electrode are disclosed. In one embodiment, the MOSFET includes a first doped region configured to receive current from a current source, a second doped region configured to drain current from the first doped region when an electric field is modified between the first doped region and the second doped region, and a gate electrode configured to modify the electric field. The gate electrode may include a high-k layer, a hafnium-based metal layer formed above the high-k layer, and a polysilicon layer formed above the hafnium-based metal layer. In a further embodiment, the gate electrode further comprises a titanium-based metal layer formed between the hafnium-based metal layer and the polysilicon layer. | 02-12-2009 |
20090108294 | SCALABLE HIGH-K DIELECTRIC GATE STACK - A stack comprising a dielectric interface layer, a high-k gate dielectric layer, a group IIA/IIIB element layer is formed in that order on a semiconductor substrate. A metal aluminum nitride layer and, optionally, a semiconductor layer are formed on the stack. The stack is annealed at a raised temperature, e.g., at about 1,000° C. so that the materials in the stack are mixed to form a mixed high-k gate dielectric layer. The mixed high-k gate dielectric layer is doped with a group IIA/IIIB element and aluminum, and has a lower effective oxide thickness (EOT) than a conventional gate stack containing no aluminum. The inventive mixed high-k gate dielectric layer is amenable to EOT scaling due to the absence of a dielectric interface layer, which is caused by scavenging, i.e. consumption of any dielectric interface layer, by the IIA/IIB elements and aluminum. | 04-30-2009 |
20090294867 | DUAL METAL GATES USING ONE METAL TO ALTER WORK FUNCTION OF ANOTHER METAL - Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process. | 12-03-2009 |
20100193896 | METHOD FOR NITRIDATION OF SHALLOW TRENCH ISOLATION STRUCTURE TO PREVENT OXYGEN ABSORPTION - A method for forming an isolation structure includes forming a trench in a semiconductor layer. At least a portion of the trench is filled with a dielectric material including oxygen. A region comprising nitrogen is formed in at least an upper portion of the dielectric material. | 08-05-2010 |
20100213553 | METAL OXIDE SEMICONDUCTOR DEVICES HAVING BURIED GATE CHANNELS AND METHODS FOR FABRICATING THE SAME - Methods for forming a semiconductor device comprising a semiconductor substrate are provided. In accordance with an exemplary embodiment, a method comprises forming a channel layer overlying the semiconductor substrate, forming a channel capping layer having a first surface overlying the channel layer, oxidizing the first surface of the channel capping layer, and depositing a high-k dielectric layer overlying the channel capping layer. | 08-26-2010 |
20100213555 | METAL OXIDE SEMICONDUCTOR DEVICES HAVING CAPPING LAYERS AND METHODS FOR FABRICATING THE SAME - Methods for forming a semiconductor device comprising a semiconductor substrate are provided. In accordance with an exemplary embodiment, a method comprises forming a silicon oxide layer overlying the semiconductor substrate, forming a metal oxide gate capping layer overlying the silicon oxide layer, depositing a first metal gate electrode layer overlying the metal oxide gate capping layer, and removing a portion of the first metal gate electrode layer and the metal oxide gate capping layer to form a gate stack. | 08-26-2010 |
20100301401 | SEMICONDUCTOR DEVICE AND RELATED FABRICATION METHODS THAT USE COMPRESSIVE MATERIAL WITH A REPLACEMENT GATE TECHNIQUE - A semiconductor device and related method of fabricating it are provided. An exemplary fabrication process begins by forming a gate structure overlying a layer of semiconductor material, the gate structure comprising a gate insulator overlying the layer of semiconductor material and comprising a temporary gate element overlying the gate insulator. The process continues by forming a layer of compressive material overlying the gate structure, and by removing a first portion of the compressive material to expose an upper surface of the temporary gate element, while leaving a second portion of the compressive material intact and external to sidewalls of the temporary gate element. Thereafter, at least a portion of the temporary gate element is removed, while leaving the second portion of the compressive material intact, resulting in a gate recess. The process continues by at least partially filling the gate recess with a gate electrode material. | 12-02-2010 |
20110198696 | FINNED SEMICONDUCTOR DEVICE WITH OXYGEN DIFFUSION BARRIER REGIONS, AND RELATED FABRICATION METHODS - A semiconductor device and related fabrication methods are provided. One exemplary fabrication method forms a fin arrangement overlying an oxide layer, where the fin arrangement includes one or more semiconductor fin structures. The method continues by nitriding exposed portions of the oxide layer without nitriding the one or more semiconductor fin structures, resulting in nitrided portions of the oxide layer. Thereafter, a gate structure is formed transversely overlying the fin arrangement, and overlying the exposed portions of the oxide layer. The nitrided portions of the oxide layer substantially inhibit diffusion of oxygen from the oxide layer into the gate structure. | 08-18-2011 |
20110309449 | INTERFACE-FREE METAL GATE STACK - A method of fabricating a gate stack for a transistor includes forming a high dielectric constant layer on a semiconductor layer. A metal layer is formed on the high dielectric constant layer. A silicon containing layer is formed over the metal layer. An oxidized layer incidentally forms during the silicon containing layer formation and resides on the metal layer beneath the silicon containing layer. The silicon containing layer is removed. The oxidized layer residing on the metal layer is removed after removing the silicon containing layer. | 12-22-2011 |
20120256270 | DUAL METAL GATES USING ONE METAL TO ALTER WORK FUNCTION OF ANOTHER METAL - Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process. | 10-11-2012 |
20130154019 | LOW THRESHOLD VOLTAGE CMOS DEVICE - A semiconductor device including an NMOS region and a PMOS region; the NMOS region having a gate structure including a first high-k gate dielectric, a first work function setting metal and a gate electrode fill material; the PMOS region having a gate structure comprising a second high-k gate dielectric, a second work function setting metal and a gate electrode fill material; wherein the first gate dielectric is different than the second gate dielectric and the first work function setting metal is different than the second work function setting metal. Also disclosed are methods for fabricating the semiconductor device which include a gate last process. | 06-20-2013 |
20130241007 | USE OF BAND EDGE GATE METALS AS SOURCE DRAIN CONTACTS - A method includes providing a semiconductor substrate having intentionally doped surface regions, the intentionally doped surface regions corresponding to locations of a source and a drain of a transistor; depositing a layer a band edge gate metal onto a gate insulator layer in a gate region of the transistor while simultaneously depositing the band edge gate metal onto the surface of the semiconductor substrate to be in contact with the intentionally doped surface regions; and depositing a layer of contact metal over the band edge gate metal in the gate region and in the locations of the source and the drain. The band edge gate metal in the source/drain regions reduces a Schottky barrier height of source/drain contacts of the transistor and serves to reduce contact resistance. A transistor fabricated in accordance with the method is also described. | 09-19-2013 |
20130241008 | Use of Band Edge Gate Metals as Source Drain Contacts - A device includes a gate stack formed over a channel in a semiconductor substrate. The gate stack includes a layer of gate insulator material, a layer of gate metal overlying the layer of gate insulator material, and a layer of contact metal overlying the layer band edge gate metal. The device further includes source and drain contacts adjacent to the channel. The source and drain contacts each include a layer of the gate metal that overlies and is in direct electrical contact with a doped region of the semiconductor substrate, and a layer of contact metal that overlies the layer of gate metal. | 09-19-2013 |
20130270646 | INTEGRATED CIRCUITS HAVING IMPROVED METAL GATE STRUCTURES AND METHODS FOR FABRICATING SAME - Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a PFET trench in a PFET region and an NFET trench in an NFET region of an interlayer dielectric material on a semiconductor surface. The NFET trench is partially filled with an N-type work function metal layer to define an inner cavity. The PFET trench and the inner cavity in the NFET trench are partially filled with a P-type work function metal layer to define a central void in each trench. In the method, the central voids are filled with a metal fill to form metal gate structures. A single recessing process is then performed to recess portions of each metal gate structure within each trench to form a recess in each trench above the respective metal gate structure. | 10-17-2013 |
20130277751 | INTERFACE-FREE METAL GATE STACK - A gate stack for a transistor is formed by a process including forming a high dielectric constant layer on a semiconductor layer. A metal layer is formed on the high dielectric constant layer. A silicon containing layer is formed over the metal layer. An oxidized layer incidentally forms during the silicon containing layer formation and resides on the metal layer beneath the silicon containing layer. The silicon containing layer is removed. The oxidized layer residing on the metal layer is removed after removing the silicon containing layer. | 10-24-2013 |
20130280901 | INTERFACE-FREE METAL GATE STACK - A non-transitory computer readable medium encoded with a program for fabricating a gate stack for a transistor is disclosed. The program includes instructions configured to perform a method. The method includes forming a high dielectric constant layer on a semiconductor layer. A metal layer is formed on the high dielectric constant layer. A silicon containing layer is formed over the metal layer. An oxidized layer incidentally forms during the silicon containing layer formation and resides on the metal layer beneath the silicon containing layer. The silicon containing layer is removed. The oxidized layer residing on the metal layer is removed after removing the silicon containing layer. | 10-24-2013 |
20130292744 | INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME HAVING A REPLACEMENT GATE STRUCTURE - An integrated circuit includes a first replacement gate structure. The first replacement gate structure includes a layer of a first barrier material that is less than 20 Å in thickness and a layer of a p-type workfunction material. The replacement gate structure is less than about 50 nm in width. | 11-07-2013 |
20130299922 | INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME HAVING A REPLACEMENT GATE STRUCTURE - Integrated circuits and methods of fabricating integrated circuits are provided herein. In an embodiment, a method of fabricating an integrated circuit includes depositing a layer of a high-k dielectric material; depositing a layer of a work function shifter material over a portion of the high-k dielectric material to form an overlapping region; heat treating the layer of the high-k dielectric material and the layer of the work function shifter material to as to form a transformed dielectric material via thermal diffusion that is a combination of the high-k dielectric and work function shifter materials in the overlapping region; and depositing a layer of a first replacement gate fill material to obtain multiple threshold voltages. | 11-14-2013 |
20140051240 | METHODS OF FORMING A REPLACEMENT GATE STRUCTURE HAVING A GATE ELECTRODE COMPRISED OF A DEPOSITED INTERMETALLIC COMPOUND MATERIAL - Disclosed herein are various methods of forming a replacement gate structure with a gate electrode comprised of a deposited intermetallic compound material. In one example, the method includes removing at least a sacrificial gate electrode structure to define a gate cavity, forming a gate insulation layer in the gate cavity, performing a deposition process to deposit an intermetallic compound material in the gate cavity above the gate insulation layer, and performing at least one process operation to remove portions of intermetallic compound material positioned outside of the gate cavity. | 02-20-2014 |
20140124876 | METAL GATE STRUCTURE FOR MIDGAP SEMICONDUCTOR DEVICE AND METHOD OF MAKING SAME - A PFET-based semiconductor gate structure providing a midgap work function for threshold voltage control between that of a NFET and a PFET is created by including an annealed layer of relatively thick TiN to dominate and shift the overall work function down from that of PFET. The structure has a PFET base covered with a high-k dielectric, a layer of annealed TiN, a layer of unannealed TiN, a thin barrier over the unannealed TiN, and n-type metal over the thin barrier. | 05-08-2014 |
20140131808 | REPLACEMENT METAL GATE STRUCTURE FOR CMOS DEVICE - A method of fabricating a replacement metal gate structure for a CMOS device. The method includes forming a dummy gate structure on an nFET portion and a pFET portion of the CMOS device; depositing an interlayer dielectric between the dummy gate structures; removing the dummy gate structures from the nFET portion and the pFET portion, resulting in a recess on the nFET portion and a recess on the pFET portion; depositing a first layer of titanium nitride into the recesses on the nFET portion and pFET portion; removing the first layer of titanium nitride from the nFET portion only; depositing a second layer of titanium nitride into the recesses on the nFET portion and pFET portion; depositing a gate metal onto the second layer of titanium nitride in the recesses on the nFET portion and pFET portion to fill the remainder of the recesses. | 05-15-2014 |
20140131809 | REPLACEMENT METAL GATE STRUCTURE FOR CMOS DEVICE - A method of fabricating a replacement metal gate structure for a CMOS device including forming a dummy gate structure on an nFET portion and a pFET portion of the CMOS device; depositing an interlayer dielectric between the dummy gate structures; removing the dummy gate structures from the nFET and pFET portions, resulting in a recess on the nFET portion and a recess on the pFET portion; conformally depositing a gate dielectric into the recesses on the nFET and pFET portions; depositing sequential layers of a first titanium nitride, tantalum nitride and a second titanium nitride into the recesses on the nFET and pFET portions; removing the second layer of titanium nitride from the nFET portion only; depositing a third layer of titanium nitride into the recesses on the nFET and pFET portions; and filling the remainder of the cavity on the nFET and pFET portions with a metal. | 05-15-2014 |
20140141598 | METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE - A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; annealing the structure at a high temperature of not less than 800° C.; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill. Optionally, a second annealing step can be performed after the first anneal. This second anneal is performed as a millisecond anneal using a flash lamp or a laser. | 05-22-2014 |
20140231922 | SEMICONDUCTOR GATE STRUCTURE FOR THRESHOLD VOLTAGE MODULATION AND METHOD OF MAKING SAME - A gate structure of a semiconductor device having a NFET and a PFET, includes a lower layer of a hafnium-based dielectric over the gates of the NFET and PFET, and an upper layer of a lanthanide dielectric. The dielectrics are annealed to mix them above the NFET resulting in a lowered work function, and corresponding threshold voltage reduction. An annealed, relatively thick titanium nitride cap over the mixed dielectric above the NFET gate also lowers the work function and threshold voltage. Above the TiN cap and the hafnium-based dielectric over the PFET gate, is another layer of titanium nitride that has not been annealed. A conducting layer of tungsten covers the structure. | 08-21-2014 |
20140246734 | REPLACEMENT METAL GATE WITH MULITIPLE TITANIUM NITRIDE LATERS - A semiconductor comprising a multilayer structure which prevents oxidization of the titanium nitride layer that protects a high-K dielectric layer is provided. Replacement metal gates are over the multilayer structure. A sacrificial polysilicon gate structure is deposited first. The sacrificial polysilicon gate structure is then removed, and the various layers of the replacement metal gate structure are deposited in the space previously occupied by the sacrificial polysilicon gate structure. | 09-04-2014 |
20140367788 | METHODS OF FORMING GATE STRUCTURES FOR CMOS BASED INTEGRATED CIRCUIT PRODUCTS AND THE RESULTING DEVICES - One illustrative method disclosed herein includes forming gate insulation layers and a first metal layer for NMOS and PMOS devices from the same material, selectively forming a first metal layer only for the PMOS device, and forming different shaped metal silicide regions within the NMOS and PMOS gate cavities. A novel integrated circuit product disclosed herein includes an NMOS transistor with an NMOS gate insulation layer, an NMOS metal silicide having a generally rectangular cross-sectional configuration and an NMOS metal layer positioned on the NMOS metal silicide region. The product also includes a PMOS transistor with the same gate insulation material, a first PMOS metal and a PMOS metal silicide region, wherein the NMOS and PMOS metal silicide regions are comprised of the same metal silicide. | 12-18-2014 |
20140367790 | METHODS OF FORMING GATE STRUCTURES FOR CMOS BASED INTEGRATED CIRCUIT PRODUCTS AND THE RESULTING DEVICES - One illustrative method disclosed herein includes forming replacement gate structures for an NMOS transistor and a PMOS transistor by forming gate insulation layers and a first metal layer for the devices from the same materials and selectively forming a metal-silicide material layer only on the first metal layer for the NMOS device but not on the PMOS device. One example of a novel integrated circuit product disclosed herein includes an NMOS device and a PMOS device wherein the gate insulation layers and the first metal layer of the gate structures of the devices are made of the same material, the gate structure of the NMOS device includes a metal silicide material positioned on the first metal layer of the NMOS device, and a second metal layer that is positioned on the metal silicide material for the NMOS device and on the first metal layer for the PMOS device. | 12-18-2014 |
20150041905 | METHODS OF FORMING REPLACEMENT GATE STRUCTURES FOR TRANSISTORS AND THE RESULTING DEVICES - Disclosed herein are illustrative methods and devices that involve forming spacers with internally trimmed internal surfaces to increase the width of the upper portions of a gate cavity. In some embodiments, the internal surface of the spacer has a stepped cross-sectional configuration or a tapered cross-sectional configuration. In one example, a device is disclosed wherein the P-type work function metal for a PMOS device is positioned only within the lateral space defined by the untrimmed internal surfaces of the spacers, while the work function adjusting metal for the NMOS device is positioned laterally between the lateral spaces defined by both the trimmed and untrimmed internal surfaces of the sidewall spacers. | 02-12-2015 |
20150054087 | REPLACEMENT METAL GATE STRUCTURE FOR CMOS DEVICE - A CMOS device that includes an nFET portion, a pFET portion and an interlayer dielectric between the nFET portion and pFET portion. The nFET portion has a gate structure having a recess filled with a conformal high-k dielectric, a first titanium nitride layer on the high-k dielectric, a barrier layer on the first titanium nitride layer, a second titanium nitride layer in direct physical contact with the barrier layer and a gate metal filling the remainder of the recess. The pFET portion has a gate structure having a recess filled with a conformal high-k dielectric, a first titanium nitride layer on the high-k dielectric, a barrier layer on the first titanium nitride layer, a second titanium nitride layer on the barrier layer, a third titanium nitride layer in direct physical contact with the second titanium nitride layer and a gate metal filling the remainder of the recess. | 02-26-2015 |
20150061027 | METHODS OF FORMING GATE STRUCTURES FOR TRANSISTOR DEVICES FOR CMOS APPLICATIONS AND THE RESULTING PRODUCTS - One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities. | 03-05-2015 |
20150126020 | METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE - A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill. | 05-07-2015 |
20150126023 | METHODS OF FORMING GATE STRUCTURES WITH MULTIPLE WORK FUNCTIONS AND THE RESULTING PRODUCTS - One illustrative method disclosed herein includes removing sacrificial gate structures for NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, forming a high-k gate insulation layer in the NMOS and PMOS gate cavities, forming a lanthanide-based material layer on the high-k gate insulation layer in the NMOS and PMOS gate cavities, performing a heating process to drive material from the lanthanide-based material layer into the high-k gate insulation layer so as to thereby form a lanthanide-containing high-k gate insulation layer in each of the NMOS and PMOS gate cavities, and forming gate electrode structures above the lanthanide-containing high-k gate insulation layer in the NMOS and PMOS gate cavities. | 05-07-2015 |
20150126025 | INTERFACE-FREE METAL GATE STACK - A gate stack for a transistor is formed by a process including forming a high dielectric constant layer on a semiconductor layer. A metal layer is formed on the high dielectric constant layer. A silicon containing layer is formed over the metal layer. An oxidized layer incidentally forms during the silicon containing layer formation and resides on the metal layer beneath the silicon containing layer. The silicon containing layer is removed. The oxidized layer residing on the metal layer is removed after removing the silicon containing layer. | 05-07-2015 |
20150129972 | METHODS OF SCALING THICKNESS OF A GATE DIELECTRIC STRUCTURE, METHODS OF FORMING AN INTEGRATED CIRCUIT, AND INTEGRATED CIRCUITS - Methods of scaling thickness of a gate dielectric structure that overlies a semiconductor substrate, methods of forming an integrated circuit, and integrated circuits are provided. A method of scaling thickness of a gate dielectric structure that overlies a semiconductor substrate includes providing the semiconductor substrate. An interfacial oxide layer is formed in or on the semiconductor substrate. A high-k dielectric layer is formed over the interfacial oxide layer. An oxygen reservoir is formed over at least a portion of the high-k dielectric layer. A sealant layer is formed over the oxygen reservoir. The semiconductor substrate including the oxygen reservoir disposed thereon is annealed to diffuse oxygen through the high-k dielectric layer and the interfacial oxide layer from the oxygen reservoir. Annealing extends the interfacial oxide layer into the semiconductor substrate at portions of the semiconductor substrate that underlie the oxygen reservoir to form a regrown interfacial region in or on the semiconductor substrate. | 05-14-2015 |
20150179640 | COMMON FABRICATION OF DIFFERENT SEMICONDUCTOR DEVICES WITH DIFFERENT THRESHOLD VOLTAGES - A multi-device semiconductor structure including a p-type logic device, a p-type memory device, a n-type logic device and a n-type memory device are provided on a bulk silicon substrate. Each of these devices includes a dielectric layer and either a n-type or a p-type work function layer disposed over the dielectric layer. Some of the various device types of the multi-device semiconductor structure are protected, and impurities, such as aluminum and/or nitrogen, are added to the exposed work function layers to achieve one or more other desired work functions with different threshold voltages. | 06-25-2015 |
20150221749 | METHODS OF FORMING GATE STRUCTURES FOR SEMICONDUCTOR DEVICES USING A REPLACEMENT GATE TECHNIQUE AND THE RESULTING DEVICES - One method and device disclosed includes, among other things, forming a recessed sacrificial gate electrode having a recessed upper surface, performing at least one second etching process to define recessed sidewall spacers positioned adjacent the recessed sacrificial gate electrode, forming a plurality of sidewall spacers within a gate opening above the recessed sidewall spacers, wherein one of the spacers comprises a low-k insulating material that is positioned laterally between two other spacers and a gate cap layer, removing the recessed sacrificial gate electrode and forming a replacement gate structure in its place. | 08-06-2015 |
20150236135 | METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE - A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill. | 08-20-2015 |
20150243761 | METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE - A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill. | 08-27-2015 |
20150243762 | METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE - A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill. | 08-27-2015 |
20150263120 | REPLACEMENT GATE STRUCTURE WITH LOW-K SIDEWALL SPACER FOR SEMICONDUCTOR DEVICES - One method and device disclosed includes, among other things, forming a recessed sacrificial gate electrode having a recessed upper surface, performing at least one second etching process to define recessed sidewall spacers positioned adjacent the recessed sacrificial gate electrode, forming a plurality of sidewall spacers within a gate opening above the recessed sidewall spacers, wherein one of the spacers comprises a low-k insulating material that is positioned laterally between two other spacers and a gate cap layer, removing the recessed sacrificial gate electrode and forming a replacement gate structure in its place. | 09-17-2015 |
20150311206 | METHODS OF FORMING GATE STRUCTURES FOR TRANSISTOR DEVICES FOR CMOS APPLICATIONS AND THE RESULTING PRODUCTS - An integrated circuit product includes an NMOS transistor having a gate structure that includes an NMOS gate insulation layer, a first NMOS metal layer positioned on the NMOS gate insulation layer, an NMOS metal silicide material positioned above the first NMOS metal layer, and a layer of a second metal material positioned above and in contact with the NMOS gate insulation layer, the first NMOS metal layer, and the NMOS metal silicide layer. The PMOS transistor has a gate structure that includes a PMOS gate insulation layer, a first PMOS metal layer positioned on the PMOS gate insulation layer, a PMOS metal silicide material positioned above the first PMOS metal layer, and a layer of the second metal material positioned above and in contact with the PMOS gate insulation layer, the first PMOS metal layer, and the PMOS metal silicide layer. | 10-29-2015 |
20150348970 | GATE STRUCTURES FOR CMOS BASED INTEGRATED CIRCUIT PRODUCTS - An integrated circuit product includes an NMOS transistor having a gate structure comprised of an NMOS gate insulation layer comprised of a high-k gate insulation material, an NMOS metal silicide region positioned above the NMOS gate insulation layer, and an NMOS metal layer positioned on the NMOS metal silicide region, and a PMOS transistor having a gate structure comprised of a PMOS gate insulation layer comprised of the high-k gate insulation material, a first PMOS metal layer positioned on the PMOS gate insulation layer, a PMOS metal silicide region positioned above the first PMOS metal layer, wherein the PMOS metal silicide region and the NMOS metal silicide region are comprised of the same metal silicide, and a second PMOS metal layer positioned on the PMOS metal silicide region, wherein the NMOS metal layer and second PMOS metal layer are comprised of the same material. | 12-03-2015 |
Patent application number | Description | Published |
20090017632 | METHODS OF MANUFACTURING SEMICONDUCTOR STRUCTURES USING RIE PROCESS - A method for etching on a semiconductors at the back end of line using reactive ion etching. The method comprises reduced pressure atmosphere and a mixture of gases at a specific flow rate ratio during plasma generation and etching. Plasma generation is induced by a source radio frequency and anisotropic etch performance is induced by a second bias radio frequency. | 01-15-2009 |
20120326269 | E-FUSE STRUCTURES AND METHODS OF MANUFACTURE - E-fuse structures in back end of the line (BEOL) interconnects and methods of manufacture are provided. The method includes forming an interconnect via in a substrate in alignment with a first underlying metal wire and forming an e-fuse via in the substrate, exposing a second underlying metal wire. The method further includes forming a defect with the second underlying metal wire and filling the interconnect via with metal and in contact with the first underlying metal wire thereby forming an interconnect structure. The method further includes filling the e-fuse via with the metal and in contact with the defect and the second underlying metal wire thereby forming an e-fuse structure. | 12-27-2012 |
20130127584 | Redundant Via Structure For Metal Fuse Applications - A metal fuse structure using redundant vias. The redundant vias are formed on one metal level in a stacked via metal fuse structure to force failures to occur in the metal level that does not have the redundant vias. The metal fuse structure includes: a first dielectric layer having a metal feature; a second dielectric layer having a first metal connector embedded therein; and a third dielectric layer having a second metal connector embedded therein. The metal connectors include at least one via and one line, and at least one metal connector has at least two vias. | 05-23-2013 |
20130176073 | BACK-END ELECTRICALLY PROGRAMMABLE FUSE - A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current. | 07-11-2013 |
20130214391 | Lateral-Dimension-Reducing Metallic Hard Mask Etch - A combination of gases including at least a fluorocarbon gas, oxygen, and an inert sputter gas is employed to etch at least one opening into an organic photoresist. The amount of oxygen is controlled to a level that limits conversion of a metallic nitride material in an underlying hard mask layer to a metal oxide, and causes organic polymers generated from the organic photoresist to cover peripheral regions of each opening formed in the organic photoresist. The hard mask layer is etched with a taper by the oxygen-limited fluorine-based etch chemistry provided by the combination of gases. The taper angle can be controlled such that a shrink ratio of the lateral dimension by the etch can exceed 2.0. | 08-22-2013 |
20130214894 | METAL FUSE STRUCTURE FOR IMPROVED PROGRAMMING CAPABILITY - Structure providing more reliable fuse blow location, and method of making the same. A vertical metal fuse blow structure has, prior to fuse blow, an intentionally damaged portion of the fuse conductor. The damaged portion helps the fuse blow in a known location, thereby decreasing the resistance variability in post-blow circuits. At the same time, prior to fuse blow, the fuse structure is able to operate normally. The damaged portion of the fuse conductor is made by forming an opening in a cap layer above a portion of the fuse conductor, and etching the fuse conductor. Preferably, the opening is aligned such that the damaged portion is on the top corner of the fuse conductor. A cavity can be formed in the insulator adjacent to the damaged fuse conductor. The damaged fuse structure having a cavity can be easily incorporated in a process of making integrated circuits having air gaps. | 08-22-2013 |
20130307151 | METHOD TO RESOLVE HOLLOW METAL DEFECTS IN INTERCONNECTS - A method of repairing hollow metal void defects in interconnects and resulting structures. After polishing interconnects, hollow metal void defects become visible. The locations of the defects are largely predictable. A repair method patterns a mask material to have openings over the interconnects (and, sometimes, the adjacent dielectric layer) where defects are likely to appear. A local metal cap is formed in the mask openings to repair the defect. A dielectric cap covers the local metal cap and any recesses formed in the adjacent dielectric layer. | 11-21-2013 |
20140035142 | PROFILE CONTROL IN INTERCONNECT STRUCTURES - The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of the line opening prevents rounding of the corners of a dielectric material portion that is present beneath the line opening and adjacent the via opening. | 02-06-2014 |
20140070363 | ELECTRONIC ANTI-FUSE - An electronic anti-fuse structure, the structure including an M | 03-13-2014 |
20140077334 | Electronic Fuse Vias in Interconnect Structures - An electronic fuse and method for forming the same. Embodiments of the invention include e-fuses having a first metallization level including a metal structure, a second metallization level above the first metallization level, a metal via in the second metallization level, an interface region where the metal via meets the first metallization level, and a damaged region at the interface region. Embodiments further include a method including providing a first metallization level including a metal structure, forming a capping layer on the first metallization level, forming an opening in the capping layer that exposes a portion of the metal structure; forming above the capping layer an adhesion layer contacting the metal structure, forming an insulating layer above the adhesion layer, etching the insulating layer and the adhesion layer to form a recess exposing the metal structure, and filling the fuse via recess to form a fuse via. | 03-20-2014 |
20140167268 | GRAPHENE AND METAL INTERCONNECTS - A graphene and metal interconnect structure and methods of making the same are disclosed. The graphene is a multiple layer graphene structure that is grown using a graphene catalyst. The graphene forms an electrical connection between two or more VIAs or components, or a combination of VIAs and components. A VIA includes a fill metal, with at least a portion of the fill metal being surrounded by a barrier metal. A component may be a routing track, a clock signal source, a power source, an electromagnetic signal source, a ground terminal, a transistor, a macrocell, or a combination thereof. The graphene is grown, using a graphene catalyst, from both solid and liquid carbon sources using chemical vapor deposition (CVD) at a temperature between 300° C.-400° C. The graphene catalyst can be an elemental form of, or alloy including, nickel, palladium, ruthenium, iridium or copper. | 06-19-2014 |
20140183688 | MODIFIED VIA BOTTOM FOR BEOL VIA EFUSE - An electronic fuse structure including an M | 07-03-2014 |
20140203435 | SELECTIVE LOCAL METAL CAP LAYER FORMATION FOR IMPROVED ELECTROMIGRATION BEHAVIOR - A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines. | 07-24-2014 |
20140217612 | ELECTRONIC FUSE HAVING A DAMAGED REGION - An electronic fuse structure including an M | 08-07-2014 |
20140319685 | Hybrid Graphene-Metal Interconnect Structures - Hybrid metal-graphene interconnect structures and methods of forming the same. The structure may include a first end metal, a second end metal, a conductive line including one or more graphene portions extending from the first end metal to the second end metal, and one or more line barrier layers partially surrounding each of the one or more graphene portions. The conductive line may further include one or more intermediate metals separating each of the one or more graphene portions. Methods of forming said interconnect structures may include forming a plurality of metals including a first end metal and a second end metal in a dielectric layer, forming one or more line trenches between each of the plurality of metals, forming a line barrier layer in each of the one or more line trenches, and filling the one or more line trenches with graphene. | 10-30-2014 |
20150035154 | PROFILE CONTROL IN INTERCONNECT STRUCTURES - The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of the line opening prevents rounding of the corners of a dielectric material portion that is present beneath the line opening and adjacent the via opening. | 02-05-2015 |
20150137312 | METAL FUSE STRUCTURE FOR IMPROVED PROGRAMMING CAPABILITY - Structure providing more reliable fuse blow location, and method of making the same. A vertical metal fuse blow structure has, prior to fuse blow, an intentionally damaged portion of the fuse conductor. The damaged portion helps the fuse blow in a known location, thereby decreasing the resistance variability in post-blow circuits. At the same time, prior to fuse blow, the fuse structure is able to operate normally. The damaged portion of the fuse conductor is made by forming an opening in a cap layer above a portion of the fuse conductor, and etching the fuse conductor. Preferably, the opening is aligned such that the damaged portion is on the top corner of the fuse conductor. A cavity can be formed in the insulator adjacent to the damaged fuse conductor. The damaged fuse structure having a cavity can be easily incorporated in a process of making integrated circuits having air gaps. | 05-21-2015 |
20150235951 | LATERAL-DIMENSION-REDUCING METALLIC HARD MASK ETCH - A combination of gases including at least a fluorocarbon gas, oxygen, and an inert sputter gas is employed to etch at least one opening into an organic photoresist. The amount of oxygen is controlled to a level that limits conversion of a metallic nitride material in an underlying hard mask layer to a metal oxide, and causes organic polymers generated from the organic photoresist to cover peripheral regions of each opening formed in the organic photoresist. The hard mask layer is etched with a taper by the oxygen-limited fluorine-based etch chemistry provided by the combination of gases. The taper angle can be controlled such that a shrink ratio of the lateral dimension by the etch can exceed 2.0. | 08-20-2015 |
20150255342 | SELECTIVE LOCAL METAL CAP LAYER FORMATION FOR IMPROVED ELECTROMIGRATION BEHAVIOR - A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines. | 09-10-2015 |
20150255343 | SELECTIVE LOCAL METAL CAP LAYER FORMATION FOR IMPROVED ELECTROMIGRATION BEHAVIOR - A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines. | 09-10-2015 |
20150255398 | SELECTIVE LOCAL METAL CAP LAYER FORMATION FOR IMPROVED ELECTROMIGRATION BEHAVIOR - A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines. | 09-10-2015 |
Patent application number | Description | Published |
20090144074 | SYSTEM AND METHOD FOR STREAMLINED REGISTRATION OF ELECTRONIC PRODUCTS OVER A COMMUNICATION NETWORK AND FOR VERIFICATION AND MANAGEMENT OF INFORMATION RELATED THERETO - The system and method of the present invention provide integrated or embedded components, for electronic (or other) products, each operable to securely store and selectively provide access to, a unique ID (UID) previously assigned to its corresponding specific product, where the UID of each product is registered with one or more particular UID registration centers over at least one communication network, and associated with one or more data records stored in a corresponding database file at the particular UID registration center, the data records being inclusive of information related to the product, the product purchase history, current ownership, etc., and wherein one or more authorized parties may subsequently advantageously utilize at least one UID (and optionally a verifier) to access, verify, edit, transfer, transmit, and/or otherwise manage at least one information item related to the one or more corresponding registered products in their UID registration center database file. Also provided is an optimized process for verifiable transfer of ownership rights between a product's authorized owner and intended recipient, the transfer process being implemented over at least one communication network with graphical user interfaces provided for each party, where the transfer of ownership rights involves association of the product's UID with the receiving party's data record and confirming ownership transfer, and optional transfer of additional product-related information from the former product owner to the current recipient. | 06-04-2009 |
20090289774 | SECURE ELECTROMAGNETIC DATA STORAGE ELEMENT HAVING A PLURALITY OF SELECTIVELY DETERMINED SWITCHABLE SECURITY MODES - The apparatus of the present invention are directed to an selectively accessible electromagnetically resonant data storage element (implemented as a resonant tag, card, and/or embedded element), that is selectively responsive to predetermined electromagnetic interrogation thereof, that comprises a novel membrane switch component for enabling a user to selectively enable and/or disable interrogatory access to the resonant component, to protect from unauthorized interrogation thereof (hereinafter “MSRDS element”). The inventive MSRDS element comprises a top circuitry layer, a bottom circuitry layer, which includes a microchip, a plurality of contact pads and an antenna, an insulation spacer layer, a pressure layer retention component, and an optional EM/EMI shielding layer. The membrane switch may be formed through a combination of aligned and configured subcomponents of at least a portion of the element's layers. In one embodiment thereof, the pressure layer retention component may be advantageously utilized to maintain the membrane switch in a pressed down position to thereby enable the MSRDS element to function continuously (i.e., in an Always-ON security mode), until such time that the pressure layer retention component is removed. In this exemplary embodiment of the MSRDS element, for example used in conjunction with consumer products, when a consumer purchases a product that has been provided with the MSRDS element, they remove (e.g., peel off, etc.) the pressure layer retention component to change the element to an Always-OFF security mode, such that the MSRDS element is only accessible to electromagnetic interrogation thereof when the membrane switch is held down. Therefore, the MSRDS element of the present invention provides a greater level of data security advantageously balanced with convenience—it is freely accessible prior to acquisition thereof by a user, and is thereafter easily made secure by the user, who is provided with the capability of readily and selectively enabling access to the data stored therein. | 11-26-2009 |
20090303050 | SECURE ELECTROMAGNETIC DATA STORAGE ELEMENT HAVING A PLURALITY OF SELECTIVELY DETERMINED SWITCHEABLE SECURITY MODES - The apparatus of the present invention are directed to an selectively accessible electromagnetically resonant data storage element (implemented as a resonant tag, card, and/or embedded element), that is selectively responsive to predetermined electromagnetic interrogation thereof, that comprises a novel membrane switch component for enabling a user to selectively enable and/or disable interrogatory access to the resonant component, to protect from unauthorized interrogation thereof (hereinafter “MSRDS element”). The inventive MSRDS element comprises a top layer, a bottom circuitry layer, which includes a microchip, a plurality of contact pads and an antenna, an insulation spacer layer, a pressure layer retention component, and an optional EMI shielding layer. The membrane switch may be formed through a combination of aligned and configured subcomponents of at least a portion of the element's layers. In one embodiment thereof, the pressure layer retention component may be advantageously utilized to maintain the membrane switch in a pressed down position to thereby enable the MSRDS element to function continuously (i.e., in an Always-ON mode), until such time that the pressure layer retention component is removed. In this exemplary embodiment of the MSRDS device, for example used in conjunction with consumer products, when a consumer purchases a product that has been provided with the MSRDS element, they remove (e.g., peel off, etc.) the pressure layer retention component to change the element to an Always-OFF mode, such that the MSRDS element is only accessible to electromagnetic interrogation thereof, when the membrane switch is held down. Therefore, the MSRDS device of the present invention provides a greater level of data security advantageously balanced with convenience—it is freely accessible prior to acquisition thereof by a user, and is thereafter easily made secure by the user, who is provided with the capability of readily and selectively enabling access to the data stored therein. | 12-10-2009 |
20110147467 | ENHANCED PERFORMANCE AND SECURITY RFID DEVICE - The present invention is directed to a selectively accessible enhanced radio-frequency identification (RFID) device, that is enhanced performance and security by selectively responsive to predetermined electromagnetic interrogation thereof, that comprises an enhanced component for enabling a user to adjust readable distances and selectively enable or disable interrogatory access to the enhanced RFID device, to protect from unauthorized interrogation thereof. The inventive enhanced RFID device comprises an antenna, a microchip and at least one enhanced component. The enhanced component may use “Electromagnetic Induction” to the antenna to increase performance and “Electromagnetic Shield”, to cover the antenna. In one embodiment thereof, the enhanced RFID device may be advantageously utilizing retention component to keep closed it in an Always-OFF mode, such that the enhanced RFID device is only accessible to electromagnetic interrogation thereof, when the enhanced RFID device is open to an Always-ON mode. Therefore, the enhanced RFID device of the present invention provides an inventively user controllable, two functions in one of enhanced component, for enhanced performance and greater level of data security advantageously balanced with convenience—it is freely accessible prior to acquisition thereof by a user, and is thereafter easily made secure by the user, who is provided with the capability of readily and selectively enabling access to the data stored therein. | 06-23-2011 |
20130227653 | SYSTEM AND METHOD FOR STREAMLINED REGISTRATION OF PRODUCTS OVER A COMMUNICATION NETWORK AND FOR VERIFICATION AND MANAGEMENT OF INFORMATION RELATED THERETO - The system and method of the present invention to provide at least one unique identification code (UID) registration center comprises of plural authorized parties' account. Each account comprises at least one product data file with UID, in which UID is associated with a product, to enable over at least one communication network (such as cloud computing), to access, verify, edit, transfer, transmit, and/or otherwise manage at least one information item, including ownership right related to the product transfer between each party, etc. application corresponding to registered products in the UID registration center. Also enable product to product (machine to machine) data exchange each other, which is part of Internet of Thing application. | 08-29-2013 |
20130241695 | SECURE ELECTROMAGNETIC DATA STORAGE ELEMENT HAVING A SELECTIVELY DETERMIND SWITCHABLE SECURITY MODE - The apparatus of the present invention are directed to a selectively accessible electromagnetically resonant data storage element (implemented as a resonant tag, card, embedded element and/or similar devices), for inventory and facility control and management, for product tracking during transportation, for security purposes (e.g., personal identification (e.g., passports, driver's licenses), access control, etc.), and to facilitate various forms of electronic information interchange (for example in electronic commerce, such as payment card, tag etc.), that is selectively responsive to predetermined electromagnetic interrogation thereof, that comprises a novel connecting component and a security mode selection component, for a user to change from Always-ON to Always-OFF, then enabling selectively to ON and OFF for interrogatory access to resonant component, to protect from unauthorized interrogation thereof. | 09-19-2013 |