Kueber
Brian M. Kueber, Bedford Park, IL US
Patent application number | Description | Published |
---|---|---|
20140199467 | LIQUID FEED COMPRISED OF CORN STEEPWATER AND HYDROL - The application relates to a composition comprising: from about 10 parts to about 40 parts of hydrol and from about 60 parts to about 90 parts of steepwater by volume. | 07-17-2014 |
Kirby Kueber, Clearwater, FL US
Patent application number | Description | Published |
---|---|---|
20110013194 | ALTERNATE MODULATION SCHEME FOR AN INTERFEROMETRIC FIBER OPTIC GYROSCOPE - An Interferometric Fiber Optic Gyro (IFOG) device for high accuracy sensing. An example IFOG includes an integrated optics chip (IOC) and a modulation component that modulates one or more light signals passing thru the IOC according to a bias-modulation waveform. A glitch pattern experienced at front-end components of the IFOG includes frequency content that has approximately zero amplitude at predefined sense harmonics. Frequency content of the bias-modulation waveform is below a predefined threshold value at the predefined sense harmonics. | 01-20-2011 |
20110227771 | INEXPENSIVELY IMPROVING RESOLUTION AND REDUCING NOISE OF LOW-NOISE SIGNALS - Systems and methods for improving resolution of low-noise signals in an analog-to-digital conversion circuit. A simple, low cost pseudo-noise generating circuit is disclosed that, when connected to the signal conditioning circuitry of A/D conversion circuit, adds pseudo-noise to an analog input voltage signal. Additional pseudo-noise is beneficial for improving the resolution of analog-to-digital conversion when oversampling and summing or averaging are used in post-conversion processing operations. The circuit is composed of a plurality of resistors configured in at least two parallel branches. An individually switchable voltage source output is connected to each branch. A resulting analog voltage can be measured at a common termination point for the branches, depending on the combination of switchable voltage source output turned on, and the branch to which the voltage output is applied. By varying the combination of switchable voltage source outputs turned on over time, a known analog pseudo-noise signal is developed. | 09-22-2011 |
Sven Kueber, Kallstadt DE
Patent application number | Description | Published |
---|---|---|
20100317889 | PROCESS FOR PREPARING ISOCYANATES - Process for preparing isocyanates by phosgenation of amines, wherein phosgene and amine are brought into contact in at least 2 mixing chambers connected in parallel. | 12-16-2010 |
William Kueber US
Patent application number | Description | Published |
---|---|---|
20110032768 | ERASE DEGRADATION REDUCTION IN NON-VOLATILE MEMORY - Methods for erasing a memory device and memory systems are provided, such as those including a non-volatile memory device is erased by using an intermediate erase step prior to a normal erase step. The intermediate erase step is comprised of an erase pulse voltage, applied to the semiconductor well of the selected memory block of memory cells, while edge rows of memory cells are biased at a low positive voltage (e.g., 0.2-2V). An erase verify operation is then performed. If the selected memory block is not erased, a normal memory erase step is then performed in which the same erase pulse voltage is used but all of the rows are biased at ground potential as in a normal erase step. If the memory block is still fails the erase verify operation, the erase pulse voltage is increased and the process repeated. | 02-10-2011 |
William Kueber, Boise, ID US
Patent application number | Description | Published |
---|---|---|
20080298123 | Non-volatile memory cell healing - Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string. | 12-04-2008 |
20090244979 | ERASE DEGRADATION REDUCTION IN NON-VOLATILE MEMORY - Methods for erasing a memory device and memory systems are provided, such as those including a non-volatile memory device is erased by using an intermediate erase step prior to a normal erase step. The intermediate erase step is comprised of an erase pulse voltage, applied to the semiconductor well of the selected memory block of memory cells, while edge rows of memory cells are biased at a low positive voltage (e.g., 0.8-2V). An erase verify operation is then performed. If the selected memory block is not erased, a normal memory erase step is then performed in which the same erase pulse voltage is used but all of the rows are biased at ground potential as in a normal erase step. If the memory block is still fails the erase verify operation, the erase pulse voltage is increased and the process repeated. | 10-01-2009 |
20100165747 | NON-VOLATILE MEMORY CELL HEALING - Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string. | 07-01-2010 |
20120300551 | NON-VOLATILE MEMORY CELL HEALING - Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string. | 11-29-2012 |
William R. Kueber, Boise, ID US
Patent application number | Description | Published |
---|---|---|
20130264628 | USE OF ETCH PROCESS POST WORDLINE DEFINITION TO IMPROVE DATA RETENTION IN A FLASH MEMORY DEVICE - Embodiments of the present disclosure describe techniques and configurations relating to use of an etch process post wordline definition to improve data retention in a flash memory device. In one embodiment, a method includes forming a plurality of wordline structures on a substrate, wherein individual wordline structures of the plurality of wordline structures include a control gate having an electrically conductive material and a cap having an electrically insulative material formed on the control gate, depositing an electrically insulative material to form a liner on a surface of the individual wordline structures, and etching the liner to remove at least a portion of the liner. Other embodiments may be described and/or claimed. | 10-10-2013 |