Patent application number | Description | Published |
20100145098 | PROCESS FOR PRODUCING CARBOXYLIC ACID ANHYDRIDES - A process for producing carboxylic acid anhydrides by the carbonylation reaction of a carboxylic acid ester, derived from an alcohol and a carboxylic acid, with carbon monoxide containing a small amount of hydrogen in a liquid reaction medium in the presence of a Group VIII B catalyst to produce a carboxylic acid anhydride. The reaction medium comprises the Group VIII B catalyst, an organic halide, the carboxylic acid ester, an alkali metal salt, the carboxylic acid anhydride, the carboxylic acid, and at least one ionic liquid consisting of a cation and an anion where the cation of the ionic liquid has a nitrogen-containing heterocyclic structure. The ionic liquid has at least one of the following structural forms: | 06-10-2010 |
20100160669 | PROCESS FOR PRODUCING ORGANIC CARBOXYLIC ACID ESTERS - The present invention relates to a process for producing organic carboxylic acid esters, in which an amino-ester exchange reaction of an organic carboxylic acid amide with an ester compound, or with an alcohol compound under a CO pressure, is carried out at a specific temperature in the presence of a catalyst and a promoter, so as to produce an organic carboxylic acid ester. | 06-24-2010 |
20110004020 | PROCESS FOR PRODUCING ORGANIC CARBOXYLIC ACID AMIDES - The present invention relates to a process for producing organic carboxylic acid amides by nitrile hydrolysis of a nitrile compound at certain temperature and pressure in the presence of a catalyst to produce an organic carboxylic acid amide. | 01-06-2011 |
20110152558 | PROCESS FOR PRODUCING DIARYL CARBONATES - The present invention relates to a process for producing diaryl carbonates, which is to synthesize diaryl carbonates by oxidative carbonylation of phenols with carbon monoxide and oxygen, and in particular, to synthesize diphenyl carbonate from phenol. The present invention is characterized in that a catalytic system comprising a metal halide catalyst and one or more cocatalysts of nitrogenous heterocyclic compounds is used to increase the convertibility, selectivity and yield of this catalytic reaction. | 06-23-2011 |
20120182271 | DIGITAL PAINTING PEN, DIGITAL PAINTING SYSTEM AND MANIPULATING METHOD THEREOF - A digital painting pen includes a pen body and at least one sensor, which is disposed on the pen body and generates at least one sensing signal according to a condition while a user rotates or presses the digital painting pen, changes an angle of the digital painting pen against a plane, changes a holding position of the digital painting pen, or slides a finger to change a position of the finger on the digital painting pen, thereby changing a color, a brush type or a brush thickness of the digital painting pen. Accordingly, the present invention can change a color, a brush type and a brush thickness of the digital painting pen to achieve an instinctive drawing effect without using buttons and switches. | 07-19-2012 |
Patent application number | Description | Published |
20100135058 | MAGNETIC MEMORY, DRIVING METHOD THEREOF, AND MANUFACTURING METHOD THEREOF - A magnetic memory, a driving method thereof, and a manufacturing method thereof are provided. The magnetic memory includes a plurality of lead structures, a plurality of first magnetic metal structures, a second magnetic metal structure, and an insulation layer. Each of the first magnetic metal structures is disposed between adjacent two of the lead structures, and the second magnetic metal structure spans over the lead structures. A structure composed of the first magnetic metal structures and the second magnetic metal structure includes a plurality of magnetic memory cells connected with each other. Each of the magnetic memory cells has a magnetic domain and a domain wall adjacent to the magnetic domain, wherein the magnetic domain is suitable for storing a bit data. | 06-03-2010 |
20100321974 | MAGNETIC SHIFT REGISTER AND READING METHOD - A magnetic shift register including at least one magnetic track is provided. Each magnetic track has at least one set of burst data formed by a plurality of consecutive magnetic domains. Each magnetic domain has a magnetization direction corresponding to a stored data. A head magnetic domain having a given magnetization direction corresponding to a given stored data is set at a most front of the set of burst data, and the head magnetic domain and the set of burst data form a data storage unit. A method for reading a magnetic shift register is provided. | 12-23-2010 |
20100328986 | MAGNETIC SHIFT REGISTER MEMORY IN STACK STRUCTURE - A magnetic shift register memory in stack structure includes magnetic shift registering layers for forming an unit of stack structure. Each registering layer has multiple magnetic domains and each domain has a magnetization direction corresponding to a stored data. The two adjacent magnetic shift registering layers respectively have an upper magnetic domain and a lower magnetic domain forming a coupling region. By a coupling structure, the lower magnetic domain and the upper magnetic domain have the same stored data. A driving current unit is coupled to the magnetic shift registering layers for respectively providing a driving current in a predetermined direction to the magnetic shift registering layers. As a result, the stored data in the magnetic domains of the magnetic shift registering layers is shifted in a direction from a foremost registering layer to a last registering layer of the magnetic shift registering layers via the coupling structure. | 12-30-2010 |
20110090730 | MAGNETIC MEMORY STRUCTURE AND OPERATION METHOD - A magnetic memory structure includes a memory track which has consecutive magnetic domains. Each of the magnetic domains has memory capacity of one bit. A first domain-wall injecting layer intersects and connects a terminal of the memory track and constantly stores a first binary data. A second domain-wall injecting layer against the first domain-wall injecting layer intersects and connects the terminal of the memory track and constantly stores a second binary data different from the first binary data. The memory track and one of the first domain-wall injecting layer and the second domain-wall injecting layer together form a domain wall. | 04-21-2011 |
20110157955 | MAGNETIC SHIFT REGISTER MEMORY - A magnetic shift register memory includes a magnetic track and a reference magnetic region. The magnetic track has multiple magnetic domains. Each of the magnetic domains stores one bit data. One end of the magnetic domains is set with a first data injection domain for storing a first data, and a second data injection domain is located adjacent to the first data injection domain. The reference magnetic region corresponding to the second data injection region is implemented at a side of the magnetic track for storing a second data. | 06-30-2011 |
20130033917 | READER FOR MAGNETIC SHIFT REGISTER - A reader for magnetic shift register is provided. The reader includes a magnetic reference layer, a tunneling layer, a magnetic canceling layer and an isolated layer. The magnetic reference layer and the magnetic canceling layer are respectively configured at different sides of a magnetic track for providing anti-parallel magnetic fields. The magnetic reference layer overlaps the magnetic canceling layer in a perpendicular direction of the magnetic track. The magnetic reference layer electrically connects to a readout circuit. The magnetic canceling layer is floating. The tunneling layer is configured between the magnetic reference layer and the magnetic track for providing a magnetic tunnel junction (MTJ). The isolated layer is configured between the magnetic canceling layer and the magnetic track for avoiding a current in the magnetic track from tunneling to the magnetic canceling layer. | 02-07-2013 |
Patent application number | Description | Published |
20100143164 | FAN MOTOR STRUCTURE - A fan motor structure is provided. A fan is disposed within an accommodating hole at a center of a body. A permanent magnet and a printed circuit board (PCB) provided with plural coils are respectively disposed between an upper ring and a base of the body. An axial air gap is formed between the coils and the permanent magnet. A bearing is disposed between the upper ring and the base. The fan blades of the fan extend from the periphery of the accommodating hole toward the center of the fan. An axle center of the fan overlaps with that of the body. The coils after being supplied with a current create a flux linkage with the permanent magnet. Due to the flux linkage and the axial air gap between the coils and the permanent magnet, the upper ring is forced to rotate, thus driving the fan to rotate. | 06-10-2010 |
20130334921 | MOTOR STRUCTURE - A motor structure includes a case, a rotor, a first magnet, a second magnet and at least one magnetic conductive plate, wherein the rotor is disposed within an accommodating slot of the case, and the first magnet is disposed between the case and the rotor. The first magnet comprises a first end portion spaced apart with the case to define a first separation space. The second magnet comprises a second end portion spaced apart with the case to define a second separation space. A spacing slot is composed of the first separation space and the second separation space, and the at least one magnetic conductive plate is disposed within the spacing slot. The magnetic conduction through the at least one magnetic conductive plate enables to lower the reluctance of the motor structure for prevention of magnetic flux leakage therefore increasing the air-gap flux density. | 12-19-2013 |
20140144581 | METHOD FOR MANUFACTURING A MAGNET-CONDUCTIVE DEVICE AND APPARATUS THEREOF - A method for manufacturing magnet-conductive device includes a filling step and an adhering step. The filling step includes providing a glue by a glue dispenser and contacting the glue with a first magnet-conductive plate to make the glue adhered to a lower surface of the first magnet-conductive plate. The adhering step includes making the lower surface of the first magnet-conductive plate face toward a second magnet-conductive plate, making the first magnet-conductive plate and the second magnet-conductive plate stackable from each other and adhering the first magnet-conductive plate and the second magnet-conductive plate via the glue. Eventually, by repeatedly performing the filling step and the adhering step, the desirable stacking quantity is achieved to form a magnet-conductive device. | 05-29-2014 |
20140284837 | METHOD FOR MANUFACTURING MAGNET-CONDUCTIVE DEVICE AND GLUE-INJECTABLE PUNCH STRUCTURE THEREOF - A method for manufacturing a magnet-conductive device includes performing a punch process to a plate by a glue-injectable punch structure, wherein the glue-injectable punch structure includes a punch head and a control member. The punch head comprises an accommodating cavity, an injection hole and an inlet, and a supply channel is formed by the accommodating cavity, the injection hole and the inlet. The control member selectively obstructs the supply channel or permits the supply channel into conduction. By using the method for manufacturing the magnet-conductive device, the stack between plural plates is simplified, and the coupling strength between adjacent plates is enhanced. In addition, this invention considers the gel between adjacent plates to be insulating medium to lower the iron loss of the magnet-conductive plates. | 09-25-2014 |
Patent application number | Description | Published |
20090047765 | METHOD OF MANUFACTURING NON-VOLATILE MEMORY - A method of manufacturing a non-volatile memory is provided. In the method, a first dielectric layer, a first conductive layer, and a first cap layer are formed sequentially on a substrate. The first cap layer and the first conductive layer are patterned to form first gate structures. A second dielectric layer is formed on the sidewall of the first gate structures, and a portion of the first dielectric layer is removed to expose the substrate between the first gate structures. An epitaxy layer is formed on the substrate between two first gate structures. A third dielectric layer is formed on the epitaxy layer. A second conductive layer is formed on the third dielectric layer. The first cap layer and a portion of the first conductive layer are removed to form second gate structures. Finally, a doped region is formed in the substrate at two sides of the second gate structures. | 02-19-2009 |
20090061581 | METHOD FOR MANUFACTURING TRENCH ISOLATION STRUCTURE AND NON-VOLATILE MEMORY - A method for manufacturing a non-volatile memory is provided. An isolation structure is formed in a trench formed in a substrate. A portion of the isolation structure is removed to form a recess. A first dielectric layer and a first conductive layer are formed sequentially on the substrate. Bar-shaped cap layers are formed on the substrate. The first conductive layer not covered by the bar-shaped cap layers is removed to form first gate structures. A second dielectric layer is formed on the sidewalls of the first gate structures. A third dielectric layer is formed on the substrate between the first gate structures. A second conductive layer is formed on the third dielectric layer. The bar-shaped cap layers and a portion of the first conductive layer are removed to form second gate structures. A doped region is formed in the substrate at two sides of each of the second gate structures. | 03-05-2009 |
20090065846 | NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF - A manufacturing method of a non-volatile memory includes forming a first dielectric layer, a first conductive layer, and a first cap layer sequentially on a substrate to form first gate structures; conformally forming a second dielectric layer on the substrate; forming a first spacer having a larger wet etching rate than the second dielectric layer on each sidewall of each first gate structure; partially removing the first and second dielectric layers to expose the substrate. A third dielectric layer is formed on the substrate between the first gate structures; removing the first spacer; forming a second conductive layer on the third dielectric layer; removing the first cap layer and a portion of the first conductive layer to form second gate structures; and forming doped regions in the substrate at two sides of each second gate structure. | 03-12-2009 |
20090087975 | METHOD FOR MANUFACTURING A MEMORY - A method for manufacturing a memory includes first providing a substrate with a horizontally adjacent control gate region and floating gate region which includes a sacrificial layer and sacrificial sidewalls, removing the sacrificial layer and sacrificial sidewalls to expose the substrate, forming dielectric sidewalls adjacent to the control gate region, forming a floating gate dielectric layer on the exposed substrate and forming a floating gate layer adjacent to the dielectric sidewalls and on the floating gate dielectric layer. | 04-02-2009 |
20090127610 | NON-VOLATILE MEMORY AND THE MANUFACTURING METHOD THEREOF - A non-volatile memory disposed on a substrate includes active regions, a memory array, and contacts. The active regions defined by isolation structures disposed in the substrate are extended in a first direction. The memory array is disposed on the substrate and includes memory cell columns, control gate lines and select gate lines. Each of the memory cell columns includes memory cells connected to one another in series and a source/drain region disposed in the substrate outside the memory cells. The contacts are disposed on the substrate at a side of the memory array and arranged along a second direction. The second direction crosses over the first direction. Each of the contacts extends across the isolation structures and connects the source/drain regions in the substrate at every two of the adjacent active regions. | 05-21-2009 |
20100279472 | MANUFACTURING METHOD OF NON-VOLATILE MEMORY - In a manufacturing method of a non-volatile memory, a substrate is provided, and strip-shaped isolation structures are formed in the substrate. A first memory array including memory cell columns is formed on the substrate. Each memory cell column includes memory cells connected in series with one another, a source/drain region disposed in the substrate outside the memory cells, select transistors disposed between the source/drain region and the memory cells, control gate lines extending across the memory cell columns and in a second direction, and first select gate lines respectively connecting the select transistors in the second direction in series. First contacts are formed on the substrate at a side of the first memory array and arranged along the second direction. Each first contact connects the source/drain regions in every two adjacent active regions. | 11-04-2010 |
20100279499 | METHOD FOR MANUFACTURING A MEMORY - A method for manufacturing a memory includes first providing a substrate with a horizontally adjacent control gate region and floating gate region which includes a sacrificial layer and sacrificial sidewalls, removing the sacrificial layer and sacrificial sidewalls to expose the substrate, forming dielectric sidewalls adjacent to the control gate region, forming a floating gate dielectric layer on the exposed substrate and forming a floating gate layer adjacent to the dielectric sidewalls and on the floating gate dielectric layer. | 11-04-2010 |
Patent application number | Description | Published |
20090124085 | METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAS A LENGTHENED CHANNEL LENGTH - The present invention discloses a method for forming a semiconductor device. The method includes providing a substrate; forming at least one first opening in the substrate to a predetermined depth and exposing a sidewall of the substrate in the first opening; forming a spacer on the sidewall and exposing a portion of the substrate in the bottom of the first opening; etching the exposed substrate in the bottom of the first opening by using the spacer as a mask to form a second opening; forming an isolation layer in the second opening and a portion of the first opening; forming a gate dielectric layer on the surface of the substrate; and forming a conductive layer covering the substrate. | 05-14-2009 |
20100032743 | DYNAMIC RANDOM ACCESS MEMORY STRUCTURE, ARRAY THEREOF, AND METHOD OF MAKING THE SAME - A dynamic random access memory (DRAM) structure has a stacked capacitor disposed above an upper source/drain region of a vertical transistor having a surrounding gate. The gates of each row of a memory array are electrically connected with a buried word line. Each of bit lines is disposed between two adjacent columns of transistors and electrically connected with lower source/drain regions through bit line contacts. The DRAM structure may have a unit cell size of 4F | 02-11-2010 |
20100097854 | FLASH MEMORY AND FLASH MEMORY ARRAY - A flash memory including a substrate having a recess, a buried bit line, a word line, a single side insulating layer, a floating gate, a tunneling dielectric layer, a control gate, and an inter-gate dielectric layer is provided. The buried bit line extends below the recess of the substrate along a first direction. The word line is on the substrate, and extends above the recess along a second direction. The single side insulating layer is on a first sidewall of the recess. The floating gate is on a second sidewall of the recess to be opposite to the single side insulating layer. The tunneling dielectric layer is sandwiched by the floating gate and the substrate to contact the buried bit line. The control gate fills the recess and contacts the word line. The inter-gate dielectric layer is sandwiched by the control gate and the floating gate. | 04-22-2010 |
20120119276 | MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A memory device includes a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections. | 05-17-2012 |
20120119277 | MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A memory device includes a plurality of isolations and trench fillers arranged in an alternating manner in a direction, a plurality of mesa structures between the isolations and trench fillers, and a plurality of word lines each overlying a side surface of the respective mesa. In one embodiment of the present invention, the width measured in the direction of the trench filler is smaller than that of the isolation, each mesa structure includes at least one paired source/drain regions and at least one channel base region corresponding to the paired source/drain regions, and each of the word lines is on a side surface of the mesa structure, adjacent the respective isolation, and is arranged adjacent the channel base region. | 05-17-2012 |
20120149172 | METHOD FOR FABRICATING TRENCH ISOLATION STRUCTURE - A method for fabricating a trench isolation structure is described. A trench is formed in a substrate. A liner layer is formed at least in the trench. A precursor layer is formed at least on the sidewalls of the trench. The precursor layer is converted to an insulating layer that has a larger volume than the precursor layer and fills up the trench. | 06-14-2012 |
20130183808 | MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A memory device includes a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections. | 07-18-2013 |
20130183809 | METHOD OF FABRICATING MEMORY DEVICE - A method of fabricating a memory device comprises forming a plurality of first insulative blocks and a plurality of second insulative blocks arranged in an alternating manner in a substrate, forming a plurality of wide trenches in the substrate to form a plurality of protruding blocks, forming a word line on each sidewall of the protruding blocks, isolating the word line on each sidewall of the protruding block, and forming an trench filler in the protruding block to form two mesa structures, wherein the first insulative block and the second insulative block have different depths, and the wide trenches are transverse to the first insulative blocks. | 07-18-2013 |
20140054794 | MEMORY PROCESS AND MEMORY STRUCTURE MADE THEREBY - A memory process is described. A substrate is provided, having therein trenches and conductive lines buried in the trenches and having thereon an array area, wherein each of the conductive lines has an array portion in the array area. A contact area apart from the array area is defined on the substrate, wherein each of the conductive lines has a contact portion in the contact area. The substrate between the contact portions of the conductive lines is etched down to below the tops of the conductive layers to form gaps between the contact portions of the conductive lines. The gaps are then filled with an insulating layer. | 02-27-2014 |
Patent application number | Description | Published |
20110039408 | Semiconductor Device and Fabrication Method Thereof - Semiconductor devices and methods for fabricating the same. The devices includes a substrate, a first etch stop layer, a dielectric layer, an opening, and an anti-diffusion layer. The first etch stop layer overlies the substrate. The dielectric layer overlies the first etch stop layer. The opening extends through the dielectric layer and the first etch stop layer, and exposes parts of the substrate. The anti-diffusion layer overlies at least sidewalls of the opening, preventing contamination molecule diffusion from at least the first etch stop layer, wherein the anti-diffusion layer is respectively denser than the first etch stop layer and the dielectric layer. | 02-17-2011 |
20120181657 | Forming Metal-Insulator-Metal Capacitors Over a Top Metal Layer - A plurality of metal layers includes a top metal layer. An Ultra-Thick Metal (UTM) layer is disposed over the top metal layer, wherein no additional metal layer is located between the UTM layer and the top metal layer. A Metal-Insulator-Metal (MIM) capacitor is disposed under the UTM layer and over the top metal layer. | 07-19-2012 |
20120190152 | Methods for Fabricating Integrated Passive Devices on Glass Substrates - A method includes forming a plurality of dielectric layers over a semiconductor substrate; and forming integrated passive devices in the plurality of dielectric layers. The semiconductor substrate is then removed from the plurality of dielectric layers. A dielectric substrate is bonded onto the plurality of dielectric layers. | 07-26-2012 |
20120217641 | Preventing the Cracking of Passivation Layers on Ultra-Thick Metals - A device includes a top metal layer; a UTM line over the top metal layer and having a first thickness; and a passivation layer over the UTM line and having a second thickness. A ratio of the second thickness to the first thickness is less than about 0.33. | 08-30-2012 |
20130200490 | Capacitor Structure and Method of Forming the Same - Disclosed embodiments include a capacitor structure and a method for forming a capacitor structure. An embodiment is a structure comprising a conductor-insulator-conductor capacitor on a substrate. The conductor-insulator-conductor capacitor comprises a first conductor on the substrate, a dielectric stack over the first conductor, and a second conductor over the dielectric stack. The dielectric stack comprises a first nitride layer, a first oxide layer over the first nitride layer, and a second nitride layer over the first oxide layer. A further embodiment is a method comprising forming a first conductor on a substrate; forming a first nitride layer over the first conductor; treating the first nitride layer with a first nitrous oxide (N | 08-08-2013 |
20130207264 | Stress Reduction Apparatus - A stress reduction apparatus comprises a metal structure formed over a substrate, an inter metal dielectric layer formed over the substrate, wherein a lower portion of the metal structure is embedded in the inter metal dielectric layer and an inverted cup shaped stress reduction layer formed over the metal structure, wherein an upper portion of the metal structure is embedded in the inverted cup shaped stress reduction layer. | 08-15-2013 |
20140038384 | Forming Metal-Insulator-Metal Capacitors Over a Top Metal Layer - A plurality of metal layers includes a top metal layer. An Ultra-Thick Metal (UTM) layer is disposed over the top metal layer, wherein no additional metal layer is located between the UTM layer and the top metal layer. A Metal-Insulator-Metal (MIM) capacitor is disposed under the UTM layer and over the top metal layer. | 02-06-2014 |
20140106563 | Stress Reduction Apparatus - A stress reduction apparatus comprises a metal structure formed over a substrate, an inter metal dielectric layer formed over the substrate, wherein a lower portion of the metal structure is embedded in the inter metal dielectric layer and an inverted cup shaped stress reduction layer formed over the metal structure, wherein an upper portion of the metal structure is embedded in the inverted cup shaped stress reduction layer. | 04-17-2014 |
20140134801 | Methods for Fabricating Integrated Passive Devices on Glass Substrates - A method includes forming a plurality of dielectric layers over a semiconductor substrate; and forming integrated passive devices in the plurality of dielectric layers. The semiconductor substrate is then removed from the plurality of dielectric layers. A dielectric substrate is bonded onto the plurality of dielectric layers. | 05-15-2014 |
20140231955 | Process of Ultra Thick Trench Etch with Multi-Slope Profile - The present disclosure relates to an integrated chip (IC) having an ultra-thick metal layer formed in a metal layer trench having a rounded shape that reduces stress between an inter-level dielectric (ILD) layer and an adjacent metal layer, and a related method of formation. In some embodiments, the IC has an inter-level dielectric layer disposed above a semiconductor substrate. The ILD layer has a cavity with a sidewall having a plurality of sections, wherein respective sections have different slopes that cause the cavity to have a rounded shape. A metal layer is disposed within the cavity. The rounded shape of the cavity reduces stress between the ILD layer and the metal layer to prevent cracks from forming along an interface between the ILD layer and the metal layer. | 08-21-2014 |
20140246751 | Integrated Circuit Using Deep Trench Through Silicon (DTS) - An embodiment radio frequency area of an integrated circuit includes a substrate having a first resistance, the substrate including an implant region, a buried oxide layer disposed over the substrate, an interface layer between the substrate and the buried oxide layer, the interface layer having a second resistance lower than the first resistance, a silicon layer disposed over the buried oxide layer, and an interlevel dielectric disposed in a deep trench, the deep trench extending through the silicon layer, the buried oxide layer, and the interface layer over the implant region. In an embodiment, the deep trench extends through a polysilicon layer disposed over the silicon layer. | 09-04-2014 |
Patent application number | Description | Published |
20090197695 | GOLF CLUB INTERCHANGING CONNECTION STRUCTURE (I) - A golf club interchanging connection structure for interchanging a club head and a shaft, in which a connecting part is in the club head and a female screw is formed in the connecting part, includes a nut hole position part, a club sleeve, and a screw. The nut hole position part includes a male screw on an outer surface thereof and a flange. The flange includes a leaning surface and a positioning hole. The male screw is screwed with the female screw in the connecting part. The club sleeve is placed within the connecting part and has one end being fixed with the shaft and the other end having a nut hole. The screw including a screw head is positioned through the positioning hole and screwed with the nut hole, and the screw head leans against the leaning surface to lock the shaft connected to the club sleeve. | 08-06-2009 |
20090197697 | GOLF CLUB INTERCHANGING CONNECTION STRUCTURE (III) - A golf club interchanging connection structure for interchanging a club head and a shaft includes a positioning mechanism, a club sleeve, an internal screw, and an anti-rotation external screw. The positioning mechanism is placed within the club head. The club sleeve, having one end being connected to and fixed with the shaft and the other end having a first male screw, is placed within the positioning mechanism. The internal screw comprises a nut hole, which is screwed with the first male screw of the club sleeve to lock the shaft connected to the club sleeve. The anti-rotation external screw comprises a second male screw on an outer surface thereof corresponding to a female screw in the club head, in which the second male screw of the anti-rotation external screw is screwed with the female screw, and the anti-rotation external screw leans against the internal screw. | 08-06-2009 |
Patent application number | Description | Published |
20080284255 | VOICE COIL MOTORS AND PRE-COMPRESSION GENERATION DEVICES THEREOF - A voice coil motor. At least one guide bar is connected to a fixed base. A coil is connected to the fixed base. A support base is movably fit on the guide bar. An annular magnetic member is connected to the support base and surrounded by the coil. A magnetization direction of the annular magnetic member parallels a moving direction of the support base and annular magnetic member. The annular magnetic member includes a first magnetic pole and a second magnetic pole. The first magnetic pole is disposed in the coil and separated from the bottom thereof. The second magnetic pole is disposed outside the coil. The coil interacts with the annular magnetic member to generate a first force, driving the support base and annular magnetic member to move along the magnetization direction of the annular magnetic member. | 11-20-2008 |
20090045896 | Electromagnetic transmission device - An electromagnetic transmission device. A guide bar connects to a fixed base and includes magnetic-permeable material and a first central height plane. A coil connects to the fixed base. A support base movably fits on the guide bar. An annular magnetic member connects to the support base and is surrounded by the coil. A magnetization direction of the annular magnetic member is perpendicular to a moving direction of the support base and annular magnetic member. The annular magnetic member includes a second central height plane. The coil interacts with the annular magnetic member to generate a first force. When moving to separate the second central height plane from the first central height plane, the annular magnetic member interacts with the guide bar to generate a second force, driving the support base and annular magnetic member to move along a direction perpendicular to the magnetization direction of the annular magnetic member. | 02-19-2009 |
20100053070 | MULTI-DIMENSIONAL OPTICAL CONTROL DEVICE AND A CONTROLLING METHOD THEREOF - A multi-dimensional optical control device and a method thereof are provided. A movable light source can be moved due to an external action, and produce a light beam. A lens coupled to the light source is to focus the light beam. A sensor is used to sense a spot formed on the sensor by the focused light beam, and a data processing circuit coupled to the sensor is to obtain variations of position, shape and light intensity in respect to a reference spot. According to such variations of position, shape and light intensity, the data processing circuit performs a motion control of multiple dimensions | 03-04-2010 |
20110134416 | FOCAL POSITION DETECTING APPARATUS AND METHOD - A focal position detecting apparatus, for detecting a focusing condition and a tilting condition of an object, includes a planar beam generating module, an optical system, an optical sensor and a cylindrical lens. The planar beam generating module generates a planar light beam along a first path. The optical system is disposed on the first path, wherein the planar light beam, reflected by the object, passes through the optical system along a second path. The optical sensor is disposed on the second path. The cylindrical lens is disposed on the second path between the optical system and the optical sensor and an axis of the cylindrical lens is perpendicular to the second path. The planar light beam passes through the optical system and the cylindrical lens along the second path, before it is incident on the optical sensor to form a linear light spot for determining defocusing degree. | 06-09-2011 |
Patent application number | Description | Published |
20100151209 | ORGANIC/INORGANIC MULTI-LAYERED GAS BARRIER FILM - The present invention employs the totally printable process to fabricate an organic/inorganic multi-layered laminate gas barrier film. Such totally printable process is simple with lower costs. Moreover, through the pattern design, the adhesion between the organic and inorganic layers is improved. | 06-17-2010 |
20100203296 | TRANSFERRING STRUCTURE FOR FLEXIBLE ELECTRONIC DEVICE AND METHOD FOR FABRICATING FLEXIBLE ELECTRONIC DEVICE - The invention provides a transferring apparatus for a flexible electronic device and method for fabricating a flexible electronic device. The transferring apparatus for the flexible electronic device includes a carrier substrate. A release layer is disposed on the carrier substrate. An adhesion layer is disposed on a portion of the carrier substrate, surrounding the release layer and adjacent to a sidewall of the release layer. A flexible electronic device is disposed on the release layer and the adhesion layer, wherein the flexible electronic device includes a flexible substrate. | 08-12-2010 |
20100224320 | APPARATUS FOR DE-BONDING FLEXIBLE DEVICE AND METHOD FOR DE-BONDING FLEXIBLE DEVICE - The invention provides an apparatus for de-bonding a flexible device and method thereof. The apparatus for de-bonding a flexible device includes a carrier to mount a carrier substrate thereon, a release layer thereon and a flexible device covering the release layer. A separation device disposed over the carrier is used to separate the flexible device from the release layer and the carrier substrate with air entering into an interface between the flexible device and the release layer. A vacuum device disposed over the carrier is used to suction the flexible device. | 09-09-2010 |
20110291544 | GAS BARRIER SUBSTRATE, PACKAGE OF ORGANIC ELECTRO-LUMINENSCENT DEVICE AND PACKAGING METHOD THEREOF - A gas barrier substrate including a first gas barrier layer, a substrate, and a second gas barrier layer is provided. The first gas barrier layer has a central bonding surface bonded with the substrate and a peripheral boding surface surrounding the central bonding surface. The second gas barrier layer entirely covers the substrate and the first gas barrier layer. The second gas barrier layer is bonded with the substrate and the peripheral boding surface of the first gas barrier layer, wherein a minimum distance from an edge of the substrate to an edge of the first gas barrier layer is greater than a thickness of the first gas barrier layer. | 12-01-2011 |
20120216961 | METHOD FOR DE-BONDING FLEXIBLE DEVICE - The disclosure provides a method for de-bonding a flexible device. The method for de-bonding a flexible device includes providing a first carrier to mount a carrier substrate thereon, a release layer thereon and a flexible device covering the release layer and a portion of the carrier substrate. A vacuum suction process is performed to suction the flexible device using a vacuum device. A separation process is performed with air entering into an interface between the flexible device and the release layer to separate a portion of the flexible device from the release layer and the carrier substrate using a separation device. A first release process is performed so that the portion of the flexible device is separated from the vacuum device. | 08-30-2012 |
20130295814 | FABRICATING MEHTOD OF GAS BARRIER SUBSTRATE, ORGANIC ELECTRO-LUMINESCENT DEVICE AND PACKAGING METHOD THEREOF - A gas barrier substrate including a first gas barrier layer, a substrate, and a second gas barrier layer is provided. The first gas barrier layer has a central bonding surface bonded with the substrate and a peripheral boding surface surrounding the central bonding surface. The second gas barrier layer entirely covers the substrate and the first gas barrier layer. The second gas barrier layer is bonded with the substrate and the peripheral boding surface of the first gas barrier layer, wherein a minimum distance from an edge of the substrate to an edge of the first gas barrier layer is greater than a thickness of the first gas barrier layer. | 11-07-2013 |
20140160705 | ENVIRONMENTAL SENSITIVE ELECTRONIC DEVICE PACKAGE AND MANUFACTURING METHOD THEREOF - An environmental sensitive electronic device package including a first substrate, a second substrate, an environmental sensitive electronic device, gas barrier structures, micro-structures, and a filler layer is provided. The second substrate is located above the first substrate. The environmental sensitive electronic device is located on the first substrate. The gas barrier structures may be located between the first substrate and the second substrate and surround the environmental sensitive electronic device. The gas barrier structures have a first height. The micro-structures may be located between the first substrate and the second substrate and have a second height. A ratio of the second height to the first height ranges from 1/250 to 1/100. The filler layer may be located between the first substrate and the second substrate and covers the gas barrier structures and the environmental sensitive electronic device. A manufacturing method of an environmental sensitive electronic device package is also provided. | 06-12-2014 |
20140242318 | SUBSTRATE STRUCTURES APPLIED IN FLEXIBLE DEVICES - A substrate structure applied in flexible devices is provided. The substrate structure includes a carrier; a release layer with a first area formed on the carrier, which has a first adhesion force to the carrier; and a flexible substrate with a second area overlying part of the first area of the release layer and contacting the carrier, which has a second adhesion force to the release layer and a third adhesion force to the carrier, wherein the first area is larger than or equal to the second area, the third adhesion force is greater than the first adhesion force, and the first adhesion force is greater than the second adhesion force. | 08-28-2014 |
20140374736 | GAS BARRIER SUBSTRATE AND ORGANIC ELECTRO-LUMINESCENT DEVICE - A gas barrier substrate including a first gas barrier layer, a substrate, and a second gas barrier layer is provided. The first gas barrier layer has a central bonding surface bonded with the substrate and a peripheral boding surface surrounding the central bonding surface. The second gas barrier layer entirely covers the substrate and the first gas barrier layer. The second gas barrier layer is bonded with the substrate and the peripheral boding surface of the first gas barrier layer, wherein a minimum distance from an edge of the substrate to an edge of the first gas barrier layer is greater than a thickness of the first gas barrier layer. | 12-25-2014 |
Patent application number | Description | Published |
20090116368 | METHOD AND SYSTEM FOR DETERMINING DISC FORMAT FOR RECOVERY OF DATA RECORDING - A method for determining a disc format is disclosed. Data from at least one address of the disc is retrieved, wherein the at least one address is selected from a plurality of predetermined addresses related to the disc format. The disc format is determined according to the retrieved data. | 05-07-2009 |
20090175142 | METHOD AND SYSTEM OF RECORDING DATA ON A STORAGE MEDIUM - A method of recording data on a storage medium is provided. A first recording indicator is written on the storage medium to indicate a first state of a data recording thereon. A second recording indicator is written on the storage medium to indicate a second state of the data recording thereon. A recording status of the data recording is determined accordingly in accordance with the first and second indicators. | 07-09-2009 |
20090245051 | METHOD AND APPARATUS FOR LASER CONTROL DURING RECORDING - The invention relates to recording on a medium, and in particular, to laser control during recording data on an optical medium. A laser control method for dynamically adjusting laser power during recording data onto an optical disc comprises: recording normal data onto the optical disc according to an initial laser power; stopping recording when a trigger is generated; reading back the recorded normal data and generating a first recording quality index; recording a test pattern at a test pattern starting point according to a selected laser power; reading back the test pattern and generating a second recording quality index; and determining an adaptive laser power to continually record the normal data according to the first recording quality index and the second recording quality index. | 10-01-2009 |
20100020654 | METHOD AND APPARATUS FOR DATA BUFFER CONTROL OF OPTICAL DISC PLAYER - An optical disc player for playback of a multimedia file stored in an optical disc is disclosed. The optical disc player includes a front-end loader and a back-end playback engine. The front-end loader, including a first data buffer, reads data from the optical disc and stores the read data in the first data buffer when the amount of data stored in the first data buffer is less than a first threshold. The back-end playback engine receives the data from the first data buffer and plays a multimedia segment corresponding to the received data. The front-end loader increases the first threshold of the first data buffer before a time-consuming servo behavior occurs. | 01-28-2010 |
20100074071 | METHOD FOR READING DISK MANAGEMENT DATA OF AN OPTICAL DISK - The invention provides a method for reading disk management data of an optical disk. In one embodiment, the disk management data comprises data layout information of the optical disk, and a plurality of disk management data copies of the disk management data is stored on the optical disk. First, a first disk management data copy selected from the plurality of disk management data copies is read from the optical disk. An accuracy measure of the first disk management data copy is then calculated to determine whether the accuracy measure of the first disk management data copy is acceptable. When the accuracy measure of the first disk management data copy is acceptable, the optical disk is accessed according to the first disk management data copy. | 03-25-2010 |
20100232274 | METHOD AND APPARATUS FOR DETECTING DISC - A method for detecting a disc, the method includes the steps of: reading a file system of the disc; determining a type of the disc according to the file system; and abandoning a multi-session checking process upon the disc if the type of the disc is a one-session disc. | 09-16-2010 |
20110069593 | METHOD OF IDENTIFYING PHYSICAL CHARACTERISTIC INFORMATION OF OPTICAL DISC AND RELATED CONTROLLER THEREOF - A method of identifying physical characteristic information of an optical disc includes: deriving a reading result by reading at least a first region of the optical disc, where a location of the first region is specified in a Blu-ray disc specification for recording information associated with recording management of a BD recordable disc; and identifying a first physical characteristic of the optical disc according to the reading result. | 03-24-2011 |
Patent application number | Description | Published |
20110101282 | WATER-SOLUBLE SELF-ACID-DOPED POLYANILINE BLENDS - The present invention provides a water-soluble self-acid-doped polyaniline blends, comprising a 70-90% weight percentage polyaniline derivative and 10-30% weight percentage at least a water-soluble polymer. The blend can be used to produce a conductive polymer film and/or a conductive-polymer composite film. In the present invention, a water-soluble self-acid-doped polyaniline derivative is blended with a water-soluble polymer to enhance the mechanical properties and the coating-to-substrate adhesion of the electric conductive polymer film or the electric conductive-polymer composite film, and increase the conductivity of the blender. In addition, the blend containing a water-soluble self-acid-doped polyaniline of the present invention is biotoxicity-free and has free radical-capture capability. Thus it can be used as a biocompatible and conductive biomedical material. | 05-05-2011 |
20110104077 | Magnetic nanocomposite with multi-biofunctional groups and method for fabricating the same - The present invention proposes a magnetic nanocomposite with multi-biofunctional groups, which comprises a core and a shell wrapping the core, wherein the core contains magnetic nanoparticles, and wherein the shell is made of a conductive polymer with multi-biofunctional groups where a medicine, an antibody or a fluorescent label can be attached. | 05-05-2011 |
20110104294 | Magnetic nanocomposite for inhibiting/treating cancer and method for fabricating the same - The present invention discloses a magnetic nanocomposite for inhibiting/treating cancer and a method for fabricating the same. The magnetic nanocomposite comprises a core formed of a plurality of magnetic nanoparticles made of ferric ferrous oxide (Fe | 05-05-2011 |
20120328705 | MAGNETIC NANOMEDICINE FOR TUMOR SUPPRESSION AND THERAPY - A magnetic nanomedicine for tumor suppression and therapy, comprising: a core, made of magnetic nanoparticles; a shell, encapsulating said core and is made of carboxylated polyaniline (SPAnH); and a tumor suppression medicine Epirubicin (EPI) or Doxorubicin (DOX) covalently bonded onto said shell. Said magnetic nanomedicine is capable of improving its thermal stability, and it can be dissolved uniformly in water, plus its superparamagnetic property, thus it can be guided by an outside magnetic field to concentrate to the site of tumor distribution to increase the local medicine concentration and enhance therapy effect. | 12-27-2012 |
20130011485 | MAGNETIC NANOMEDICINE FOR INHIBITING/TREATING HUMAN PROSTATE CANCER - The present invention discloses a magnetic nanomedicine for inhibiting/treating human prostate cancer, which comprises a core containing a magnetic particle having a diameter of less than 10 nm; a shell made of a carboxylated polyaniline and encapsulating the core; and a medicine covalently linked to the shell and able to inhibit/treat prostate cancer. The magnetic nanomedicine of the present invention not only has superior thermal stability and but also has water solubility higher than that of the conventional anti-prostate cancer medicine. Further, the magnetic nanomedicine of the present invention can be magnetically conducted to the cancer area to increase the local concentration of medicine and enhance the therapeutic effect. | 01-10-2013 |
20130251814 | MAGNETIC NANODRUG FOR TREATING THROMBOSIS - The present invention discloses a magnetic nanodrug for treating thrombosis, which comprises a core formed of magnetic nanoparticles, a shell enveloping the core and made of carboxyl-functionalized polyaniline, and a thrombosis-treatment drug covalently bonded to the shell. The magnetic nanodrug of the present invention is non-toxic to vascular endothelial cells, has superior stability, features superparamagnetism, and can be uniformly dissolved in water. Therefore, the magnetic nanodrug for treating thrombosis can be guided by an external magnetic field to concentrate on a specified region and increase the effect of thrombosis treatment. | 09-26-2013 |
Patent application number | Description | Published |
20090262688 | RATE ADAPTATION METHODS FOR WIRELESS COMMUNICATION APPARATUS, AND WIRELESS COMMUNICATION APPARATUS FOR PERFORMING WIRELESS COMMUNICATION WITH RATE ADAPTATION - A rate adaptation method for a wireless communication apparatus includes: determining whether to use a first mode or a second mode according to at least one estimation value, where the first mode and the second mode correspond to different values of an overall data rate of the wireless communication apparatus. A wireless communication apparatus for performing wireless communication with rate adaptation includes: a processing circuit; and a wireless receiver and a wireless transmitter, both coupled to the processing circuit. The processing circuit determines at least one estimation value regarding communication quality of the wireless communication apparatus, and further determines whether to use a first mode or a second mode according to the estimation value, where the first mode and the second mode correspond to different values of an overall data rate of the wireless communication apparatus. | 10-22-2009 |
20100166093 | METHOD FOR ESTIMATING PHASE ERROR IN MIMO OFDM COMMUNICATIONS SYSTEM - A method for estimating a phase error existing in a receiver of a MIMO OFDM communications system is disclosed. The method includes executing Hermitian transpose on channel coefficient matrix of the MIMO OFDM communications system for generating Hermitian-transposed channel coefficient matrix, multiplying received signal matrix of the receiver with the Hermitian-transposed channel coefficient matrix for generating converted signals, summing products of the converted signals and complex conjugates of pilot signals corresponding to the converted signals for generating a sum result, and generating the phase error according to the sum result, the converted signals, and the complex conjugates of the pilot signals. The pilot signals are extracted from the received signal matrix. | 07-01-2010 |
20100202570 | Method for estimating phase error in MIMO OFDM communications system - A method for estimating a phase error existing in a receiver of a MIMO OFDM communications system is disclosed. The method includes executing Hermitian transpose on channel coefficient matrix of the MIMO OFDM communications system for generating Hermitian-transposed channel coefficient matrix, multiplying received signal matrix of the receiver with the Hermitian-transposed channel coefficient matrix for generating converted signals, summing products of the converted signals and complex conjugates of pilot signals corresponding to the converted signals for generating a sum result, and generating the phase error according to the sum result, the converted signals, and the complex conjugates of the pilot signals. The pilot signals are extracted from the received signal matrix. | 08-12-2010 |
20120140848 | Transmitting Terminal and Transmit Antenna Selecting Method Thereof - A transmitting terminal includes a signal processing unit, M | 06-07-2012 |
Patent application number | Description | Published |
20110174774 | METHOD OF DESCUMMING PATTERNED PHOTORESIST - A method of descumming a patterned photoresist is provided. First a material layer to be etched is provided. The material layer is covered by a patterned photoresist. Then a descum process is preformed to descum the edge of the patterned photoresist by nitrogen. Finally, the descummed patterned photoresist is used as a mask for etching the material layer. | 07-21-2011 |
20110223768 | Method for Forming Contact Opening - A method for forming contact openings is provided. First, a semiconductor device is formed on a substrate. Next, an etching stop layer, a first dielectric layer and a patterned photoresist layer are sequentially formed on the substrate. Next a portion of the first dielectric layer and a portion of the etching stop layer are removed to form an opening, wherein the portion of the first dielectric layer and the portion of the etching stop layer are not covered by the patterned photoresist layer. Next, the patterned photoresist layer is removed. Next, an over etching process is performed to remove the etching stop layer at a bottom of the opening and expose the semiconductor device in a nitrogen-free environment. The reactant gas of the over etching process includes fluorine-containing hydrocarbons, hydrogen gas and argon gas. | 09-15-2011 |
20120220113 | Method of Manufacturing Semiconductor Device Having Metal Gate - The present invention provides a method of manufacturing semiconductor device having metal gate. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench and then a first metal layer and a first material layer are formed in the first trench. Next, the first metal layer and the first material layer are flattened. The second sacrifice gate is removed to form a second trench and then a second metal layer and a second material layer are formed in the second trench. Lastly, the second metal layer and the second material layer are flattened. | 08-30-2012 |
20120315748 | METHOD FOR FABRICATING AN APERTURE - A method for fabricating an aperture is disclosed. The method includes the steps of: forming a hard mask containing carbon on a surface of a semiconductor substrate; and using a non-oxygen element containing gas to perform a first etching process for forming a first aperture in the hard mask. | 12-13-2012 |
20130005151 | METHOD FOR FORMING CONTACT HOLES - In an exemplary method for forming contact holes, a substrate overlaid with an etching stop layer and an interlayer dielectric layer in that order is firstly provided. A first etching process then is performed to form at least a first contact opening in the interlayer dielectric layer. A first carbon-containing dielectric layer subsequently is formed overlying the interlayer dielectric layer and filling into the first contact opening. After that, a first anti-reflective layer and a first patterned photo resist layer are sequentially formed in that order overlying the carbon-containing dielectric layer. Next, a second etching process is performed by using the first patterned photo resist layer as an etching mask to form at least a second contact opening in the interlayer dielectric layer. | 01-03-2013 |
20130109151 | METHOD FOR FORMING VOID-FREE DIELECTRIC LAYER | 05-02-2013 |
20140038399 | METHOD FOR FABRICATING AN APERTURE - A method for fabricating an aperture is disclosed. The method includes the steps of: forming a hard mask containing carbon on a surface of a semiconductor substrate; and using a non-oxygen element containing gas to perform a first etching process for forming a first aperture in the hard mask. Before forming the hard mask, a gate which includes a contact etch stop layer and a dielectric layer is formed on the semiconductor substrate. | 02-06-2014 |
20140073104 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device is disclosed in the present invention. First, at least one gate structure and plurality of source/drain regions on a substrate are formed, a dielectric layer is then formed on the substrate, a first contact hole and a second contact hole are formed in the dielectric layer, respectively on the gate structure and the source/drain region, and a third contact hole is formed in the dielectric layer, wherein the third contact hole overlaps the first contact hole and the second contact hole. | 03-13-2014 |
20140315365 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device is provided. At least one gate structure including a dummy gate is formed on a substrate. A contact etch stop layer and a dielectric layer are formed to cover the gate structure. A portion of the contact etch stop layer and a portion of the dielectric layer are removed to expose the top of the gate structure. A dry etching process is performed to remove a portion of the dummy gate of the gate structure. A hydrogenation treatment is performed to the surface of the remaining dummy gate. A wet etching process is performed to remove the remaining dummy gate and thereby form a gate trench. | 10-23-2014 |
Patent application number | Description | Published |
20110221494 | PHASE-LOCKED LOOP START UP CIRCUIT - A phase-locked loop (PLL) circuit includes a voltage-controlled oscillator (VCO) having a VCO input for receiving a control voltage and a VCO output, a feedback loop between the VCO input and the VCO output, and a start-up circuit having a start-up circuit input and a start-up circuit output. The start-up circuit output is coupled to the VCO input and the start-up circuit input is coupled to the VCO output. The start-up circuit provides a voltage at its start-up circuit output during a start-up phase, which terminates after a predetermined number of feedback pulses are detected by the start-up circuit. | 09-15-2011 |
20110279175 | SYSTEM AND METHOD FOR RC CALIBRATION USING PHASE AND FREQUENCY - An RC filter is calibrated to a desired cutoff frequency by initializing the filter with a cutoff frequency. An input signal is filtered by the RC filter to provide a filter output signal having phase and frequency values. The cutoff frequency of the RC filter is adjusted based on the phase and frequency values of the filter output signal if the phase and frequency values do not satisfy a predetermined condition. The filtering and adjusting are repeated until the phase and frequency values of the filter output signal satisfy the predetermined condition. A calibration apparatus has a frequency generator, a resistor-capacitor (RC) filter, a phase comparator, a frequency detector, and a state machine. The phase comparator, frequency detector, and state machine are configured to calibrate the RC filter to a cutoff frequency specified by the reference signal based on a filter output signal of the RC filter. | 11-17-2011 |
20130038366 | BIST CIRCUIT FOR PHASE MEASUREMENT - A BIST circuit for high speed applications includes a phase difference detection circuit, a period-to-current conversion circuit having an input coupled to an output of the phase difference detection circuit and a current-to-voltage conversion circuit coupled to an output of the period-to-current conversion circuit. The phase difference detection circuit includes first NAND logic for receiving as inputs an input clock signal and a delayed version of an inverted version of the input clock signal; second NAND logic for receiving as inputs the inverted version of the input clock signal and a delayed version of the input clock signal; third NAND logic for receiving as inputs the input clock signal and the delayed version of the input clock signal; and fourth NAND logic for receiving as inputs the inverted version of the input clock signal and a delayed version of the inverted version of the input clock signal. | 02-14-2013 |
20130271106 | Optimization Methodology and Apparatus for Wide-Swing Current Mirror with Wide Current Range - A current mirror circuit includes an input portion configured to conduct a bias current, and a first current source circuit coupled to the input portion and configured to generate the bias current, and vary the bias current over a range of currents based on a first group of weightings associated therewith. The current mirror circuit also includes an output portion configured to conduct an operational current, wherein the output portion is coupled to the input portion, and a second current source circuit coupled to the output portion and configured to generate the operational current, and vary the operational current over a range of currents based on a second group of weightings associated therewith. The first group of weightings and the second group of weightings are different. | 10-17-2013 |
20130300382 | REGULATING CASCODE CIRCUIT WITH SELF-CALIBRATION CAPABILITY - A circuit comprises a cascode core circuit and a current adjustor circuit. The cascode core circuit has an output node and a current path (ID). The current adjustor circuit is configured to change a current on the current path in response to a change in a voltage at the output node. The cascode core circuit comprises a first transistor, a second transistor, and a third transistor. A first terminal of the first transistor is coupled to a second terminal of the second transistor and to a third terminal of the third transistor. A first terminal of the second transistor is configured as the output node. A first terminal of the third transistor is coupled to a third terminal of the second transistor. The current path is through the first terminal of the third transistor. | 11-14-2013 |
20130342252 | Real Time Automatic and Background Calibration at Embedded Duty Cycle Correlation - The present disclosure relates to a clock generation system. The system includes a clock source, a tuning buffer, an output buffer, a duty cycle measurement circuit and an automatic calibration component. The clock source generates a clock signal. The tuning buffer is configured to generate a corrected clock signal from the clock signal according to adjustment values. The output buffer is configured to generate an output clock signal from the corrected clock signal. The duty cycle measurement circuit is configured measure a duty cycle of the output clock signal. The automatic calibration component is configured to generate the adjustment values according to the duty cycle measurement and the specification values. | 12-26-2013 |
Patent application number | Description | Published |
20090010022 | MULTI-FUNCTIONAL LED LAMP - A multi-functional LED lamp is mainly composed of a lamp base, an illuminant device, a light guide device and a lampshade. The illuminant device is provided with plural LED bulbs planted on a laminate that is fixed on the lamp base with a heat-conductive medium spread in between. Heat generated by the illuminant device is dispersed by the lamp base. The light guide device is transparent, placed at a place where the illuminant device is to emit, used to conduct the light beams and promote its brightness. The lampshade is covered on the light guide device and the illuminant device. With features of low energy consumption, long service life and high luminous efficiency for LEDs and a good cooling member, the LED lamp is really energy saving and high-efficient. | 01-08-2009 |
20090316396 | HIGH-EFFICIENCY LED LAMP - A high efficiency LED lamp includes a positioning frame base, LED bars, a light guide plate, a reflection sheet, an optical film, a power supply unit and a protective cover. The LED bars and the light guide plate are disposed at the inner side of the positioning frame base; the reflection sheet is stuck at one side of the light guide plate; the optical film is disposed at the other side of the light guide plate, and the protective cover is covered on foresaid members. The power supply unit is installed at the rear side of the positioning frame base for converting and supplying DC power for the LED bars. The optical film can be arranged in different modes for adjusting the lighting angles of the LED bars, and the power supply unit can function to supply steady DC power. The LED lamp of this invention can concentrate light and has excellent lighting effect. | 12-24-2009 |
Patent application number | Description | Published |
20110141274 | Depth Detection Method and System Using Thereof - A depth detection method includes the following steps. First, first and second video data are shot. Next, the first and second video data are compared to obtain initial similarity data including r×c×d initial similarity elements, wherein r, c and d are natural numbers greater than 1. Then, an accumulation operation is performed, with each similarity element serving as a center, according to a reference mask to obtain an iteration parameter. Next, n times of iteration update operations are performed on the initial similarity data according to the iteration parameter to generate updated similarity data. Then, it is judged whether the updated similarity data satisfy a character verification condition. If yes, the updated similarity data is converted into depth distribution data. | 06-16-2011 |
20110317925 | Method for Recognizing Three-Dimensional Control Point and Computer Readable Medium Using the Same Thereof - A method for recognizing three-dimensional control points and a computer readable medium using the same are disclosed. The method for recognizing three-dimensional control points comprises the following steps. A depth information item corresponding to an image captured by an image capturing apparatus is received. A three-dimensional block information item corresponding to a three-dimensional block is generated according to the depth information. At least one reference plane is generated according to the depth information. At least one connection group is generated according to the three-dimensional block information and the reference plane. A three-dimensional block nearest to the image capturing apparatus is selected as a control point from the connection group. | 12-29-2011 |
20120139925 | System for Estimating Location of Occluded Skeleton, Method for Estimating Location of Occluded Skeleton and Method for Reconstructing Occluded Skeleton - A system for estimating a location of an occluded skeleton, a method for estimating a location of an occluded skeleton and a method for reconstructing an occluded skeleton are provided. The method for estimating a location of an occluded skeleton comprises the following steps: Firstly, a trace of a reference central point of a body is estimated according to a plurality of continuously moving images. Next, a human movement state is estimated according to the trace and a motion information of the continuously moving images free of skeleton occlusion. Then, a possible range of the occluded skeleton for maintaining human balance is calculated according to the human movement state. Afterwards, a current motion level of the occluded skeleton is predicted according to a historic motion information of the occluded skeleton. Lastly, the location of the occluded skeleton is estimated according to the current motion level and the possible range. | 06-07-2012 |
20140099017 | METHOD AND APPARATUS FOR RECONSTRUCTING THREE DIMENSIONAL MODEL - A method and an apparatus for reconstructing a three dimensional model of an object are provided. The method includes the following steps. A plurality of first depth images of an object are obtained. According to a linking information of the object, the first depth images are divided into a plurality of depth image groups. The linking information records location information corresponding to a plurality of substructures of the object. Each depth image group includes a plurality of second depth images, and the substructures correspond to the second depth images. According to the second depth image and the location information corresponding to each substructure, a local module of each substructure is built. According to the linking information, the local models corresponding to the substructures are merged, and the three-dimensional model of the object is built. | 04-10-2014 |
Patent application number | Description | Published |
20110255600 | METHOD FOR PERFORMING LOCALIZED MULTIHYPOTHESIS PREDICTION DURING VIDEO CODING OF A CODING UNIT, AND ASSOCIATED APPARATUS - A method for performing localized multihypothesis prediction during video coding of a coding unit includes: dividing the coding unit into a plurality of sub-coding units; and performing motion vector prediction of each of the sub-coding units. More particularly, the step of performing motion vector prediction of each of the sub-coding units further includes: obtaining a plurality of motion vectors for multihypothesis motion compensation of a specific sub-coding unit of the sub-coding units from a plurality of other sub-coding/coding units. The method further includes performing multihypothesis motion compensation on the specific sub-coding unit according to the plurality of motion vectors, and more particularly, includes utilizing a linear combination of a plurality of pixel values of the plurality of other sub-coding/coding units as a predicted pixel value of the specific sub-coding unit. An associated apparatus is also provided. | 10-20-2011 |
20120027097 | METHOD FOR PERFORMING LOCALIZED MULTIHYPOTHESIS PREDICTION DURING VIDEO CODING OF A CODING UNIT, AND ASSOCIATED APPARATUS - A method for performing localized multihypothesis prediction during video coding of a coding unit includes processing the coding unit. More particularly, the step of processing the coding unit further includes: obtaining at least two sets of motion information derived from a set of coded units for multihypothesis motion compensation of the coding unit; and utilizing a linear combination of a plurality of pixel values derived from the at least two sets of motion information derived from the set of coded units as a predicted pixel value of the coding unit. An associated apparatus is also provided. | 02-02-2012 |
20120063514 | METHOD FOR PERFORMING HYBRID MULTIHYPOTHESIS PREDICTION DURING VIDEO CODING OF A CODING UNIT, AND ASSOCIATED APPARATUS - A method for performing hybrid multihypothesis prediction during video coding of a coding unit includes: processing a plurality of sub-coding units in the coding unit; and performing motion vector derivation of a portion of the sub-coding units. More particularly, the step of performing motion vector derivation of the portion of the sub-coding units further includes: deriving a plurality of motion vectors for multihypothesis motion-compensated prediction of a specific sub-coding unit of the portion of the sub-coding units from at least one other sub-coding/coding unit or by performing motion estimation. The method further includes performing multihypothesis motion-compensated prediction on the specific sub-coding unit according to the plurality of motion vectors, and more particularly, includes utilizing a linear combination of a plurality of pixel values derived from the plurality of motion vectors as a predicted pixel value of the specific sub-coding unit. An associated apparatus is also provided. | 03-15-2012 |
20130063374 | METHOD FOR CONVERTING CONTROL INPUT OF INPUT DOMAIN INTO CONTROL OUTPUT OF CONTROL DOMAIN USING VARIABLE CONTROL RESOLUTION TECHNIQUE, AND RELATED CONTROL APPARATUS THEREOF - An exemplary method for determining a control output in a control domain includes: obtaining a control input of an input domain, wherein the control input includes a previous input value and a current input value; and dynamically adjusting a control resolution setting, and converting the control input of the input domain into the control output in the control domain according to the control resolution setting, wherein the control output includes a previous output value and a current output value corresponding to the previous input value and the current input value, respectively, the control resolution setting for the current input value is determined according to at least the previous input value, and the current output value is identical to the previous output value when the current input value and the previous input value are generated in response to a same user input. | 03-14-2013 |
20130077852 | METHOD AND APPARATUS FOR GENERATING FINAL DEPTH INFORMATION RELATED MAP THAT IS RECONSTRUCTED FROM COARSE DEPTH INFORMATION RELATED MAP THROUGH GUIDED INTERPOLATION - A method for generating a final depth information related map includes the following steps: receiving a coarse depth information related map, wherein a resolution of the coarse depth information related map is smaller than a resolution of the final depth information related map; and outputting the final depth information related map reconstructed from the coarse depth information related map by receiving an input data and performing a guided interpolation operation upon the coarse depth information related map according to the input data. | 03-28-2013 |
20130208804 | Method and Apparatus for Parsing Error Robustness of Temporal Motion Vector Prediction - A method and apparatus for deriving a motion vector predictor (MVP) are disclosed. The MVP is selected from spatial MVP and temporal MVP candidates. The method uses a flag to indicate whether temporal MVP candidates are disabled. If the flag indicates that the temporal MVP candidates are disabled, the MVP is derived from the spatial MVP candidates only. Otherwise, the MVP is derived from the spatial and temporal MVP candidates. The method may further skip spatial redundant MVP removal by comparing MV values. Furthermore, the parsing error robustness scheme determines a forced temporal MVP when a temporal MVP is not available and the temporal MVP candidates are allowed as indicated by the flag. The flag may be incorporated in sequence, picture, slice level, or a combination of these levels. | 08-15-2013 |
20130243098 | METHOD AND APPARATUS FOR DERIVATION OF MOTION VECTOR CANDIDATE AND MOTION VECTOR PREDICTION CANDIDATE - An apparatus and method for deriving a motion vector predictor are disclosed. A search set comprising of multiple (spatial, or temporal) search MVs with priority is determined, wherein the search MVs for multiple neighboring reference block or one or more co-located reference blocks arc configured into multiple search MV groups. In order to improve coding efficiency, embodiments according to the present invention, perform redundancy check every time after a search MV group is searched to determine whether an available search MV found. If an available search MV is found and the available search MV is not the same as a previously derived motion vector predictor (MVP), the available search MV is used as the MVP and the MVP derivation process terminates. Otherwise, the MVP derivation process moves to the next reference block. The search MV group can be configured to include different search MV(s) associated with reference blocks. | 09-19-2013 |
20130249864 | METHODS FOR INPUT-OUTPUT CALIBRATION AND IMAGE RENDERING - One of the embodiments of the invention provides an input-output calibration method performed by a processing unit connected to an output device and an input device. The output device and the input device correspond to an output device coordinate system and an input device coordinate system, respectively. The processing unit first derives M calibration points' coordinates in the input device coordinate system by using the input device to sense a viewer specifying the M calibration points' positions, wherein M is a positive integer. Then, the processing unit uses the M calibration points' coordinates in the output device coordinate system and coordinates in the input device coordinate system to derive the relationship between the output device coordinate system and the input device coordinate system. | 09-26-2013 |
20130266223 | REGION GROWING METHOD FOR DEPTH MAP/COLOR IMAGE - An exemplary region growing method include at least the following steps: selecting a seed point of a current frame as an initial growing point of a region in the current frame; determining a background confidence value at a neighboring pixel around the seed point; and utilizing a processing unit for checking if the neighboring pixel is allowed to be included in the region according to at least the background confidence value. | 10-10-2013 |
20130303247 | INTERACTION DISPLAY SYSTEM AND METHOD THEREOF - An interaction display system applied in a mobile device is provided. The system has a first camera, facing a first side of the mobile device configured to capture first images of a user; a second camera, facing a second side opposite to the first side of the mobile device, configured to capture second images of a scene; and a processing unit coupled to the first camera and the second camera directly, configured to perform interactions between the user and the scene utilizing the first images and the second images simultaneously captured by the first camera and the second camera. | 11-14-2013 |
20140200060 | INTERACTION DISPLAY SYSTEM AND METHOD THEREOF - An interaction display system applied in a mobile device is provided. The system has a camera unit configured to capture images of a scene; a motion detection unit configured to detect motions of the mobile device during capturing the images; and a processing unit coupled to the camera unit and the motion detection unit, configured to estimate a geometry of the scene according to the captured images and the detected motions. | 07-17-2014 |
20150033157 | 3D DISPLAYING APPARATUS AND THE METHOD THEREOF - A 3D displaying method, comprising: acquiring distance information map from at least one image; receiving control information from a user input device; modifying the distance information map according to the control information to generate modified distance information map; generating an interactive 3D image according to the modified distance information map; and displaying the interactive 3D image. | 01-29-2015 |
Patent application number | Description | Published |
20100001416 | WAFER LASER-MARKING METHOD AND DIE FABRICATED USING THE SAME - A wafer laser-marking method is provided. First, a wafer having a first surface (an active surface) and a second surface (a back surface) opposite to each other is provided. Next, the wafer is thinned. Then, the thinned wafer is fixed on a tape such that the second surface of the wafer is attached to the tape. Finally, the laser marking step is performed, such that a laser light penetrates the tape and marks a pattern on the second surface of the wafer. There are glue residuals remained in the laser-marking pattern of the die manufactured according to the laser-marking method of the invention, and the components of the glue residuals at least include elements of silicon, carbon and oxygen. | 01-07-2010 |
20110241194 | Stacked Semiconductor Device Package Assemblies with Reduced Wire Sweep and Manufacturing Methods Thereof - An embodiment of a stacked package assembly includes: (1) a first semiconductor device package including: (a) a semiconductor device including back and lateral surfaces; (b) a package body including an upper surface and substantially covering the back and lateral surfaces of the device; and (c) a first conductive contact adjacent to the upper surface of the body and electrically connected to the device; (2) a second semiconductor device package disposed above the upper surface of the body; (3) a conductive bump adjacent to the first contact and to the second device package; (4) a second conductive contact external to the first and the second device packages; and (5) a conductive wire electrically connecting the first and the second device packages to the second contact, a first end of the wire adjacent to the first contact and at least partially covered by the bump. | 10-06-2011 |
20110316122 | WAFER LASER-MARKING METHOD AND DIE FABRICATED USING THE SAME - A wafer laser-marking method is provided. First, a wafer having a first surface (an active surface) and a second surface (a back surface) opposite to each other is provided. Next, the wafer is thinned. Then, the thinned wafer is fixed on a non-UV tape such that the second surface of the wafer is attached to the tape. Finally, the laser marking step is performed, such that a laser light penetrates the non-UV tape and marks a pattern on the second surface of the wafer. According to the laser-marking method of the embodiment, the pattern is formed by the non-UV residuals left on the second surface of the wafer, and the components of the glue residuals at least include elements of silicon and carbon. | 12-29-2011 |