Patent application number | Description | Published |
20080302672 | SYSTEMS AND METHODS FOR SENSING - A sensor system for measuring a plurality of chemical species is disclosed. The sensor system includes a plurality of semiconductor device sensor elements, wherein each sensor element includes at least one wide band gap semiconductor layer and at least one catalytic layer configured to have an electrical property modifiable on exposure to an analyte including one or more chemical species; and an acquisition and analysis system configured to receive sensor signals from the plurality of sensor elements and to use multivariate analysis techniques to analyze the sensor signals to provide multivariate analyte measurement data. | 12-11-2008 |
20090140293 | HETEROSTRUCTURE DEVICE AND ASSOCIATED METHOD - A heterostructure device or article includes a carrier transport layer, a back channel layer and a barrier layer. The carrier transport layer has a first surface and a second surface opposing to the first surface. The back channel layer is secured to the first surface of the carrier transport layer and the barrier layer is secured to the second surface of the carrier transport layer. Each of the carrier transport layer, the back channel layer and the barrier layer comprises an aluminum gallium nitride alloy. The article further includes a 2D electron gas at an interface of the second surface of the carrier transport layer and a surface of the barrier layer. The 2D electron gas is defined by a bandgap differential at an interface, which allows for electron mobility. A system includes a heterostructure field effect transistor that includes the article. | 06-04-2009 |
20090159929 | HETEROSTRUCTURE DEVICE AND ASSOCIATED METHOD - A heterostructure device includes a semiconductor multi-layer structure that has a first region, a second region and a third region. The first region is coupled to a source electrode and the second region is coupled to a drain electrode. The third region is disposed between the first region and the second region. The third region provides a switchable electrically conductive pathway from the source electrode to the drain electrode. The third region includes iodine ions. A system includes a heterostructure field effect transistor that includes the device. | 06-25-2009 |
20120171824 | HETEROSTRUCTURE DEVICE AND ASSOCIATED METHOD - A method of manufacturing a heterostructure device is provided that includes implantation of ions into a portion of a surface of a multi-layer structure. Iodine ions are implanted between a first region and a second region to form a third region. A charge is depleted from the two dimensional electron gas (2DEG) channel in the third region to form a reversibly electrically non-conductive pathway from the first region to the second region. On applying a voltage potential to a gate electrode proximate to the third region allows electrical current to flow from the first region to the second region. | 07-05-2012 |
Patent application number | Description | Published |
20100093116 | DIMENSION PROFILING OF SIC DEVICES - There is provided a method for dimension profiling of a semiconductor device. The method involves incorporating a feature comprising a detectable element into the device, and thereafter detecting the detectable element to determine a dimension of the feature. This information can be used for the determination of a dimension of buried channels, and also for end-point detection of CMP processes. | 04-15-2010 |
20100140730 | SEMICONDUCTOR DEVICES AND SYSTEMS - A semiconductor device is disclosed. The semiconductor device comprises, a first region of a first conductivity type, a second region of a second conductivity type disposed adjacent to the first region to form a p-n junction structure, a resistance modification region of the second conductivity type, and a field response modification region of the second conductivity type disposed between the resistance modification region and the second region, wherein the field response modification region comprises a varying dopant concentration distribution along a thickness direction of the field response modification region. | 06-10-2010 |
20110138813 | IMPURITY DETECTION IN COMBUSTOR SYSTEMS - The present invention discloses a combustor system and method of measuring impurities in the combustion system. The combustion system includes an up-stream fuel injection point; a down-stream turbine combustor; a flame zone in the turbine combustor comprising a plurality of axial sub-zones; an optical port assembly configured to obtain a non-axial, direct, optical view of at least one of the plurality of axial sub-zones, and an impurity detection system in optical communication with the optical port assembly. | 06-16-2011 |
20110221456 | SENSOR SYSTEM AND METHODS FOR ENVIRONMENTAL SENSING - A sensor system, and an associated method for detecting harsh environmental conditions, is provided. The sensor system includes at least one sensor having an electrical sensing element. The electrical sensing element is based on certain classes of composite materials: (a) silicon carbide (SiC); (Mo,W) | 09-15-2011 |
20130105816 | METHOD AND SYSTEM FOR TRANSIENT VOLTAGE SUPPRESSORS | 05-02-2013 |
20130328064 | METHOD AND SYSTEM FOR TRANSIENT VOLTAGE SUPPRESSORS - A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The TVS assembly includes a semiconductor die in a mesa structure that includes a first layer of a first wide band gap semiconductor having a conductivity of a first polarity, a second layer of the first or a second wide band gap semiconductor having a conductivity of a second polarity coupled in electrical contact with the first layer wherein the second polarity is different than the first polarity. The TVS assembly also includes a third layer of the first, the second, or a third wide band gap semiconductor having a conductivity of the first polarity coupled in electrical contact with the second layer. The layer having a conductivity of the second polarity is lightly doped relative to the layers having a conductivity of the first polarity. | 12-12-2013 |
20140264775 | METHOD AND SYSTEM FOR TRANSIENT VOLTAGE SUPPRESSION - A transient voltage suppression (TVS) device and a method of forming the device are provided. The device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer and comprising an ion implanted material structure between 0.1 micrometers (μm) and 22.0 μm thick, the second layer operating using punch-through physics, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer. | 09-18-2014 |
20150028469 | SEMICONDUCTOR ASSEMBLY AND METHOD OF MANUFACTURE - A monolithically integrated semiconductor assembly is presented. The semiconductor assembly includes a substrate including silicon (Si), and gallium nitride (GaN) semiconductor device is fabricated on the substrate. The semiconductor assembly further includes at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, wherein the TVS structure is in electrical contact with the GaN semiconductor device. The TVS structure is configured to operate in a punch-through mode, an avalanche mode, or combinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. Methods of making a monolithically integrated semiconductor assembly are also presented. | 01-29-2015 |
20150034969 | METHOD AND SYSTEM FOR A SEMICONDUCTOR DEVICE WITH INTEGRATED TRANSIENT VOLTAGE SUPPRESSION - A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value. | 02-05-2015 |
20150162743 | METHOD AND SYSTEM FOR OVER-VOLTAGE PROTECTION USING TRANSIENT VOLTAGE SUPPRESSION DEVICES - A method of fabricating an overvoltage protection device and an over-voltage circuit protection device are provided. The over-voltage circuit protection device includes a plurality of transient voltage suppression (TVS) devices coupled in electrical parallel. | 06-11-2015 |