Patent application number | Description | Published |
20080210460 | Circuit board structure with capacitors embedded therein and method for fabricating the same - A circuit board structure with capacitors embedded therein and a method for fabricating the same are disclosed. The structure comprises at least two core layers individually comprising a dielectric layer having two opposite surfaces, circuit layers disposed on the outsides of the two opposite surfaces of the dielectric layer, and at least two capacitors embedded respectively on the insides of the two opposite surfaces of the dielectric layer and individually electrically connecting with the circuit layer at the same side; at least one adhesive layer disposed between the core layers to combine the core layers as a core structure; and at least one conductive through hole penetrating the core layers and the adhesive layer, and electrically connecting the circuit layers of the core layers. Accordingly, the present invention can improve the flexibility of circuit layout, and realize parallel connection between the capacitors to provide more capacitance. | 09-04-2008 |
20080224295 | Package structure and stacked package module using the same - A package structure with chip embedded therein is disclosed, which comprises a circuit board having a first surface, an opposite second surface and a through cavity penetrating the circuit board, wherein the first surface of the circuit board has a plurality of first conductive pads and a plurality of wire bonding pads disposed thereon, and the second surface of the circuit board has a plurality of second conductive pads disposed thereon; and a chip embedded in the through cavity of the circuit board, wherein the gap between the through cavity and the chip is filled with a filling material, the chip has an active surface with a plurality of electrode pads and an inactive surface, and the electrode pads electrically connect to the wire bonding pads of the circuit board by a plurality of metal lines. The present invention further provides a package module using the aforementioned package structure. | 09-18-2008 |
20080230892 | Chip package module - A chip package module is disclosed, which comprises a core plate and two rigid plates individually having a circuit layer. The core plate is sandwiched in between the two rigid plates to form a composite circuit board. Furthermore, the two rigid plates individually have a cavity to expose the surface of the core plate. In addition, the cavities individually have at least one chip disposed therein, and each chip electrically connects to the composite circuit board. The present invention reduces the height of the package module and makes the package module lighter and smaller. | 09-25-2008 |
20090032930 | PACKAGING SUBSTRATE HAVING CHIP EMBEDDED THEREIN AND MANUFACTURING METHOD THEREOF - A packaging substrate having a chip embedded therein, comprises a first aluminum substrate having a first cavity therein; a second aluminum substrate having a second cavity corresponding to the first cavity; a dielectric layer disposed between the first aluminum substrate and the second aluminum substrate; a chip embedded in the first cavity and the second cavity, having an active surface with a plurality of electrode pads thereon; and one built-up structure disposed on the surface of the first aluminum substrate and the active surface of the chip, wherein the built-up structure has a plurality of conductive vias electrically connecting to the electrode pads. The substrate warpage is obviously reduced by the assistance of using aluminum or aluminum alloy as the material of the substrate. Also, a method of manufacturing a packaging substrate having a chip embedded therein is disclosed. | 02-05-2009 |
Patent application number | Description | Published |
20110063434 | Monitor system for monitoring riverbed elevation change at bridge pier - A monitor system for monitoring riverbed elevation changes at bridge piers is revealed. The monitor system includes a container, a rail, a holder, a photographic unit, a processor and a transmission unit. The container is disposed at a pier under the water and the rail is mounted in the container. The holder is arranged at the rail and is moved on the rail. The photographic unit is disposed on the holder to capture a monitor image of a riverbed under the water. As to the processor, it processes the monitor image so as to learn elevation change of the riverbed under the water. By the transmission unit, the riverbed elevation change is sent to a remote monitor unit so as to get the riverbed elevation according to the riverbed elevation change. Thus the riverbed elevation change at the bridge pier is monitored in real time. | 03-17-2011 |
20110242309 | MULTI-LENS MONITORING SYSTEM FOR BED ELEVATION AROUND A PIER - The present invention relates to a multi-lens monitoring system for bed elevation around a pier according to the present invention comprises a container, a holder, a plurality of photographing units, and a processing module. The container is disposed on the pier; the holder is disposed inside the container; and the plurality of photographing units are disposed on the holder for photographing the bed under water and producing a monitoring image. The processing module is used for activating one of the plurality of photographing units for photographing the bed under water. The processing module also analyzes the monitoring image, gives the elevation variation of the bed, and transmits the elevation variation of the bed to a remote monitoring unit for real-timely monitoring and recording. During the monitoring process, the processing module will change activating one of the plurality of photographing units according to the monitoring image, and hence the electrical power can be saved. | 10-06-2011 |
20110255735 | PROBE MONITORING SYSTEM FOR RIVERBED ELEVATION MONITORING AT BRIDGE PIERS - A probe monitoring system for riverbed elevation monitoring at bridge piers is revealed. The system includes a housing, a measuring rod, a moving member, a control module, a photographic unit and a sensing unit. The housing is fixed on the pier. Both the moving member for driving the measuring rod and the control module for control of the moving member are mounted in the housing. When the control module drives the measuring rod to move downward and the sensing unit on the bottom of the measuring rod approaches the riverbed, a sensing signal is sent to the control module. Thus the moving member stops moving the measuring rod and the photographic unit takes pictures of the measuring rod to generate an image. Then the riverbed elevation is obtained according to the image or the movement of the moving member and is sent to a remote monitor unit for real-time monitoring. | 10-20-2011 |
Patent application number | Description | Published |
20080315308 | LOW ON-RESISTANCE LATERAL DOUBLE-DIFFUSED MOS DEVICE AND METHOD OF FABRICATING THE SAME - A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region. | 12-25-2008 |
20110204441 | LOW ON-RESISTANCE LATERAL DOUBLE-DIFFUSED MOS DEVICE - A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region. | 08-25-2011 |
20130277725 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor memory device includes a substrate, a well region in the substrate, a patterned first dielectric layer on the substrate extending over the well region, a patterned first gate structure on the patterned first dielectric layer, a patterned second dielectric layer on the patterned first gate structure, and a patterned second gate structure on the patterned second dielectric layer. The patterned first gate structure includes a first section extending in a first direction and a second section extending in a second direction orthogonal to the first section, the first section and the second section intersecting each other in a cross pattern. The patterned second gate structure includes at least one of a first section extending in the first direction over the first section of the patterned first gate structure or a second section extending in the second direction over the second section of the patterned first gate structure. | 10-24-2013 |
20140266409 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor structure with a high voltage area and a low voltage area includes a substrate of a first conductivity type accommodating the high voltage area and the low voltage area. A resistor is on the substrate, connecting the high voltage area and the low voltage area, and the resistor resides substantially in the high voltage area. The structure further includes a first doped region of the first conductivity type in the substrate between the high voltage area and the low voltage area, and a second doped region of a second conductivity type between the substrate and the first doped region. Moreover, an insulating layer is formed between the resistor and the first doped region. | 09-18-2014 |
20150118820 | METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE - A method of manufacturing a semiconductor structure with a high voltage area and a low voltage area is provided. The method includes the following steps: providing a substrate of a first conductivity type; forming a second doped region of a second conductivity type in the substrate by a first implantation; forming a first doped region of a first conductivity type in the second doped region by a second implantation; forming an insulating layer on the substrate; forming a resistor on the insulating layer, wherein the resistor is electrically connecting the high voltage area and the low voltage area; and forming a conductor electrically connected to the resistor. The step of forming a first doped region defines the high voltage area and the low voltage area. | 04-30-2015 |