Patent application number | Description | Published |
20080283959 | Tapered through-silicon via structure - An integrated circuit structure includes a substrate; a through-silicon via (TSV) in the substrate, the TSV being tapered; a hard mask region extending from a top surface of the substrate into the substrate, wherein the hard mask encircles a top portion of the TSV; dielectric layers over the substrate; and a metal post extending from a top surface of the dielectric layers to the TSV, wherein the metal post comprises same materials as the TSV. | 11-20-2008 |
20080296763 | Multi-Die Wafer Level Packaging - A semiconductor die package is provided. The semiconductor die package includes a plurality of dies arranged in a stacked configuration. Through-silicon vias are formed in the lower or intermediate dies to allow electrical connections to dies stacked above. The lower die is positioned face up and has redistribution lines electrically coupling underlying semiconductor components to the through-silicon vias. The dies stacked above the lower die may be oriented face up such that the contact pads are facing away from the lower die or flipped such that the contact pads are facing the lower die. The stacked dies may be electrically coupled to the redistribution lines via wire bonding or solder balls. Additionally, the lower die may have another set of redistribution lines on an opposing side from the stacked dies to reroute the vias to a different pin-out configuration. | 12-04-2008 |
20090051039 | THROUGH-SUBSTRATE VIA FOR SEMICONDUCTOR DEVICE - A semiconductor device including a substrate having a front surface and a back surface is provided. A plurality of interconnect layers are formed on the front surface and have a first surface opposite the front surface of the substrate. A tapered profile via extends from the first surface of the plurality of interconnect layers to the back surface of the substrate. In one embodiment, a insulating layer is formed on the substrate and includes an opening, and wherein the opening includes conductive material providing contact to the tapered profile via. | 02-26-2009 |
20090057823 | Semiconductor Structure with a Discontinuous Material Density for Reducing Eddy Currents - A semiconductor structure includes an inductor; and a semiconductor substrate underlying the inductor, having a discontinuous material density across a plane underneath and in parallel with the inductor, thereby reducing eddy currents induced by an electrical current flowing through the inductor. | 03-05-2009 |
20090155957 | Multi-Die Wafer Level Packaging - A semiconductor die package is provided. The semiconductor die package includes a plurality of dies arranged in a stacked configuration. Through-silicon vias are formed in the lower or intermediate dies to allow electrical connections to dies stacked above. The lower die is positioned face up and has redistribution lines electrically coupling underlying semiconductor components to the through-silicon vias. The dies stacked above the lower die may be oriented face up such that the contact pads are facing away from the lower die or flipped such that the contact pads are facing the lower die. The stacked dies may be electrically coupled to the redistribution lines via wire bonding or solder balls. Additionally, the lower die may have another set of redistribution lines on an opposing side from the stacked dies to reroute the vias to a different pin-out configuration. | 06-18-2009 |
20090269905 | Tapered Through-Silicon Via Structure - An integrated circuit structure includes a substrate; a through-silicon via (TSV) in the substrate, the TSV being tapered; a hard mask region extending from a top surface of the substrate into the substrate, wherein the hard mask encircles a top portion of the TSV; dielectric layers over the substrate; and a metal post extending from a top surface of the dielectric layers to the TSV, wherein the metal post comprises same materials as the TSV. | 10-29-2009 |
20100084747 | Zigzag Pattern for TSV Copper Adhesion - A system and method for forming a TSV contact is presented. A preferred embodiment includes a TSV in contact with a portion of the uppermost metal layer of a semiconductor die. The interface between the TSV conductor and the contact pad is preferably characterized by a non-planar zigzag pattern that forms a grid pattern of contacts. Alternatively, the contacts may form a plurality of metal lines that make contact with the contact pad. | 04-08-2010 |
20100090304 | BONDING PROCESS FOR CMOS IMAGE SENSOR - The present disclosure provides a method of making an integrated circuit (IC). The method includes forming an electric device on a front side of a substrate; forming a top metal pad on the front side of the substrate, the top metal pad being coupled to the electric device; forming a passivation layer on the front side of the substrate, the top metal pad being embedded in the passivation layer; forming an opening in the passivation layer, exposing the top metal pad; forming a deep trench in the substrate; filling a conductive material in the deep trench and the opening, resulting in a though-wafer via (TWV) feature in the deep trench and a pad-TWV feature in the opening, where the top metal pad being connected to the TWV feature through the pad-TWV feature; and applying a polishing process to remove excessive conductive material, forming a substantially planar surface. | 04-15-2010 |
20100171223 | Through-Silicon Via With Scalloped Sidewalls - A semiconductor device having one or more through-silicon vias (TSVs) is provided. The TSVs are formed such that sidewalls of the TSVs have a scalloped surface. In an embodiment, the sidewalls of the TSVs are sloped wherein a top and bottom of the TSVs have different dimensions. The TSVs may have a V-shape wherein the TSVs have a wider dimension on a circuit side of the substrate, or an inverted V-shape wherein the TSVs have a wider dimension on a backside of the substrate. The scalloped surfaces of the sidewalls and/or sloped sidewalls allow the TSVs to be more easily filled with a conductive material such as copper. | 07-08-2010 |
20110006416 | STRUCTURE AND METHOD FOR FORMING PILLAR BUMP STRUCTURE HAVING SIDEWALL PROTECTION - A method for forming a metal pillar bump structure is provided. In one embodiment, a passivation layer is formed over a semiconductor substrate and a conductive layer is formed over the passivation layer. A patterned and etched photoresist layer is provided above the conductive layer, the photoresist layer defining at least one opening therein. A metal layer is deposited in the at least one opening. Portions of the photoresist layer are etched along one or more interfaces between the photoresist layer and the metal layer to form cavities. A solder material is deposited in the at least one opening, the solder material filling the cavities and a portion of the opening above the metal layer. The remaining photoresist layer and the conductive layer not formed under the copper layer are removed. The solder material is then reflown to encapsulate the metal layer. | 01-13-2011 |
20110034027 | Structure and Process for the Formation of TSVs - An integrated circuit structure includes a semiconductor substrate; an interconnect structure over the semiconductor substrate, wherein the interconnect structure comprises a top inter-metal dielectric (IMD); an opening penetrating the interconnect structure into the semiconductor substrate; a conductor in the opening; and an isolation layer having a vertical portion and a horizontal portion physically connected to each other. The vertical portion is on sidewalls of the opening. The horizontal portion is directly over the interconnect structure. The integrated circuit structure is free from passivation layers vertically between the top IMD and the horizontal portion of the isolation layer. | 02-10-2011 |
20110068465 | STRONG INTERCONNECTION POST GEOMETRY - A flip-chip packaging assembly and integrated circuit device are disclosed. An exemplary flip-chip packaging assembly includes a first substrate; a second substrate; and joint structures disposed between the first substrate and the second substrate. Each joint structure comprises an interconnect post between the first substrate and the second substrate and a joint solder between the interconnect post and the second substrate, wherein the interconnect post exhibits a width and a first height. A pitch defines a distance between each joint structure. The first height is less than half the pitch. | 03-24-2011 |
20110095436 | THROUGH SILICON VIA WITH DUMMY STRUCTURE AND METHOD FOR FORMING THE SAME - A through silicon via structure includes a top pad and a vertical conductive post that is connected to the top pad. The top pad covers a wider area than the cross section of the vertical conductive post. An interconnect pad is formed at least partially below the top pad. An under layer is also formed at least partially below the top pad. At least one dummy structure connects the top pad and the under layer to fasten the top pad and the interconnect pad. | 04-28-2011 |
20110101519 | Robust Joint Structure for Flip-Chip Bonding - An integrated circuit structure includes a first work piece and a second work piece. The first work piece includes a copper bump at a main surface of the first work piece and having a first dimension; and a nickel-containing barrier layer over and adjoining the copper bump. The second work piece is bonded to the first work piece and includes a bond pad at a main surface of the second work piece; and a solder mask at the main surface of the second work piece and having a solder resist opening with a second dimension exposing a portion of the bond pad. A ratio of the first dimension to the second dimension is greater than about 1. Further, a solder region electrically connects the copper bump to the bond pad, with a vertical distance between the bond pad and the copper bump being greater than about 30 μm. | 05-05-2011 |
20110175220 | SEMICONDUCTOR DEVICE HAVING CONDUCTIVE PADS AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device includes at least two conductive pads, one of the conductive pads being formed above another of the at least two conductive pads, and a redistribution layer extending from at least one of the conductive pads. The semiconductor device also includes a bump structure formed over the conductive pads and electrically coupled to the conductive pads. | 07-21-2011 |
20110186986 | T-Shaped Post for Semiconductor Devices - A T-shaped post for semiconductor devices is provided. The T-shaped post has an under-bump metallization (UBM) section and a pillar section extending from the UBM section. The UBM section and the pillar section may be formed of a same material or different materials. In an embodiment, a substrate, such as a die, wafer, printed circuit board, packaging substrate, or the like, having T-shaped posts is attached to a contact of another substrate, such as a die, wafer, printed circuit board, packaging substrate, or the like. The T-shaped posts may have a solder material pre-formed on the pillar section such that the pillar section is exposed or such that the pillar section is covered by the solder material. In another embodiment, the T-shaped posts may be formed on one substrate and the solder material formed on the other substrate. | 08-04-2011 |
20110186988 | Multi-Direction Design for Bump Pad Structures - An integrated circuit structure includes a semiconductor chip having a first region and a second region; a dielectric layer formed on the first region and the second region of the semiconductor chip; a first elongated under-bump metallization (UBM) connector formed in the dielectric layer and on the first region of the semiconductor chip and having a first longer axis extending in a first direction; and a second elongated UBM connector formed in the dielectric layer on the second region of the semiconductor chip and having a second longer axis extending in a second direction. The first direction is different from the second direction. | 08-04-2011 |
20110193227 | Methods and Apparatus for Robust Flip Chip Interconnections - Apparatus and methods for providing a robust solder connection in a flip chip arrangement using lead free solder are disclosed. A copper column extends from an input/output terminal of an integrated circuit. A cap layer of a material comprising one of nickel, nickel alloys, palladium, platinum, cobalt, silver, gold, and alloys of these is formed on the exterior surface of the copper column. A lead free solder connector is disposed on the cap layer. A substrate having a metal finish solder pad is aligned with the solder connector. A thermal reflow is performed. The metal finish may be of nickel, nickel alloy and nickel based materials. Following a thermal reflow, the solder connection formed between the copper terminal column and the metal finish solder pad is less than 0.5 wt. %. | 08-11-2011 |
20110193232 | CONDUCTIVE PILLAR STRUCTURE FOR SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURE - A conductive pillar structure for a die includes a passivation layer having a metal contact opening over a substrate. A bond pad has a first portion inside the metal contact opening and a second portion overlying the passivation layer. The second portion of the bond pad has a first width. A buffer layer over the bond pad has a pillar contact opening with a second width to expose a portion of the bond pad. A conductive pillar has a first portion inside the pillar contact opening and a second portion over the buffer layer. The second portion of the conductive pillar has a third width. A ratio of the second width to the first width is between about 0.35 and about 0.65. A ratio of the second width to the third width is between about 0.35 and about 0.65. | 08-11-2011 |
20110217841 | METHOD OF FORMING THROUGH SILICON VIA WITH DUMMY STRUCTURE - A method of forming a through silicon via (TSV) structure includes forming an interconnect pad over a substrate. An under layer is formed over the interconnect pad. A vertical conductive post is formed at least partially through the substrate. At least one dummy structure is formed at least partially through the under layer. A top pad is formed over the dummy structure and the vertical conductive post. The top pad covers a wider area than a cross section of the vertical conductive post. The interconnect pad is electrically connected to the top pad. The dummy structure connects the top pad and the under layer thereby fastening the top pad and the interconnect pad. | 09-08-2011 |
20110227216 | Under-Bump Metallization Structure for Semiconductor Devices - An under-bump metallization (UBM) structure for a semiconductor device is provided. A passivation layer is formed over a contact pad such that at least a portion of the contact pad is exposed. A protective layer, such as a polyimide layer, may be formed over the passivation layer. The UBM structure, such as a conductive pillar, is formed over the underlying contact pad such that the underlying contact pad extends laterally past the UBM structure by a distance large enough to prevent or reduce cracking of the passivation layer and or protective layer. | 09-22-2011 |
20110241202 | Dummy Metal Design for Packaging Structures - An integrated circuit structure includes a semiconductor chip, a metal pad at a major surface of the semiconductor chip, and an under-bump metallurgy (UBM) over and contacting the metal pad. A metal bump is formed over and electrically connected to the UBM. A dummy pattern is formed at a same level, and formed of a same metallic material, as the metal pad. | 10-06-2011 |
20110263120 | THROUGH-SUBSTRATE VIA FOR SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device including providing a substrate having a front surface and a back surface. A masking element is formed on the front surface of the substrate. The masking element includes a first layer having a first opening and a second layer having a second opening of a greater width than the first opening. The second opening is a tapered opening. The method further includes etching a tapered profile via extending from the front surface to the back surface of the substrate using the formed masking element. | 10-27-2011 |
20110285013 | Controlling Solder Bump Profiles by Increasing Heights of Solder Resists - A device includes a first work piece bonded to a second work piece. The first work piece includes a solder resist at a surface of the first work piece, wherein the solder resist includes a solder resist opening, and a bond pad in the solder resist opening. The second work piece includes a non-reflowable metal bump at a surface of the second work piece. A solder bump bonds the non-reflowable metal bump to the bond pad, with at least a portion of the solder bump located in the solder resist opening and adjoining the non-reflowable metal bump and the bond pad. A thickness of the solder resist is greater than about 50 percent a height of the solder bump, wherein the height equals a distance between the non-reflowable metal bump and the bond pad. | 11-24-2011 |
20110291262 | Strength of Micro-Bump Joints - A device includes a work piece including a metal bump; and a dielectric layer having a portion directly over the metal bump. The metal bump and a surface of the portion of the dielectric layer form an interface. A metal finish is formed over and contacting the metal bump. The metal finish extends from over the dielectric layer to below the interface. | 12-01-2011 |
20120001334 | Structure and Process for the Formation of TSVs - An integrated circuit structure includes a semiconductor substrate; an interconnect structure over the semiconductor substrate, wherein the interconnect structure comprises a top inter-metal dielectric (IMD); an opening penetrating the interconnect structure into the semiconductor substrate; a conductor in the opening; and an isolation layer having a vertical portion and a horizontal portion physically connected to each other. The vertical portion is on sidewalls of the opening. The horizontal portion is directly over the interconnect structure. The integrated circuit structure is free from passivation layers vertically between the top IMD and the horizontal portion of the isolation layer. | 01-05-2012 |
20120012985 | Substrate Stand-Offs for Semiconductor Devices - Substrate stand-offs for use with semiconductor devices are provided. Active pillars and dummy pillars are formed on a first substrate such that the dummy pillars may have a height greater than a height of the active pillars. The dummy pillars act as stand-offs when joining the first substrate to a second substrate, thereby creating greater uniformity. In an embodiment, the dummy pillars may be formed simultaneously as the active pillars by forming a patterned mask having openings with a smaller width for the dummy pillars than for the active pillars. When an electro-plating process of the like is used to form the dummy and active pillars, the smaller width of the dummy pillar openings in the patterned mask causes the dummy pillars to have a greater height than the active pillars. | 01-19-2012 |
20120040524 | PROCESS FOR MAKING CONDUCTIVE POST WITH FOOTING PROFILE - A process for making a copper post with footing profile employs dual photoresist films of different photosensitivities and thicknesses on an under-bump-metallurgy (UBM) layer. After an exposure lithography process, a first opening with a substantially vertical sidewall is formed in a first photoresist film, and a second opening with a sloped sidewall is formed in a second photoresist film. The second opening has a top diameter and a bottom diameter greater than the top diameter, and the bottom diameter is greater than the diameter of the first opening. A conductive layer is then formed in the first opening and the second opening followed by removing the dual photoresist films. | 02-16-2012 |
20120104561 | Structures for Preventing Cross-talk Between Through-Silicon Vias and Integrated Circuits - A semiconductor chip includes a through-silicon via (TSV), a device region, and a cross-talk prevention ring encircling one of the device region and the TSV. The TSV is isolated from substantially all device regions comprising active devices by the cross-talk prevention ring. | 05-03-2012 |
20120178252 | Dummy Metal Design for Packaging Structures - A method of forming an integrated circuit structure is provided. The method includes forming a metal pad at a major surface of a semiconductor chip, forming an under-bump metallurgy (UBM) over the metal pad such that the UBM and the metal pad are in contact, forming a dummy pattern at a same level as the metal pad, the dummy pattern formed of a same metallic material as the metal pad and electrically disconnected from the metal pad, and forming a metal bump over the UBM such that the metal bump is electrically connected to the UBM and no metal bump in the semiconductor chip is formed over the dummy pattern. | 07-12-2012 |
20120270369 | Methods for Lead Free Solder Interconnections for Integrated Circuits - Methods for forming lead free solder interconnections for integrated circuits. A copper column extends from an input/output terminal of an integrated circuit. A cap layer of material is formed on the input/output terminal of the integrated circuit. A lead free solder connector is formed on the cap layer. A substrate having a metal finish solder pad is aligned with the solder connector. An intermetallic compound is formed at the interface between the cap layer and the lead free solder connector. A solder connection is formed between input/output terminal of the integrated circuit and the metal finish pad that is less than 0.5 weight percent copper, and the intermetallic compound is substantially free of copper. | 10-25-2012 |
20130026622 | BUMP STRUCTURES IN SEMICONDUCTOR DEVICE AND PACKAGING ASSEMBLY - A bump structure in a semiconductor device or a packing assembly includes an under-bump metallization (UBM) layer formed on a conductive pad of a semiconductor substrate. The UBM layer has a width greater than a width of the conductive pad. | 01-31-2013 |
20130056872 | Packaging and Function Tests for Package-on-Package and System-in-Package Structures - A method includes placing a plurality of bottom units onto a jig, wherein the plurality of bottom units is not sawed apart and forms an integrated component. Each of the plurality of bottom units includes a package substrate and a die bonded to the package substrate. A plurality of upper component stacks is placed onto the plurality of bottom units, wherein solder balls are located between the plurality of upper component and the plurality of bottom units. A reflow is performed to join the plurality of upper component stacks with respective ones of the plurality of bottom units through the solder balls. | 03-07-2013 |
20130062755 | ELONGATED BUMP STRUCTURE IN SEMICONDUCTOR DEVICE - A device includes a chip attached to a substrate. The chip includes a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar. The substrate includes a conductive trace and a mask layer overlying the conductive trace, wherein the mask layer has an opening exposing a portion of the conductive trace. An interconnection is formed between the conductive pillar and the exposed portion of the conductive trace. The opening has a first dimension (d | 03-14-2013 |
20130075872 | Metal Pad Structures in Dies - A die includes a substrate, a metal pad over the substrate, and a passivation layer that has a portion over the metal pad. A dummy pattern is disposed adjacent to the metal pad. The dummy pattern is level with, and is formed of a same material as, the metal pad. The dummy pattern forms at least a partial ring surrounding at least a third of the metal pad. | 03-28-2013 |
20130093075 | Semiconductor Device Package and Method - An embodiment is a structure. The structure comprises a substrate, a chip, and a reinforcement component. The substrate has a first surface, and the first surface comprises depressions. The chip is over and attached to the first surface of the substrate. The reinforcement component is over a first area of the first surface of the substrate. The first area is not under the chip. The reinforcement component has a portion disposed in at least some of the depressions in the first area. | 04-18-2013 |
20130093079 | Connector Structures of Integrated Circuits - A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad. | 04-18-2013 |
20130119539 | Package Structures and Methods for Forming the Same - A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A solder region is disposed in the polymer region and electrically coupled to the redistribution line. The solder region includes a second flat top surface not higher than the first flat top surface. | 05-16-2013 |
20130134563 | Electrical Connection Structure - A structure comprises a top metal connector formed underneath a bond pad. The bond pad is enclosed by a first passivation layer and a second passivation layer. A polymer layer is further formed on the second passivation layer. The dimension of an opening in the first passivation layer is less than the dimension of the top metal connector. The dimension of the top metal connector is less than the dimensions of an opening in the second passivation layer and an opening in the polymer layer. | 05-30-2013 |
20130249091 | Multi-Direction Design for Bump Pad Structures - An integrated circuit structure includes a semiconductor chip having a first region and a second region; a dielectric layer formed on the first region and the second region of the semiconductor chip; a first elongated under-bump metallization (UBM) connector formed in the dielectric layer and on the first region of the semiconductor chip and having a first longer axis extending in a first direction; and a second elongated UBM connector formed in the dielectric layer on the second region of the semiconductor chip and having a second longer axis extending in a second direction. The first direction is different from the second direction. | 09-26-2013 |
20130288473 | Electrical Connection Structure - A structure comprises a top metal connector formed underneath a bond pad. The bond pad is enclosed by a first passivation layer and a second passivation layer. A polymer layer is further formed on the second passivation layer. The dimension of an opening in the first passivation layer is less than the dimension of the top metal connector. The dimension of the top metal connector is less than the dimensions of an opening in the second passivation layer and an opening in the polymer layer. | 10-31-2013 |
20130320524 | Design Scheme for Connector Site Spacing and Resulting Structures - A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 μm. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 μm. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 μm. | 12-05-2013 |
20140035148 | Bump on Pad (BOP) Bonding structure - The embodiments described above provide enlarged overlapping surface areas of bonding structures between a package and a bonding substrate. By using elongated bonding structures on either the package and/or the bonding substrate and by orienting such bonding structures, the bonding structures are designed to withstand bonding stress caused by thermal cycling to reduce cold joints. | 02-06-2014 |
20140048929 | Bonded Structures for Package and Substrate - The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance. | 02-20-2014 |
20140051244 | METHOD OF FORMING AN INTEGRATED CIRCUIT DEVICE - A method of forming an integrated circuit device includes forming an under-bump metallurgy (UBM) layer overlying a semiconductor substrate. Next, a first photoresist film is formed on the UBM layer where the first photoresist film has a first photosensitivity and a first thickness. Additionally, the method includes forming a second photoresist film on the first photoresist film. Next, the method includes performing an exposure process on the second photoresist film and the first photoresist film. The method further includes removing an exposed portion of the second photoresist film to form a first opening. The method further also includes removing an exposed portion of the first photoresist film to expose a portion of the UBM layer. Furthermore, the method includes forming a copper layer in the first opening. The method also includes removing the second photoresist film and the first photoresist film where the copper layer forms a copper post. | 02-20-2014 |
20140070402 | Stress Reduction Apparatus - A structure comprises a plurality of connectors formed on a top surface of a first semiconductor die, a second semiconductor die formed on the first semiconductor die and coupled to the first semiconductor die through the plurality of connectors and a first dummy conductive plane formed between an edge of the first semiconductor die and the plurality of connectors, wherein an edge of the first dummy conductive plane and a first distance to neutral point (DNP) direction form a first angle, and wherein the first angle is less than or equal to 45 degrees. | 03-13-2014 |
20140124947 | Methods and Apparatus for Flip Chip Substrate with Guard Rings Outside of a Die Attach Region - Methods and apparatus for flip chip substrates with guard rings. An embodiment comprises a substrate core with a die attach region for attaching an integrated circuit die; at least one dielectric layer overlying a die side surface of the substrate core; and at least one guard ring formed adjacent a corner of the substrate core, the at least one guard ring comprising: a first trace overlying the dielectric layer having rectangular portions extending in two directions from the corner of the substrate core and in parallel to the edges of the substrate core; a second trace underlying the dielectric layer; and at least one via extending through the dielectric layer and coupling the first and second traces; wherein the first trace, the at least one via, and the second trace form a vertical via stack. Methods for forming the flip chip substrates with the guard rings are disclosed. | 05-08-2014 |
20140131862 | SEMICONDUCTOR DEVICE HAVING CONDUCTIVE PADS AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, a plurality of conductive pads formed in consecutive conductive layers, and a bump structure. The plurality of conductive pads is aligned and arranged one above another over the substrate. The plurality of conductive pads comprises a first conductive pad and a second conductive pad. The first conductive pad is above the second conductive pad. A redistribution layer extends the second conductive pad. The first conductive pad is not extended by a redistribution layer. The bump structure is formed directly on the first conductive pad and electrically coupled to the plurality of conductive pads. | 05-15-2014 |
20140191390 | Metal Routing Architecture for Integrated Circuits - A device includes a substrate, a metal pad over the substrate, and a metal trace electrically disconnected from the metal pad. The metal pad and the metal trace are level with each other. A passivation layer includes a portion overlapping an edge portion of the metal pad. A metal pillar is overlying the metal pad, and is electrically connected to the metal pad. The metal trace has a portion overlapped by the metal pillar. | 07-10-2014 |
20140220776 | Multi-Direction Design for Bump Pad Structures - An integrated circuit structure includes a semiconductor chip having a first region and a second region; a dielectric layer formed on the first region and the second region of the semiconductor chip; a first elongated under-bump metallization (UBM) connector formed in the dielectric layer and on the first region of the semiconductor chip and having a first longer axis extending in a first direction; and a second elongated UBM connector formed in the dielectric layer on the second region of the semiconductor chip and having a second longer axis extending in a second direction. The first direction is different from the second direction. | 08-07-2014 |
20140231987 | Connector Structures of Integrated Circuits - A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad. | 08-21-2014 |
20140231994 | APPARATUS FOR LEAD FREE SOLDER INTERCONNECTIONS FOR INTEGRATED CIRCUITS - An apparatus includes an integrated circuit having at least one input/output terminal comprising copper formed thereon. A metal cap layer overlies an upper surface of the at least one input/output terminal. A substrate includes at least one conductive trace formed on a first surface, and a metal finish layer overlies a portion of the at least one conductive trace. A lead free solder connection is disposed between the metal cap layer and the metal finish layer, and a first intermetallic compound is disposed at an interface between the metal cap layer and the lead free solder connection. The lead free solder connection has a copper content of less than 0.5 wt. %, and the first intermetallic compound is substantially free of copper. | 08-21-2014 |
20140248722 | Packaging and Function Tests for Package-on-Package and System-in-Package Structures - A method includes placing a plurality of bottom units onto a jig, wherein the plurality of bottom units is not sawed apart and forms an integrated component. Each of the plurality of bottom units includes a package substrate and a die bonded to the package substrate. A plurality of upper component stacks is placed onto the plurality of bottom units, wherein solder balls are located between the plurality of upper component and the plurality of bottom units. A reflow is performed to join the plurality of upper component stacks with respective ones of the plurality of bottom units through the solder balls. | 09-04-2014 |
20140377946 | Bonded Structures for Package and Substrate - The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance. | 12-25-2014 |
20150037936 | Strength of Micro-Bump Joints - A device includes a work piece including a metal bump; and a dielectric layer having a portion directly over the metal bump. The metal bump and a surface of the portion of the dielectric layer form an interface. A metal finish is formed over and contacting the metal bump. The metal finish extends from over the dielectric layer to below the interface. | 02-05-2015 |