Patent application number | Description | Published |
20090011374 | METHOD AND MATERIAL FOR FORMING HIGH ETCH RESISTANT DOUBLE EXPOSURE PATTERNS - The present invention includes a lithography method comprising forming a first patterned resist layer including at least one opening therein over a substrate. A protective layer is formed on the first patterned resist layer and the substrate whereby a reaction occurs at the interface between the first patterned resist layer and the protective layer to form a reaction layer over the first patterned resist layer. The non-reacted protective layer is then removed. Thereafter, a second patterned resist layer is formed over the substrate, wherein at least one portion of the second patterned resist layer is disposed within the at least one opening of the first patterned resist layer. The substrate is thereafter etched using the first and second patterned resist layers as a mask. | 01-08-2009 |
20110006401 | METHOD AND SYSTEM FOR COMBINING PHOTOMASKS TO FORM SEMICONDUCTOR DEVICES - A photomask set includes at least two masks that combine to form a device pattern in a semiconductor device. Orthogonal corners may be produced in a semiconductor device pattern to include one edge defined by a first mask and an orthogonal edge defined by a second mask. The mask set may include a first mask with compensation features and a second mask with void areas overlaying the compensation features when the first and second masks are aligned with one another, such that the compensation features are removed when patterns are successfully formed from the first and second masks. The compensation features alleviate proximity effects during the formation of device features. | 01-13-2011 |
20110086504 | METHODS FOR FORMING INTEGRATED CIRCUITS - A method for forming an integrated circuit is provided. The method includes forming a gate dielectric structure over a substrate. A titanium-containing sacrificial layer is formed, contacting the gate dielectric structure. The whole titanium-containing sacrificial layer is substantially removed. | 04-14-2011 |
20110156166 | High Temperature Anneal for Aluminum Surface Protection - The present disclosure also provides another embodiment of a method for making metal gate stacks. The method includes forming a first dummy gate and a second dummy gate on a substrate; removing a polysilicon layer from the first dummy gate, resulting in a first gate trench; forming a first metal layer and a first aluminum layer in the first gate trench; applying a chemical mechanical polishing (CMP) process to the substrate; performing an annealing process to the first aluminum layer using a nitrogen and oxygen containing gas, forming an interfacial layer of aluminum, nitrogen and oxygen on the first aluminum layer; thereafter removing the polysilicon layer from the second dummy gate, resulting in a second gate trench; and forming a second metal layer and a second aluminum layer on the second metal layer in the second gate trench. | 06-30-2011 |
20110159410 | COST-EFFECTIVE METHOD FOR EXTREME ULTRAVIOLET (EUV) MASK PRODUCTION - The present disclosure provides for many different embodiments. An exemplary method can include providing a blank mask and a design layout to be patterned on the blank mask, the design layout including a critical area; inspecting the blank mask for defects and generating a defect distribution map associated with the blank mask; mapping the defect distribution map to the design layout; performing a mask making process; and performing a mask defect repair process based on the mapping. | 06-30-2011 |
20110195570 | INTEGRATION OF BOTTOM-UP METAL FILM DEPOSITION - The described embodiments of methods of bottom-up metal deposition to fill interconnect and replacement gate structures enable gap-filling of fine features with high aspect ratios without voids and provide metal films with good film quality. In-situ pretreatment of metal film(s) deposited by gas cluster ion beam (GCIB) allows removal of surface impurities and surface oxide to improve adhesion between an underlying layer with the deposited metal film(s). Metal films deposited by photo-induced chemical vapor deposition (PI-CVD) using high energy of low-frequency light source(s) at relatively low temperature exhibit liquid-like nature, which allows the metal films to fill fine feature from bottom up. The post deposition annealing of metal film(s) deposited by PI-CVD densifies the metal film(s) and removes residual gaseous species from the metal film(s). For advanced manufacturing, such bottom-up metal deposition methods address the challenges of gap-filling of fine features with high aspect ratios. | 08-11-2011 |
20120064715 | INTEGRATION OF BOTTOM-UP METAL FILM DEPOSITION - A method of depositing a metal film on a substrate with patterned features includes placing a substrate with patterned features into a photo-induced chemical vapor deposition (PI-CVD) process chamber. The method also includes depositing a metal film by PI-CVD to fill the patterned features from bottom up. | 03-15-2012 |
20130023094 | METHOD OF FABRICATING AN INTEGRATED CIRCUIT DEVICE - A method for fabricating an integrated device is disclosed. A protective layer is formed over a gate structure when forming epitaxial (epi) features adjacent to another gate structure uncovered by the protective layer. The protective layer is thereafter removed after forming the epitaxial (epi) features. The disclosed method provides an improved method for removing the protective layer without substantial defects resulting. In an embodiment, the improved formation method is achieved by providing a protector over an oxide-base material, and then removing the protective layer using a chemical comprising hydrofluoric acid. | 01-24-2013 |
20130157387 | Multi-zone EPD Detectors - The present disclosure relates to a semiconductor body etching apparatus having a multi-zone end point detection system. In some embodiments, the multi-zone end point detection system has a processing chamber that houses a workpiece that is etched according to an etching process. A plurality of end point detector (EPD) probes are located within the processing chamber. Respective EPD probes are located within different zones in the processing chamber, thereby enabling the detection of end point signals from multiple zones within the processing chamber. The detected end point signals are provided from the plurality of EPD probes to an advanced process control (APC) unit. The APC unit is configured to make a tuning knob adjustment to etching process parameters based upon the detected end point signals and to thereby account for etching non-uniformities. | 06-20-2013 |
20130160795 | Plasma Etcher Design with Effective No-Damage In-Situ Ash - In some embodiments, the present disclosure relates to a plasma etching system having direct and localized plasma sources in communication with a processing chamber. The direct plasma is operated to provide a direct plasma to the processing chamber for etching a semiconductor workpiece. The direct plasma has a high potential, formed by applying a large bias voltage to the workpiece. After etching is completed the bias voltage and direct plasma source are turned off. The localized plasma source is then operated to provide a low potential, localized plasma to a position within the processing chamber that is spatially separated from the workpiece. The spatial separation results in formation of a diffused plasma having a zero/low potential that is in contact with the workpiece. The zero/low potential of the diffused plasma allows for reactive ashing to be performed, while mitigating workpiece damage resulting from ion bombardment caused by positive plasma potentials. | 06-27-2013 |
20130171336 | WAFER PROCESSING METHOD AND SYSTEM USING MULTI-ZONE CHUCK - In a wafer processing method and a wafer processing system, a first property on a back side of a wafer is measured. The back side of the wafer is supported on a multi-zone chuck having a plurality of zones with controllable clamping forces. The wafer is secured to the multi-zone chuck by controlling the clamping forces in the corresponding zones in accordance with measured values of the first property in the zones. | 07-04-2013 |
20130189851 | CVD Conformal Vacuum/Pumping Guiding Design - The present disclosure relates to a guiding element for guiding gas flow within a chamber. The guiding element includes a structure, one or more inlets, an outlet, and a transportation region. The one or more inlets are formed on a first side of the structure. The inlets have inlet sizes selected according to a removal rate and to mitigate gas flow variations within the chamber. The outlet is on a second side of the structure, opposite the first side of the structure. The outlet has an outlet size selected according to the removal rate. The transportation region is within the structure and couples or connects the inlets to the outlet. | 07-25-2013 |
20130199926 | Novel Multi Coil Target Design - In some embodiments, the present disclosure relates to a plasma processing system configured to form a symmetric plasma distribution around a workpiece. In some embodiments, the plasma processing system comprises a plurality of coils symmetrically positioned around a processing chamber. When a current is provided to the coils, separate magnetic fields, which operate to ionize the target atoms, emanate from the separate coils. The separate magnetic fields operate upon ions within the coils to form a plasma on the interior of the coils. Furthermore, the separate magnetic fields are superimposed upon one another between coils to form a plasma on the exterior of the coils. Therefore, the disclosed plasma processing system can form a plasma that continuously extends along a perimeter of the workpiece with a high degree of uniformity (i.e., without dead spaces). | 08-08-2013 |
20130210173 | Multiple Zone Temperature Control for CMP - To provide improved planarization, techniques in accordance with this disclosure include a CMP station that includes a plurality of concentric temperature control elements arranged over a number of concentric to-be-polished wafer surfaces. During polishing, a wafer surface planarity sensor monitors relative heights of the concentric to-be-polished wafer surfaces, and adjusts the temperatures of the concentric temperature control elements to provide an extremely well planarized wafer surface. Other systems and methods are also disclosed. | 08-15-2013 |
20130217306 | CMP Groove Depth and Conditioning Disk Monitoring - Some embodiments relate to a chemical mechanical polishing (CMP) system. The CMP system includes a polishing pad having a polishing surface, and a wafer carrier to retain a wafer proximate to the polishing surface during polishing. A motor assembly rotates the polishing pad and concurrently rotates the wafer during polishing of the wafer. A conditioning disk has a conditioning surface that is in frictional engagement with the polishing surface during polishing. A torque measurement element measures a torque exerted by the motor assembly during polishing. A condition surface analyzer determines a surface condition of the conditioning surface or the polishing surface based on the measured torque. Other systems and methods are also disclosed. | 08-22-2013 |
20130226327 | NOVEL CLOSED LOOP CONTROL FOR RELIABILITY - The present disclosure relates to semiconductor tool monitoring system having multiple sensors configured to concurrently and independently monitor processing conditions of a semiconductor manufacturing tool. In some embodiments, the disclosed tool monitoring system comprises a first sensor system configured to monitor one or more processing conditions of a semiconductor manufacturing tool and to generate a first monitoring response based thereupon. A redundant, second sensor system is configured to concurrently monitor the one or more processing conditions of the manufacturing tool and to generate a second monitoring response based thereupon. A comparison element is configured to compare the first and second monitoring responses, and if the responses deviate from one another (e.g., have a deviation greater than a threshold value) to generate a warning signal. By comparing the first and second monitoring responses, errors in the sensor systems can be detected in real time, thereby preventing yield loss. | 08-29-2013 |
20130244552 | MANUFACTURE AND METHOD OF MAKING THE SAME - A manufacture includes a substrate, a reinforcement layer over the substrate, and abrasive particles over the substrate. The abrasive particles are partially buried in the reinforcement layer. Upper tips of the abrasive particles are substantially coplanar. | 09-19-2013 |
20130258339 | WAFER ALIGNMENT MARK SCHEME - A wafer alignment apparatus includes a light source, a light detection device, and a rotation device configured to rotate a wafer. The light source is configured to provide light directed to a backside of the wafer. The light detection device is configured to detect reflected light intensity from the backside of the wafer to find a position of at least one wafer alignment mark formed on the back side of the wafer. | 10-03-2013 |
20130264308 | PLASMA PROCESS, FILM DEPOSITION METHOD AND SYSTEM USING ROTARY CHUCK - A chuck and a wafer supported thereon are rotated during a plasma process or a film deposition process to reduce thickness non-uniformity of a film processed or deposited on the wafer. | 10-10-2013 |
20130270617 | INTEGRATION OF BOTTOM-UP METAL FILM DEPOSITION - A gate structure including a substrate and a gate dielectric layer formed over the substrate. The gate structure further includes a workfunction layer over the gate dielectric layer and spacers enclosing the gate dielectric layer and the workfunction layer. A top surface of a portion of the workfunction layer in contact with sidewalls of the spacer is a same distance from the gate dielectric layer as a top surface of a center portion of the work function layer. | 10-17-2013 |
20130285264 | WAFER ASSEMBLY WITH CARRIER WAFER - A wafer assembly includes a process wafer and a carrier wafer. Integrated circuits are formed on the process wafer. The carrier wafer is bonded to the process wafer. The carrier wafer has at least one alignment mark. | 10-31-2013 |
20130293857 | LITHOGRAPHY APPARATUS HAVING DUAL RETICLE EDGE MASKING ASSEMBLIES AND METHOD OF USE - A lithography apparatus includes at least two reticle edge masking assemblies (REMAs). The lithography apparatus further includes a light source configured to emit a light beam having a wavelength and a beam separating element configured to divide the light beam into more than one collimated light beam. Each REMA is positioned to receive one of the more than one collimating light beams and each REMA comprises a movable slit for passing the one collimated light beam therethrough. The lithography apparatus further includes at least one mask having a pattern, where the at least one mask is configured to receive light from at least one of the REMA and a projection lens configured to receive light from the at least one mask. A method of using a lithography apparatus is also discussed. | 11-07-2013 |
20130319612 | PLASMA CHAMBER HAVING AN UPPER ELECTRODE HAVING CONTROLLABLE VALVES AND A METHOD OF USING THE SAME - This description relates to a plasma treatment apparatus including a vapor chamber, a gas supply and an upper electrode assembly. The upper electrode assembly includes a gas distribution plate having a plurality of holes in a bottom surface thereof and an upper electrode having at least one gas nozzle and at least one controllable valve connected to the at least one gas nozzle. The plasma treatment apparatus further includes a controller configured to generate a control signal. The at least one controllable valve is configured to be adjusted based on the control signal. A control system and a method of controlling a controllable valve are also described. | 12-05-2013 |
20140100684 | 2D/3D Analysis for Abnormal Tools and Stages Diagnosis - A method for analyzing abnormalities in a semiconductor processing system provides performing an analysis of variance on a production history associated with each of a plurality of tools at each of a plurality of process steps for each of a plurality of processed wafers, and key process steps are identified. A regression analysis on a plurality of measurements of the plurality of wafers at each process step is performed and key measurement parameters are identified. An analysis of covariance on the key measurement parameters and key process steps, and the key process steps are ranked based on an f-ratio, therein ranking an abnormality of the key process steps. Further, the plurality of tools associated with each of the key process steps are ranked based on an orthogonal t-ratio associated with an analysis of covariance, therein ranking an abnormality each tool associated with the key process steps. | 04-10-2014 |
20140202383 | WAFER PROCESSING SYSTEM USING MULTI-ZONE CHUCK - A wafer processing system includes at least one metrology chamber, a process chamber, and a controller. The at least one metrology chamber is configured to measure a thickness of a first layer on a back side of a wafer. The process chamber is configured to perform a treatment on a front side of the wafer. The front side is opposite the back side. The process chamber includes therein a multi-zone chuck. The multi-zone chuck is configured to support the back side of the wafer. The multi-zone chuck has a plurality of zones with controllable clamping forces for securing the wafer to the multi-zone chuck. The controller is coupled to the metrology chamber and the multi-zone chuck. The controller is configured to control the clamping forces in the corresponding zones in accordance with measured values of the thickness of the first layer in the corresponding zones. | 07-24-2014 |
20150076371 | LITHO CLUSTER AND MODULIZATION TO ENHANCE PRODUCTIVITY - The present disclosure relates to a lithographic tool arrangement for semiconductor workpiece processing. The lithographic tool arrangement groups lithographic tools into clusters, and selectively transfers a semiconductor workpiece between a plurality of lithographic tools of a first type in a first cluster to a plurality of lithographic tools of a second type in a second cluster. The selective transfer is achieved though a transfer assembly, which is coupled to a defect scan tool that identifies defects generated in the lithographic tool of the first type. The disclosed lithographic tool arrangement also utilizes shared structural elements such as a housing assembly, and shared functional elements such as gases and chemicals. The lithographic tool arrangement may consist of baking, coating, exposure, and development units configured to provide a modularization of these various components in order to optimize throughput and efficiency for a given lithographic fabrication process. | 03-19-2015 |
Patent application number | Description | Published |
20080265322 | METAL OXIDE SEMICONDUCTOR TRANSISTOR WITH Y SHAPE METAL GATE AND FABRICATING METHOD THEREOF - A method of manufacturing a metal oxide semiconductor transistor having a metal gate is provided. The method firstly includes a step of providing a substrate. A dummy gate is formed on the substrate, a spacer is formed around the dummy gate, and doped regions are formed in the substrate outside of the dummy gate. A bevel edge is formed on the spacer, and a trench is formed in the inner sidewall of the spacer. A barrier layer, and a metal gate are formed in the trench and on the bevel edge, and the barrier layer will not form poor step coverage. | 10-30-2008 |
20090042053 | DIELECTRIC LAYER STRUCTURE AND MANUFACTURING METHOD THEREOF - A method for fabricating a dielectric layer structure includes providing a substrate, forming at least a low-k dielectric layer on the substrate, forming a single tensile layer on the low-k dielectric layer, and performing a moisture preventing treatment on the single tensile film. The single tensile layer possesses a stress comparative to a stress of the low-k dielectric layer and a hydrophobic characteristic that prevents itself from absorbing moisture. | 02-12-2009 |
20090166766 | METAL OXIDE SEMICONDUCTOR TRANSISTOR WITH Y SHAPE METAL GATE - A metal oxide semiconductor (MOS) transistor with a Y structure metal gate is provided. The MOS transistor includes a substrate, a Y structure metal gate positioned on the substrate, two doping regions disposed in the substrate on two sides of the Y structure metal structure, a spacer, an insulating layer positioned outside the spacer, a dielectric layer positioned outside the insulating layer and a bevel edge covering the spacer. The spacer has a vertical sidewall, and the vertical sidewall surrounds a recess. A part of the Y structure metal gate is disposed in the recess, and a part of the Y structure metal gate is positioned on the bevel edge. | 07-02-2009 |
20110062562 | DIELECTRIC LAYER STRUCTURE - A dielectric layer structure includes an interlayer dielectric (ILD) layer covering at least a metal interconnect structure and a single tensile hydrophobic film. The ILD layer further includes a low-k dielectric layer, and the single tensile hydrophobic film is positioned on the low-k dielectric layer for counteracting at least a part of a stress of the low-k dielectric layer. | 03-17-2011 |
20110065285 | DIELECTRIC LAYER STRUCTURE AND MANUFACTURING METHOD THEREOF - A method for fabricating a dielectric layer structure includes providing a substrate, blanketly forming a low-k dielectric layer of an interlayer dielectric (ILD) layer, the low-k dielectric layer covering at least a first metal interconnect structure on the substrate, blanketly forming a single tensile film of the ILD layer having a thickness of 200-1500 angstroms on the low-k dielectric layer, and performing a moisture preventing treatment on the single tensile film. The single tensile layer possesses a stress comparative to a stress of the low-k dielectric layer and a hydrophobic characteristic that prevents itself from absorbing moisture. | 03-17-2011 |
20110204491 | DIELECTRIC LAYER STRUCTURE - A dielectric layer structure includes an interlayer dielectric (ILD) layer covering at least a metal interconnect structure and a single tensile film. The ILD layer further includes a low-k dielectric layer, and the single tensile film is positioned on the low-k dielectric layer for counteracting at least a part of a stress of the low-k dielectric layer. | 08-25-2011 |
Patent application number | Description | Published |
20110193144 | SEMICONDUCTOR DEVICE HAVING ELEVATED STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate; a gate stack overlying the substrate, a spacer formed on sidewalls of the gate stack, and a protection layer overlying the gate stack for filling at least a portion of a space surrounded by the spacer and the top surface of the gate stack. A top surface of the spacer is higher than a top surface of the gate stack. | 08-11-2011 |
20110294287 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING DUAL FULLY-SILICIDED GATE - A method of manufacturing the semiconductor device having a dual fully-silicided gate includes the following steps. A substrate having a first transistor and a second transistor formed thereon is provided, wherein the first transistor includes a first gate and a first source/drain and the second transistor includes a second gate and a second source/drain. The gate height of the first gate is different from that of the second gate. A first silicidation process is performed to respectively transform the first gate and the second gate into a first silicided gate and a second silicided gate simultaneously, wherein the material of the first silicided gate is different from that of the second silicided gate. | 12-01-2011 |
20120138897 | SOURCE/DRAIN STRESSOR HAVING ENHANCED CARRIER MOBILITY AND METHOD FOR MANUFACTURING SAME - Various source/drain stressors that can enhance carrier mobility, and methods for manufacturing the same, are disclosed. An exemplary source/drain stressor includes a seed layer of a first material disposed over a substrate of a second material, the first material being different than the second material; a relaxed epitaxial layer disposed over the seed layer; and an epitaxial layer disposed over the relaxed epitaxial layer. | 06-07-2012 |
20130252175 | Litho Cluster and Modulization to Enhance Productivity - The present disclosure relates to a lithographic tool arrangement for semiconductor workpiece processing. The lithographic tool arrangement groups lithographic tools into clusters, and selectively transfers a semiconductor workpiece between a plurality of lithographic tools of a first type in a first cluster to a plurality of lithographic tools of a second type in a second cluster. The selective transfer is achieved though a transfer assembly, which is coupled to a defect scan tool that identifies defects generated in the lithographic tool of the first type. The disclosed lithographic tool arrangement also utilizes shared structural elements such as a housing assembly, and shared functional elements such as gases and chemicals. The lithographic tool arrangement may consist of baking, coating, exposure, and development units configured to provide a modularization of these various components in order to optimize throughput and efficiency for a given lithographic fabrication process. | 09-26-2013 |
20140113424 | Source/Drain Stressor Having Enhanced Carrier Mobility and Method for Manufacturing Same - Various source/drain stressors that can enhance carrier mobility, and methods for manufacturing the same, are disclosed. An exemplary source/drain stressor includes a seed layer of a first material disposed over a substrate of a second material, the first material being different than the second material; a relaxed epitaxial layer disposed over the seed layer; and an epitaxial layer disposed over the relaxed epitaxial layer. | 04-24-2014 |
20140213048 | Method of Making a FinFET Device - A FinFET device is fabricated by first receiving a FinFET precursor. The FinFET precursor includes a substrate, fins on the substrate, isolation regions on sides of the fins and dummy gate stacks on the substrate including wrapping a portion of the fin, which is referred to as a gate channel region. The dummy gate stacks is removed to form a gate trench and a gate dielectric layer is deposited in the gate trench. A metal stressor layer (MSL) is conformably deposited on the gate dielectric layer. A capping layer is deposited on the MSL. A thermal treatment is applied to the MSL to achieve a volume expansion. Then the capping layer is removed and a metal gate (MG) is formed on the MSL. | 07-31-2014 |