Patent application number | Description | Published |
20120309194 | METHOD FOR PROVIDING HIGH ETCH RATE - A method for etching features into an etch layer in a plasma processing chamber, comprising a plurality of cycles is provided. Each cycle comprises a deposition phase and an etching phase. The deposition phase comprises providing a flow of deposition gas, forming a plasma from the deposition gas in the plasma processing chamber, providing a first bias during the deposition phase to provide an anisotropic deposition, and stopping the flow of the deposition gas into the plasma processing chamber. The etching phase, comprises providing a flow of an etch gas, forming a plasma from the etch gas in the plasma processing chamber, providing a second bias during the etch phase, wherein the first bias is greater than the second bias, and stopping the flow of the etch gas into the plasma processing chamber. | 12-06-2012 |
20120309198 | USE OF SPECTRUM TO SYNCHRONIZE RF SWITCHING WITH GAS SWITCHING DURING ETCH - A method for etching features into an etch layer in a plasma processing chamber is provided. An optically timed deposition phase is provided comprising providing a flow of deposition phase gas, detecting the presence of deposition gas within the plasma processing chamber, providing RF energy for forming a plasma from the deposition phase gas in the plasma processing chamber, and stopping the flow of the deposition gas into the plasma processing chamber. An optically timed etching phase is provided, comprising providing a flow of an etch gas, detecting the presence of the etch gas within the plasma processing chamber, providing RF energy for forming a plasma from the etch gas in the plasma processing chamber, and stopping the flow of the etch gas into the plasma processing chamber. | 12-06-2012 |
20130115776 | PRESSURE CONTROL VALVE ASSEMBLY OF PLASMA PROCESSING CHAMBER AND RAPID ALTERNATING PROCESS - A pressure control valve assembly of a plasma processing chamber in which semiconductor substrates are processed includes a housing having an inlet, an outlet and a conduit extending between the inlet and the outlet, the inlet adapted to be connected to an interior of the plasma processing chamber and the outlet adapted to be connected to a vacuum pump which maintains the plasma processing chamber at desired pressure set points during rapid alternating phases of processing a semiconductor substrate in the chamber. A fixed slotted valve plate having a first set of parallel slots therein is fixed in the conduit such that gasses withdrawn from the chamber into the conduit pass through the first set of parallel slots. A movable slotted valve plate having a second set of parallel slots therein is movable with respect to the fixed slotted valve plate so as to adjust pressure in the chamber. | 05-09-2013 |
20130203256 | CONTROLLED GAS MIXING FOR SMOOTH SIDEWALL RAPID ALTERNATING ETCH PROCESS - A method for etching features in a silicon layer disposed below a mask in a plasma processing chamber a plurality of cycles is provided. A deposition phase forming a deposition on the silicon layer in the plasma processing chamber is provided comprising providing a deposition gas into the plasma processing chamber wherein the deposition gas comprises a halogen containing etchant component and a fluorocarbon deposition component, forming the deposition gas into a plasma, which provides a net deposition on the silicon layer, and stopping the flow of the deposition gas. A silicon etch phase is provided, comprising providing a silicon etch gas into the plasma processing chamber that is different than the deposition gas, forming the silicon etch gas into a plasma to etch the silicon layer, and stopping the flow of the silicon etch gas. | 08-08-2013 |
20130237062 | METHOD FOR ACHIEVING SMOOTH SIDE WALLS AFTER BOSCH ETCH PROCESS - A method is provided for etching silicon in a plasma processing chamber, having an operating pressure and an operating bias. The method includes: performing a first vertical etch in the silicon to create a hole having a first depth and a sidewall; performing a deposition of a protective layer on the sidewall; performing a second vertical etch to deepen the hole to a second depth and to create a second sidewall, the second sidewall including a first trough, a second trough and a peak, the first trough corresponding to the first sidewall, the second trough corresponding to the second sidewall, the peak being disposed between the first trough and the second trough; and performing a third etch to reduce the peak. | 09-12-2013 |
20150364337 | PATTERNING OF A HARD MASK MATERIAL - A method for processing a substrate includes providing the substrate including a photoresist/bottom anti-reflection coating (PR/BARC) layer, a hard mask layer, a stop layer, a carbon layer and a stack including a plurality of layers. The method includes defining a hole pattern including a plurality of holes in the PR/BARC layer using photolithography; transferring the hole pattern into the carbon layer; filling the plurality of holes in the hole pattern with oxide to create oxide pillars; using a planarization technique to remove the hard mask layer, a remaining portion of the PR/BARC layer and the stop layer; stripping the carbon layer to expose the oxide pillars; filling space between the oxide pillars with hard a mask material including metal; planarizing at least part of the hard mask material; and stripping the oxide pillars to expose the hole pattern in the hard mask material. | 12-17-2015 |
Patent application number | Description | Published |
20140164169 | FOOT AND FOOTWEAR ANALYSIS CONFIGURATION - One embodiment is directed to system for analyzing the feet of a subject, wherein the subject may position and orient his feet in a capture configuration relative to a 3-dimensional camera, and the 3-dimensional camera may be utilized to capture a plurality of images about the subject's feet from a plurality of perspectives. A point cloud may be created based upon the captured images, and extraction procedures may be conducted to create individual, or discrete, point clouds for each of the feet from the overall superset point cloud created using the 3-dimensional imaging device. The discrete point clouds may be utilized to conduct various measurements of the feet, which may be utilized in various configurations, such as for shoe fitment or manufacturing. | 06-12-2014 |
20150235298 | FOOT AND FOOTWEAR ANALYSIS CONFIGURATION - One embodiment is directed to system for analyzing the feet of a subject, wherein the subject may position and orient his feet in a capture configuration relative to a 3-dimensional camera, and the 3-dimensional camera may be utilized to capture a plurality of images about the subject's feet from a plurality of perspectives. A point cloud may be created based upon the captured images, and extraction procedures may be conducted to create individual, or discrete, point clouds for each of the feet from the overall superset point cloud created using the 3-dimensional imaging device. The discrete point clouds may be utilized to conduct various measurements of the feet, which may be utilized in various configurations, such as for shoe fitment or manufacturing. | 08-20-2015 |
Patent application number | Description | Published |
20150130799 | ANALYSIS AND MANIPULATION OF IMAGES AND VIDEO FOR GENERATION OF SURROUND VIEWS - Various embodiments of the present invention relate generally to systems and methods for analyzing and manipulating images and video. According to particular embodiments, the spatial relationship between multiple images and video is analyzed together with location information data, for purposes of creating a representation referred to herein as a surround view. In particular embodiments, the surround view reduces redundancy in the image and location data, and presents a user with an interactive and immersive viewing experience. | 05-14-2015 |
20150130800 | SEGMENTATION OF SURROUND VIEW DATA - Various examples of the present disclosure include techniques and mechanisms for generating a surround view. According to various examples, a surround view is constructed from multiple images that are captured from different locations. A computer processor is used to create a three dimensional model that includes the content and context of the surround view. In some examples, the content and context can be segmented such that separate three dimensional models can be provided for each of the content of the surround view and the context of the surround view. | 05-14-2015 |
20150130894 | ANALYSIS AND MANIPULATION OF PANORAMIC SURROUND VIEWS - Various embodiments of the present invention relate generally to systems and methods for analyzing and manipulating images and video. According to particular embodiments, the spatial relationship between multiple images and video is analyzed together with location information data, for purposes of creating a representation referred to herein as a surround view. In particular embodiments, a surround view can be generated by combining a panoramic view of an object with a panoramic view of a distant scene, such that the object panorama is placed in a foreground position relative to the distant scene panorama. Such combined panoramas can enhance the interactive and immersive viewing experience of the surround view. | 05-14-2015 |
20150134651 | MULTI-DIMENSIONAL SURROUND VIEW BASED SEARCH - According to various examples, a surround view can be used as a visual search query for an object to be searched and this surround view can be compared to a database of three dimensional models. A determination can then be made about whether any of the three dimensional models match the visual search query. Based on how closely the three dimensional models match the visual search query, matching objects can be provided in various formats such as ranked lists. | 05-14-2015 |
20150138190 | ANALYSIS AND MANIPULATION OF OBJECTS AND LAYERS IN SURROUND VIEWS - Various embodiments of the present invention relate generally to systems and methods for analyzing and manipulating images and video. According to particular embodiments, the spatial relationship between multiple images and video is analyzed together with location information data, for purposes of creating a representation referred to herein as a surround view for presentation on a device. An object included in the surround view may be manipulated along axes by manipulating the device along corresponding axes. In particular embodiments, a surround view can be separated into layers. Effects can be applied to one or more of these layers to enhance the interactive and immersive viewing experience of the surround view. | 05-21-2015 |
20150339846 | ANALYSIS AND MANIPULATION OF OBJECTS AND LAYERS IN SURROUND VIEWS - Various embodiments of the present invention relate generally to systems and methods for analyzing and manipulating images and video. According to particular embodiments, the spatial relationship between multiple images and video is analyzed together with location information data, for purposes of creating a representation referred to herein as a surround view for presentation on a device. An object included in the surround view may be manipulated along axes by manipulating the device along corresponding axes. In particular embodiments, a surround view can be separated into layers. Effects can be applied to one or more of these layers to enhance the interactive and immersive viewing experience of the surround view. | 11-26-2015 |
Patent application number | Description | Published |
20140181596 | WEAR-OUT EQUALIZATION TECHNIQUES FOR MULTIPLE FUNCTIONAL UNITS - Wear-out equalization techniques for multiple functional hardware units are disclosed. An integrated circuit includes a power control unit (PCU) configured to monitor indicators of wear-out incurred by multiple functional hardware units of the integrated circuit. The PCU calculates cumulative wear-out metrics of the functional hardware units based on the monitored indicators and performs an equalization action to equalize the cumulative wear-out metrics of the functional hardware units. | 06-26-2014 |
20140184349 | APPARATUS, SYSTEM AND METHOD FOR CONFIGURING SIGNAL MODULATION - Techniques and mechanisms for configuring logic to implement a signal modulation. In an embodiment, the logic includes a finite impulse response (FIR) module comprising circuitry. The selection circuitry may be operable to concurrently receive signals from latch circuitry of the FIR module and, based on the signals, to select an input group of the selection circuitry and to output a voltage identifier. In another embodiment, configuration logic is operable to set an operational mode which determines a total number of concurrent input signals, received by the FIR module, which the FIR module will use to select an input group for generating an output representing a voltage level. | 07-03-2014 |
20140237267 | Dynamically Controlling A Maximum Operating Voltage For A Processor - In an embodiment, a processor includes voltage calculation logic to calculate a plurality of maximum operating voltage values each associated with a number of active cores of the plurality of cores, based at least in part on a plurality of coefficient values. In this way, the processor can operate at different maximum operating voltages dependent on the number of active cores. Other embodiments are described and claimed. | 08-21-2014 |
20140266340 | INTEGRATED CLOCK DIFFERENTIAL BUFFERING - Integrated clock differential buffering. A first phase locked loop (PLL) circuit having a first clocking ratio is coupled to receive an input differential clock signal. The first PLL circuit generates a first reference clock signal. A second PLL circuit having a second clocking ratio is coupled to receive the input differential clock signal. The second PLL circuit to generate a second reference clock signal. A first set of clock signal output buffers are coupled to receive the first reference clock signal and to provide a first differential reference clock signal corresponding to the first reference clock signal. A second set of clock signal output buffers is coupled to receive the second reference clock signal and to provide a second differential reference clock signal corresponding to the second reference clock signal. The first PLL circuit, the second PLL circuit, the first set of output buffers and the second set of output buffers reside within an integrated circuit package also having a die to receive at least the first differential reference clock signal. | 09-18-2014 |
20150067361 | Adaptively Controlling Low Power Mode Operation For A Cache Memory - In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a cache memory including a plurality of portions distributed across a die of the processor, a plurality of sleep circuits each coupled to one of the portions of the cache memory, and at least one sleep control logic coupled to the cache memory portions to dynamically determine a sleep setting independently for each of the sleep circuits and to enable the corresponding sleep circuit to maintain the corresponding cache memory portion at a retention voltage. Other embodiments are described and claimed. | 03-05-2015 |
20150188548 | INTEGRATED CLOCK DIFFERENTIAL BUFFERING - Integrated clock differential buffering. A first phase locked loop (PLL) circuit having a first clocking ratio is coupled to receive an input differential clock signal. The first PLL circuit generates a first reference clock signal. A second PLL circuit having a second clocking ratio is coupled to receive the input differential clock signal. The second PLL circuit to generate a second reference clock signal. A first set of clock signal output buffers are coupled to receive the first reference clock signal and to provide a first differential reference clock signal corresponding to the first reference clock signal. A second set of clock signal output buffers is coupled to receive the second reference clock signal and to provide a second differential reference clock signal corresponding to the second reference clock signal. The first PLL circuit, the second PLL circuit, the first set of output buffers and the second set of output buffers reside within an integrated circuit package also having a die to receive at least the first differential reference clock signal. | 07-02-2015 |
20160087918 | Converged Adaptive Compensation Scheme - Described is an apparatus which comprises: logic to convert output of at least one sensor to a digital sensing signal; a router coupled to the sensor, the router to receive the digital sensing signal and to map into circuit data; and one or more communication interfaces, coupled to the router, to forward circuit data to a circuit endpoint. Described is a method which comprises: providing one or more digital sensing signals from a plurality of sensors; receiving the one or more digital sensing signals; generating packets of data using the one or more digital sensing signals; and providing the packets of data to one or more destinations. | 03-24-2016 |
Patent application number | Description | Published |
20090085552 | POWER MANAGEMENT USING DYNAMIC EMBEDDED POWER GATE DOMAINS - In some embodiments of the invention, a processor with a power management scheme using dynamically switchable embedded power gates. | 04-02-2009 |
20090089607 | Systems and methods for voltage regulator communication - Systems and method for providing a regulated voltage supply to an integrated circuit. In an embodiment of the invention, a voltage regulator in a system provides an integrated circuit in the system with information related to the voltage regulator providing a supply voltage to the integrated circuit. In another embodiment of the invention, the integrated circuit makes determinations about the operating characteristic of the system using information from the voltage regulator. | 04-02-2009 |
20100033211 | Link transmitter with reduced power consumption - With some transmitter embodiments disclosed herein, static power consumption in low power modes may be reduced without excessively increasing latency. | 02-11-2010 |
20140173317 | APPARATUS AND METHOD FOR REDUCING LEAKAGE POWER OF A CIRCUIT - Described is a processor comprising: a plurality of transistors operable to provide dynamically adjustable transistor size, the plurality of transistors coupled at one end to a first power supply and coupled at another end to a second power supply; a circuit coupled to the second power supply, the second power supply to provide power to the circuit; and a power control unit (PCU) to monitor the level of the first power supply, and to dynamically adjust the transistor size of the plurality of transistors so that the second power supply is adjusted to keep the circuit operational. | 06-19-2014 |
20140201550 | APPARATUS, METHOD, AND SYSTEM FOR ADAPTIVE COMPENSATION OF REVERSE TEMPERATURE DEPENDENCE - Described herein are an apparatus, method, and system for adaptive compensation for reverse temperature dependence in a processor. The apparatus comprises: a first sensor to determine operating temperature of a processor; a second sensor to determine behavior of the processor; and a control unit to determine a frequency of a clock signal for the processor and a power supply level for the processor according to the determined operating temperature and behavior of the processor, wherein the control unit to increase the power supply level from an existing power supply level, and/or reduce frequency of the clock signal from an existing frequency of the clock signal when the operating temperature is in a region of reverse temperature dependence (RTD). | 07-17-2014 |
20160077567 | APPARATUS AND METHOD FOR REDUCING LEAKAGE POWER OF A CIRCUIT - Described is a processor comprising: a plurality of transistors operable to provide dynamically adjustable transistor size, the plurality of transistors coupled at one end to a first power supply and coupled at another end to a second power supply; a circuit coupled to the second power supply, the second power supply to provide power to the circuit; and a power control unit (PCU) to monitor the level of the first power supply, and to dynamically adjust the transistor size of the plurality of transistors so that the second power supply is adjusted to keep the circuit operational. | 03-17-2016 |
20160092396 | METHOD AND APPARATUS FOR STACKING A PLURALITY OF CORES - An apparatus and method are described for stacking a plurality of cores. For example, one embodiment of an apparatus comprises: a package; an uncore die mounted on the package, the uncore die comprising a plurality of exposed landing slots, each landing slot including an inter-die interface usable to connect vertically to a cores die, the uncore die including a plurality of uncore components usable by cores within the cores die including a memory controller component, a level 3 (L3) cache, a system memory or system memory interface, and a core interconnect fabric or bus; and a first cores die comprising a first plurality of cores, the cores spaced on the first cores die to correspond to all or a first subset of the landing slots on the uncore die, each of the cores having an inter-die interface positioned to be communicatively coupled to a corresponding inter-die interface within a landing slot on the uncore die when the first cores die is vertically coupled on top of the uncore die, wherein the communicative coupling between the inter-die interface of a core and the inter-die interface of its corresponding landing slot communicatively couples the core to the uncore components of the uncore die. | 03-31-2016 |