Patent application number | Description | Published |
20100097662 | SYSTEM AND METHOD FOR SCANNING AND PROCESSING PRINTED MEDIA - A method of scanning paper media, the method comprises rendering a three-dimensional (3D) dataset comprising a plurality of voxels that represents ink data and paper data within scanned paper media, orienting the 3D dataset to a coordinate system, perform voxel smoothing when undulations are present to remove the undulations, and electronically unfolding any folded pages. | 04-22-2010 |
20100322373 | SYSTEM AND METHOD FOR SCANNING AND PROCESSING PRINTED MEDIA - A mobile scanner is disclosed and may include a frame. A front axle and a rear axle may be attached to the frame. The front axle may include a first tire/wheel assembly mounted thereon and a second tire/wheel assembly mounted thereon. Further, the rear axle may include a first tire/wheel assembly mounted thereon and a second tire/wheel assembly mounted thereon. Moreover, a cab may be mounted on the frame and a body may be mounted on the frame adjacent to the cab. A volumetric document scanner may be disposed within the body. The volumetric document scanner may be configured to use x-ray computed tomography in order to scan documents and create a three-dimensional data set representing the documents. | 12-23-2010 |
20110031289 | WRIST WORN ELECTRONIC DEVICE HOLDER - A device for supporting an electronic device is disclosed and may include a wrist wrap. The wrist wrap may include an interior wrist wrap layer and an exterior wrist wrap layer. The device may also include at least one spring metal strip that may be disposed between the interior wrist wrap layer and the exterior wrist wrap layer. Further, the device may include at least one exterior fastener disposed on the exterior wrist wrap layer. The at least one exterior fastener may be configured to receive a fastener on a device engagement housing, a fastener on a portable electronic device, or a combination thereof. | 02-10-2011 |
20140175247 | EXHAUST PIPE TETHER - An exhaust pipe tether includes a body defining a first end and a second end and at least one end piece removably engaged with at least one of the first and second ends. The body comprises a dimension, d | 06-26-2014 |
Patent application number | Description | Published |
20080316659 | HIGH VOLTAGE ESD PROTECTION FEATURING PNP BIPOLAR JUNCTION TRANSISTOR - A protection circuit is disclosed that protects a semiconductor device from damage due to an electrostatic discharge. One such protection circuit comprises a vertical pnp hetero-junction bipolar transistor (HBT) connected between terminals such as supply terminals of the device, configured to conduct during an electrostatic discharge. The protection circuit also comprises a trigger circuit, such as a transient activated RC circuit connected between the terminals to detect the electrostatic discharge and control the transistor based on the detected electrostatic discharge. A Darlington transistor pair in the trigger circuit can be used to multiply the effective capacitance and HBT drive current. The HBT transistor absorbs energy from the electrostatic discharge and clamps the over-voltage across the terminals. The protection circuit may also be used across other I/O terminals of the device. | 12-25-2008 |
20130188286 | Low-Impedance High-Swing Power Supply with Integrated High Positive and Negative DC Voltage Protection and Electro-Static Discharge (ESD) Protection - An apparatus comprises a first PFET including a first intrinsic body diode; an electrostatic discharge (ESD) subcircuit coupled to a source of the first PFET; a reverse bias voltage element, such as a zener diode, an anode of which is coupled to a gate of the first PFET; a second PFET having a source coupled to a cathode of the zener diode a capacitor coupled to a gate the second PFET; and a first resistor coupled to the gate of the second PFET. The apparatus can protect against both positive and negative electro static transient discharge events. | 07-25-2013 |
20130264640 | DRAIN EXTENDED MOS TRANSISTOR HAVING SELECTIVELY SILICIDED DRAIN - A method of forming a drain extended metal-oxide-semiconductor (MOS) transistor includes forming a gate structure including a gate electrode on a gate dielectric on a semiconductor surface portion of a substrate. The semiconductor surface portion has a first doping type. A source is formed on one side of the gate structure having a second doping type. A drain is formed including a highly doped portion on another side of the gate structure having the second doping type. A masking layer is formed on a first portion of a surface area of the highly doped drain portion. A second portion of the surface area of the highly doped drain portion does not have the masking layer. Selectively siliciding is used to form silicide on the second portion. The masking layer blocks siliciding on the first portion so that the first portion is silicide-free. | 10-10-2013 |
20140035608 | SYSTEM AND METHOD FOR TESTING AN ELECTRONIC DEVICE - Adapters for electrostatic discharge probe tips are disclosed herein. An embodiment of the adapter includes an attachment device that is attachable to the tip of the probe. A first conductor is affixed to the attachment device so that the first conductor contacts the tip when the attachment device is attached to the tip of the probe. A second conductor extends between the first electrical conductor and a point external to the attachment device. | 02-06-2014 |
20140049864 | STATIC MEMS SWITCH FOR ESD PROTECTION - An integrated circuit with either a normally open MEMS ESD protection switch coupled between a bond pad and an internal circuit or a normally closed MEMS ESD protection switch coupled between the bond pad and a common reference of the integrated circuit. At least one of a control bond pad and an enable logic circuit is coupled to a control terminal of the MEMS ESD protection switch. | 02-20-2014 |
20140184237 | PACKAGED DEVICE FOR DETECTING FACTORY ESD EVENTS - An ESD monitor device may take the form of an integrated circuit with a plurality of monitor components available at each I/O site of the ESD monitor device. Each monitor component has a physical structure which provides scalable ESD robustness. The monitor components are connected in parallel to an ESD bus. An integrated circuit may be formed by processing an ESD monitor device through one or more process steps of an integrated circuit manufacturing line, and subsequently measuring the ESD monitor device. Parameters of a process step of the manufacturing line may be adjusted to reduce ESD events at the process step, based on measurement results from the ESD monitor device. The integrated circuit may subsequently be processed through the adjusted process step. | 07-03-2014 |
20140185168 | SHUT-OFF CIRCUITS FOR LATCHED ACTIVE ESD FET - An integrated circuit may include an over-capability detection circuit coupled to an I/O pad which provides a shut-off signal to a latch controlling an ESD protection shunting component. The ESD protection shunting component is coupled between the I/O pad and a reference node of the integrated circuit. The over-capability detection circuit provides the shut-off signal when safe operating conditions are resumed after a voltage excursion at the I/O pad. After receiving the shut-off signal, the latch biases the ESD protection shunting component into an off-state. | 07-03-2014 |
20150270253 | PROGRAMMABLE ESD PROTECTION CIRCUIT - An electrostatic discharge (ESD) protection circuit (FIG. | 09-24-2015 |
Patent application number | Description | Published |
20110286267 | Pattern-Sensitive Coding of Data for Storage in Multi-Level Memory Cells - A method of operating a memory device includes receiving first and second sets of bits to be stored in multi-level cells in the device. A multi-level encoding is selected from among a plurality of multi-level encodings for storing the first and second sets of bits in the multi-level cells. Each multi-level encoding includes at least four encoding levels for a respective multi-level cell. Respective multi-level encodings have respective costs associated with programming the first and second sets of bits into the multi-level cells in accordance with the respective multi-level encodings. The multi-level encoding is selected based on the respective costs of the respective encodings. The first and second sets of bits are encoded in accordance with the selected multi-level encoding to produce encoded data for storage in the device such that a respective multi-level cell stores respective bits from both the first and second sets of bits. | 11-24-2011 |
20120221769 | RECONFIGURABLE MEMORY CONTROLLER - Embodiments of a memory controller are described. This memory controller includes signal connectors, which are electrically coupled to a communication path that includes multiple links, and an interface circuit, which is electrically coupled to the signal connectors. In a first operating mode, the interface circuit communicates with a first memory device via the communication path using spatial multiplexing, in which there are dedicated command/address links and dedicated data links in the communication path. Moreover, in a second operating mode, the interface circuit communicates with a second memory device via the communication path using time multiplexing, in which at least some of the links in the communication path time interleave command/address information and data. | 08-30-2012 |
20140115296 | Remapping Memory Cells Based on Future Endurance Measurements - A method of operating a memory device that includes groups of memory cells is presented. The groups include a first group of memory cells. Each one of the groups has a respective physical address and is initially associated with a respective logical address. The device also includes an additional group of memory cells that has a physical address but is not initially associated with a logical address. In the method, a difference in the future endurance between the first group of memory cells and the additional group of memory cells is identified. When the difference in the future endurance between the first group and the additional group exceeds a predetermined threshold difference, the association between the first group and the logical address initially associated with the first group is ended and the additional group is associated with the logical address that was initially associated with the first group. | 04-24-2014 |
20140153310 | CONTENT ADDRESSABLE MEMORY - A content addressable memory can include an array of memory cells having multiple memory elements, such as RRAM elements, to store data based on a plurality resistive states. A common switching device, such as a transistor, can electrically couple a plurality of the multiple memory elements with a matchline during read, write, erase, and search operations. In search operations, the memory cells can receive a search word and selectively discharge a voltage level on the matchline based on the data stored by the memory elements and the search word provided to the memory elements. The voltage level of the matchline can indicate whether the search word matched the data stored in the memory cells. The content addressable memory can potentially have an effective memory cell sizing under 0.5F | 06-05-2014 |
20140181331 | Reconfigurable Memory Controller - Embodiments of a memory controller are described. This memory controller includes signal connectors, which are electrically coupled to a communication path that includes multiple links, and an interface circuit, which is electrically coupled to the signal connectors. In a first operating mode, the interface circuit communicates with a first memory device via the communication path using spatial multiplexing, in which there are dedicated command/address links and dedicated data links in the communication path. Moreover, in a second operating mode, the interface circuit communicates with a second memory device via the communication path using time multiplexing, in which at least some of the links in the communication path time interleave command/address information and data. | 06-26-2014 |
20140208188 | Variable Code Rate Transmission - An integrated circuit device includes an output buffer circuit that provides a first output having a first code rate. The first output is provided in response to a first indication of a change in a parameter that affects an error rate of the first output. The first output includes redundant information. The output buffer circuit provides a second output having a second code rate. The second output is provided in response to a second indication of the second output having an error rate that is different than the error rate of the first output. The second code rate of the second output is different than the first code rate. | 07-24-2014 |
20150248327 | MEMORY MODULE WITH DEDICATED REPAIR DEVICES - A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations. | 09-03-2015 |
20150254192 | Local Internal Discovery and Configuration of Individually Selected and Jointly Selected Devices - A memory controller ( | 09-10-2015 |
20150268862 | MULTIPLE MEMORY RANK SYSTEM AND SELECTION METHOD THEREOF - A multiple memory rank selection method and system assigns, based at least in part on decoding an assignment signal in a second command/address signal, a first terminal of a memory device to receive a first command/address signal and a second terminal of the memory device to receive the second command/address signal or assigns the first terminal of the memory device to receive the second command/address signal and the second terminal of the memory device to receive the first command/address signal. The multiple memory selection method and system decodes a selection signal encoded in the first command/address signal and enables the memory device based at least in part on the assignment signal and the selection signal. | 09-24-2015 |