Patent application number | Description | Published |
20100158665 | SUPERSONIC COMPRESSOR - A novel supersonic compressor is provided by the present invention. In one embodiment, the novel supersonic compressor comprises a fluid inlet, a fluid outlet, and at least two counter rotary supersonic compressor rotors, said supersonic compressor rotors being configured in series such that an output from a first supersonic compressor rotor having a first direction of rotation is directed to a second supersonic compressor rotor configured to counter-rotate with respect to the first supersonic compressor rotor. | 06-24-2010 |
20100329856 | SUPERSONIC COMPRESSOR COMPRISING RADIAL FLOW PATH - The present invention provides novel supersonic compressors comprising novel supersonic compressor rotors. The supersonic compressor rotors are designed to operate at very high rotational speed wherein the velocity of the gas entering the supersonic compressor rotor is greater than the local speed of sound in the gas, hence the descriptor “supersonic”. The new supersonic compressors comprise at least one supersonic compressor rotor defining an inner cylindrical cavity and an outer rotor rim and at least one radial flow channel allowing fluid communication between the inner cylindrical cavity and the outer rotor rim, said radial flow channel comprising a supersonic compression ramp. The novel supersonic compressor rotors are expected to enhance the performance of supersonic compressors comprising them, and to provide for greater design versatility in systems comprising such novel supersonic compressors. | 12-30-2010 |
20120156015 | SUPERSONIC COMPRESSOR AND METHOD OF ASSEMBLING SAME - A supersonic compressor includes a fluid inlet and a fluid outlet, a fluid conduit extending therebetween, and a supersonic compressor rotor disposed within the fluid conduit. The rotor includes at least one rotor disk that includes a substantially cylindrical body extending between a radially inner and outer surface and a plurality of vanes coupled to the body that extend radially outward from the rotor disk and adjacent vanes form a pair of vanes. The rotor disk further includes a shroud extending about at least a portion of the rotor disk. The shroud is coupled to at least a portion of each of the plurality of vanes. The radially outer surface, the pair of adjacent vanes, and the shroud are oriented such that a fluid flow channel is defined therebetween. The rotor disk also includes a plurality of adjacent supersonic compression ramps positioned within the fluid flow channel. | 06-21-2012 |
Patent application number | Description | Published |
20120141341 | Specimen Collection Container Assembly - A specimen collection container includes inner and outer tubes. The inner tube includes a bottom end, a top end, and a sidewall extending therebetween defining an interior. The sidewall includes an inner surface and an outer surface having at least one annular protrusion extending therefrom. The inner tube includes at least one funnel portion adjacent the top end for directing a specimen into the inner tube interior, and an annular ring disposed about a portion of the outer surface of the sidewall adjacent the top end. The outer tube includes a bottom end, a top end, and a sidewall extending therebetween, the sidewall having an outer surface and an inner surface defining an annular recess adapted to receive a portion of the annular protrusion therein. The inner tube is disposed within the outer tube and a portion of the top end of the outer tube abuts the annular ring. | 06-07-2012 |
20120210778 | Specimen Container Label for Automated Clinical Laboratory Processing Systems - A label and labeling system for identifying the volume of a specimen within a specimen collection container are disclosed. The system includes providing a specimen collection container having an open top end, a closed bottom end, and a sidewall extending therebetween forming an interior adapted for receiving a specimen therein. The specimen collection container also includes a label having a label body disposed over at least a portion of the sidewall, in visual alignment with a colored background. At least one of the sidewall of the specimen collection container and the label body have printing disposed thereon having a color that is substantially identical to the colored background against which the specimen collection container will be viewed. At least one of the sidewall of the specimen collection container and the label body may have colorless indicia having a surface enhancement feature for providing visual distinction. | 08-23-2012 |
20130251605 | Specimen Collection Container Assembly - A specimen collection container includes inner and outer tubes. The inner tube includes a bottom end, a top end, and a sidewall extending therebetween defining an interior. The sidewall includes an inner surface and an outer surface having at least one annular protrusion extending therefrom. The inner tube includes at least one funnel portion adjacent the top end for directing a specimen into the inner tube interior, and an annular ring disposed about a portion of the outer surface of the sidewall adjacent the top end. The outer tube includes a bottom end, a top end, and a sidewall extending therebetween, the sidewall having an outer surface and an inner surface defining an annular recess adapted to receive a portion of the annular protrusion therein. The inner tube is disposed within the outer tube and a portion of the top end of the outer tube abuts the annular ring. | 09-26-2013 |
20150135813 | Specimen Container Label for Automated Clinical Laboratory Processing Systems - A label and labeling system for identifying the volume of a specimen within a specimen collection container are disclosed. The system includes providing a specimen collection container having an open top end, a closed bottom end, and a sidewall extending therebetween forming an interior adapted for receiving a specimen therein. The specimen collection container also includes a label having a label body disposed over at least a portion of the sidewall, in visual alignment with a colored background. At least one of the sidewall of the specimen collection container and the label body have printing disposed thereon having a color that is substantially identical to the colored background against which the specimen collection container will be viewed. At least one of the sidewall of the specimen collection container and the label body may have colorless indicia having a surface enhancement feature for providing visual distinction. | 05-21-2015 |
Patent application number | Description | Published |
20110049680 | DUAL EXPOSURE TRACK ONLY PITCH SPLIT PROCESS - An integrated circuit is formed with structures spaced more closely together than a transverse dimension of such structures, such as for making contacts to electronic elements formed at minimum lithographically resolvable dimensions by dark field split pitch techniques. Acceptable overlay accuracy and process efficiency and throughput for the split pitch process that requires etching of a hard mark for each of a plurality of sequentially applied and patterned resist layers is supported by performing the etching of the hard mask entirely within a lithography track through using an acid sensitive hard mark material and an acidic overcoat which contacts areas of the hard mask through patterned apertures in the resist. The contacted areas of the hard mask are activated for development by baking of the acidic overcoat. | 03-03-2011 |
20130320546 | DUAL-METAL SELF-ALIGNED WIRES AND VIAS - Disclosed is a semiconductor structure which includes a semiconductor substrate and a wiring layer on the semiconductor substrate. The wiring layer includes a plurality of fin-like structures comprising a first metal; a first layer of a second metal on each of the plurality of fin-like structures wherein the first metal is different from the second metal, the first layer of the second metal having a height less than each of the plurality of fin-like structures; and an interlayer dielectric (ILD) covering the plurality of fin-like structures and the first layer of the second metal except for exposed edges of the plurality of fin-like structures at predetermined locations, and at locations other than the predetermined locations, the height of the plurality of fin-like structures has been reduced so as to be covered by the ILD. | 12-05-2013 |
20140256145 | DSA GRAPHO-EPITAXY PROCESS WITH ETCH STOP MATERIAL - A method for defining a template for directed self-assembly (DSA) materials includes forming an etch stop layer on a neutral material, forming a mask layer on the etch stop layer and forming an anti-reflection coating (ARC) on the mask layer. A resist layer is patterned on the ARC using optical lithography to form a template pattern. The ARC and the mask layer are reactive ion etched down to the etch stop layer in accordance with the template pattern to form a template structure. The ARC is removed from the mask layer and the template structure is trimmed to reduce a width of the template structure. A wet etch is performed to remove the etch stop layer to permit the neutral material to form an undamaged DSA template for DSA materials. | 09-11-2014 |
20140315390 | GRAPHO-EPITAXY DSA PROCESS WITH DIMENSION CONTROL OF TEMPLATE PATTERN - A method for defining a template for directed self-assembly (DSA) materials includes patterning a resist on a stack including an ARC and a mask formed over a hydrophilic layer. A pattern is formed by etching the ARC and the mask to form template lines which are trimmed to less than a minimum feature size (L). Hydrophobic spacers are formed on the template lines and include a fractional width of L. A neutral brush layer is grafted to the hydrophilic layer. A DSA material is deposited between the spacers and annealed to form material domains in a form of alternating lines of a first and a second material wherein the first material in contact with the spacers includes a width less than a width of the lines. A metal is added to the domains forming an etch resistant second material. The first material and the spacers are removed to form a DSA template pattern. | 10-23-2014 |
20140322917 | GRAPHO-EPITAXY DSA PROCESS WITH DIMENSION CONTROL OF TEMPLATE PATTERN - A method for defining a template for directed self-assembly (DSA) materials includes patterning a resist on a stack including an ARC and a mask formed over a hydrophilic layer. A pattern is formed by etching the ARC and the mask to form template lines which are trimmed to less than a minimum feature size (L). Hydrophobic spacers are formed on the template lines and include a fractional width of L. A neutral brush layer is grafted to the hydrophilic layer. A DSA material is deposited between the spacers and annealed to form material domains in a form of alternating lines of a first and a second material wherein the first material in contact with the spacers includes a width less than a width of the lines. A metal is added to the domains forming an etch resistant second material. The first material and the spacers are removed to form a DSA template pattern. | 10-30-2014 |
20140342549 | DUAL DAMASCENE DUAL ALIGNMENT INTERCONNECT SCHEME - A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions. | 11-20-2014 |
20150035154 | PROFILE CONTROL IN INTERCONNECT STRUCTURES - The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of the line opening prevents rounding of the corners of a dielectric material portion that is present beneath the line opening and adjacent the via opening. | 02-05-2015 |
20150050601 | DEVELOPABLE BOTTOM ANTIREFLECTIVE COATING COMPOSITION AND PATTERN FORMING METHOD USING THEREOF - The present invention relates to a developable bottom antireflective coating (BARC) composition and a pattern forming method using the BARC composition. The BARC composition includes a first polymer having a first carboxylic acid moiety, a hydroxy-containing alicyclic moiety, and a first chromophore moiety; a second polymer having a second carboxylic acid moiety, a hydroxy-containing acyclic moiety, and a second chromophore moiety; a crosslinking agent; and a radiation sensitive acid generator. The first and second chromophore moieties each absorb light at a wavelength from 100 nm to 400 nm. In the patterning forming method, a photoresist layer is formed over a BARC layer of the BARC composition. After exposure, unexposed regions of the photoresist layer and the BARC layer are selectively removed by a developer to form a patterned structure in the photoresist layer. The BARC composition and the pattern forming method are especially useful for implanting levels. | 02-19-2015 |
20150145048 | STRUCTURE AND METHOD FOR FORMING CMOS WITH NFET AND PFET HAVING DIFFERENT CHANNEL MATERIALS - Embodiments of the present invention provide an improved structure and method for forming CMOS field effect transistors. In embodiments, silicon germanium (SiGe) is formed on a PFET side of a semiconductor structure, while silicon is disposed on an NFET side of a semiconductor structure. A narrow isolation region is formed between the PFET and NFET. The NFET fins are comprised of silicon and the PFET fins are comprised of silicon germanium. | 05-28-2015 |
20150380251 | BLOCK MASK LITHO ON HIGH ASPECT RATIO TOPOGRAPHY WITH MINIMAL SEMICONDUCTOR MATERIAL DAMAGE - A trilayer stack that can be used as a block mask for forming patterning features in semiconductor structures with high aspect ratio topography is provided. The trilayer stack includes an organic planarization (OPL) layer, a titanium-containing antireflective coating (TiARC) layer on the OPL layer and a photoresist layer on the TiARC layer. Employing a combination of an OPL having a high etch rate and a TiARC layer that can be easily removed by a mild chemical etchant solution in the trilayer stack can significantly minimize substrate damage during lithographic patterning processes. | 12-31-2015 |
Patent application number | Description | Published |
20100330756 | INTEGRATED CIRCUIT STRUCTURE MANUFACTURING METHODS USING HARD MASK AND PHOTORESIST COMBINATION - A method of manufacturing an integrated circuit structure implants a first-type of channel implant in a first area of a substrate and implants a second-type of channel implant in a second area of the substrate. The method forms at least one first gate conductor above the first area of the substrate and forms at least one second gate conductor above the second area of the substrate. The method forms a hard mask over the first gate conductor, the second gate conductor, and the substrate. The hard mask comprises an oxide or a nitride and patterns an organic photoresist over the hard mask, to leave the organic photoresist on areas of the hard mask that are above the first area of the substrate. The method removes portions of the hard mask not protected by the organic photoresist to leave the hard mask on the first area of the substrate and not on the second area of the substrate. The method then removes the organic photoresist, implants impurities in the second area of the substrate to form source and drain regions adjacent the second gate conductor; and removes the hard mask using a wet etching process. | 12-30-2010 |
20110108961 | DEVICE HAVING AND METHOD FOR FORMING FINS WITH MULTIPLE WIDTHS - A method for fabrication of features for an integrated circuit includes patterning a mandrel layer to include structures having at least one width on a surface of an integrated circuit device. Exposed sidewalls of the structures are reacted to integrally form a new compound in the sidewalls such that the new compound extends into the exposed sidewalls by a controlled amount to form pillars. One or more layers below the pillars are etched using the pillars as an etch mask to form features for an integrated circuit device. | 05-12-2011 |
20120280365 | DEVICE HAVING AND METHOD FOR FORMING FINS WITH MULTIPLE WIDTHS - A structure for a semiconductor device is disclosed. The structure includes a first feature and a second feature. The first feature and the second feature are formed simultaneously in a single etch process from a same monolithic substrate layer and are integrally and continuously connected to each other. The first feature has a width dimension of less than a minimum feature size achievable by lithography and the second feature has a width dimension of at least equal to a minimum feature size achievable by lithography. | 11-08-2012 |
20130012025 | DEVICE HAVING AND METHOD FOR FORMING FINS WITH MULTIPLE WIDTHS - A method for fabrication of features for an integrated circuit includes patterning a mandrel layer to include structures having a plurality of different widths on a surface of an integrated circuit device. Exposed sidewalls of the structures are reacted to integrally form a new compound in the sidewalls such that the new compound extends into the exposed sidewalls by a controlled amount to form pillars. One or more layers below the pillars are etched using the pillars as an etch mask to form features for an integrated circuit device. | 01-10-2013 |
Patent application number | Description | Published |
20140110846 | DUAL HARD MASK LITHOGRAPHY PROCESS - A first metallic hard mask layer over an interconnect-level dielectric layer is patterned with a line pattern. At least one dielectric material layer, a second metallic hard mask layer, a first organic planarization layer (OPL), and a first photoresist are applied above the first metallic hard mask layer. A first via pattern is transferred from the first photoresist layer into the second metallic hard mask layer. A second OPL and a second photoresist are applied and patterned with a second via pattern, which is transferred into the second metallic hard mask layer. A first composite pattern of the first and second via patterns is transferred into the at least one dielectric material layer. A second composite pattern that limits the first composite pattern with the areas of the openings in the first metallic hard mask layer is transferred into the interconnect-level dielectric layer. | 04-24-2014 |
20150221591 | OVERLAY-TOLERANT VIA MASK AND REACTIVE ION ETCH (RIE) TECHNIQUE - A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal. | 08-06-2015 |
20150255286 | DEEP WELL IMPLANT USING BLOCKING MASK - Various methods include: forming an opening in a resist layer to expose a portion of an underlying blocking layer; performing an etch on the exposed portion of the blocking layer to expose a portion of an etch stop layer, wherein the etch stop layer resists etching during the etch of the exposed portion of the blocking layer; etching the exposed portion of the etch stop layer to expose a portion of a substrate below the exposed portion of the etch stop layer and leave a remaining portion of the etch stop layer; and ion implanting the exposed portion of the substrate, wherein the blocking layer prevents ion implanting of the substrate outside of the exposed portion. | 09-10-2015 |