Patent application number | Description | Published |
20120062286 | TERAHERTZ PHASED ARRAY SYSTEM - Microelectronics have now developed to the point where radiation within the terahertz frequency range can be generated and used. Here, an integrated circuit or IC is provided that includes a phased array radar system, which uses terahertz radiation. In order to accomplish this, several features are employed; namely, a lower frequency signal is propagated to transceivers, which multiplies the frequency up to the desired frequency range. To overcome the losses from the multiplication, an injection locked voltage controlled oscillator (ILVCO) is used, and a high frequency power amplifier (PA) can then be used to amplify the signal for transmission. | 03-15-2012 |
20120068238 | LOW IMPEDANCE TRANSMISSON LINE - Transmission lines employing transmission line units or elements within integrated circuits (ICs) are well-known. Typically, different heights for these transmission line units can vary the characteristics of the cell (and transmission line), and there is typically a tradeoff between impedance and space (layout) specifications. Here, a transmission line is provided, which is generally comprised of elements of the same general width, but having differing or tapered heights that allow for impedance adjustments for high frequency applications (i.e., 160 GHz). For example, a transmission line that is coupled to a balun, with the transmission line units decreasing in height near the balun's center tap to adjust the impedance of the transmission line for the balun, is shown. | 03-22-2012 |
20120261579 | ANALOG BASEBAND CIRCUIT FOR A TERAHERTZ PHASED ARRAY SYSTEM - A method for determining the position of a target is provided. Several emitted pulses of terahertz radiations are emitted from a phased array (which has several transceivers) in consecutive cycles (typically). These emitted pulses are generally configured to be reflected by a target so as to be received by the phased array within a scan range (which includes a digitization window with several sampling periods). Output signals from each of the transceivers are then combined to generate a combined signal for each cycle. The combined signal in each sampling period within the digitization window for emitted pulses is averaged to generate an averaged signal for each sampling period within the digitization window. These averaged signals are then digitized. | 10-18-2012 |
20120293217 | FEEDFORWARD ACTIVE DECOUPLING - There are a variety of duty cycle systems, such as low noise amplifiers or LNAs, that have a large time varying current consumption, and parasitic inductances and resistance (usually from bondwires in the package) that can significantly affect supply currents. Thus, to compensate for these parasitics, a boost circuit is provided that allows for current to be supplied from a separate supply using a feedforward scheme to perform active decoupling. | 11-22-2012 |
20120299797 | HIGH IMPEDANCE SURFACE - An apparatus for emitting radiation is provided. The apparatus comprises an antenna formed on a substrate, and a high impedance surface (HIS). The HIS has a plurality of cells formed on the substrate that are arranged to form an array that substantially surrounds at least a portion of the antenna. Each cell generally includes a ground plane, first plate, second plate, and an interconnect. The ground plane is formed on the substrate, while the first plate (which is substantially rectangular) is formed over and coupled to the ground plane. The first plate for each cell is also arranged so as to form a first checkered pattern for the array. The second plate (which is substantially rectangular) is formed over and is substantially parallel to the first plate. The first and second plates are also substantially aligned with a central axis that extends generally perpendicular to the first and second plates hand have a interconnect formed therebetween. The second plate for each cell is also arranged so as to form a second checkered pattern for the array. | 11-29-2012 |
20120306574 | WIDE BANDWIDTH CLASS C AMPLIFIER WITH COMMON-MODE FEEDBACK - A method for providing common-mode feedback is provided. A common-mode current is applied to a common-gate amplifier, and the common-mode current is sensed. In response to the sensed common-mode current, a control voltage is generated. A first feedback current (which is generated in response to the control voltage) can then be applied to differential ground of the common-gate amplifier if the common-mode current is less than a predetermined threshold. Additionally, a second feedback current (which is generated in response to the control voltage) can be applied to input terminals of the common-gate amplifier if the common-mode current is greater than the predetermined threshold. | 12-06-2012 |
20120313895 | TOUCH SCREEN - A method for determining the location of an object on a touch panel is provided. Initially, a pulse of terahertz radiation is transmitted through a touch panel, which formed of a dielectric material such that the pulse generates a evanescent field in a region adjacent to a touch surface of the touch panel. A reflected pulse is generated by an object located within the region adjacent to the touch surface of the touch panel, and a position of the object on the touch surface of the touch panel is triangulated at least in part from the reflected pulse. | 12-13-2012 |
20130021208 | LOOP ANTENNA - A loop antenna is provided. The apparatus comprises a substrate, a first metallization layer, and a second metallization layer. The substrate has first and second feed terminals and a ground terminal. The first metallization layer is disposed over the substrate and includes a first window conductive region, a first conductive region, a second conductive region, and a third conductive region. The first conductive region is disposed over and is in electrical contact with the first feed terminal; it is also is substantially circular and located within the first window region. The second conductive region is disposed over and is in electrical contact with the second feed terminal; it is also substantially circular and is located within the first window region. The a third conductive region is disposed over and is in electrical contact with the ground terminal, and the third conductive region substantially surrounds the first window region. The second metallization layer is disposed over and is in electrical contact with the first, second, and third conductive regions of the first metallization layer, and the second metallization layer includes a second window region that is at least partially aligned with the first window region. | 01-24-2013 |
20130026586 | CROSS-LOOP ANTENNA - An antenna is provided. This antenna is contained within a package that is secured to an IC (which allows radiation to propagated away for a printed circuit board so as to reduce interference), and this antenna includes two loop antennas that are shorted to ground and that “overlap” and includes a “via wall.” With this configuration, circular polarization can be achieved by varying the relative phases of the input signals, and the “via wall” improves efficiency by reducing surface waves. | 01-31-2013 |
20130059551 | ROUTING FOR A PACKAGE ANTENNA - An apparatus is provided. A plurality of transceiver antennas are arranged to form a phased array, where each antenna include a differential transmit antenna and a differential receive antenna arranged in a first pattern. A plurality of transceivers are arranged in a second pattern that is substantially symmetrical, and each transceiver is associated with at least one of the transceiver antennas and includes a feed network. Each feed network has a power amplifier (PA), a first matching network that is coupled between the PA and its associated transmit antenna so as to translate the phase of each differential transmit signal, a low noise amplifier (LNA), and a second matching network that is coupled between the LNA and its associated receive antenna so as to translate the phase of each differential receive signal. | 03-07-2013 |
20130120186 | DELAY LOCKED LOOP - A method for providing a plurality of narrow pulses is provided. A first pulse having a first width is received by a delay line having a plurality of delay cells. This first pulse has a first width. In response to this first pulse, a plurality of second pulses is generated by the delay line, where each second pulse has a second width that is less than the first width. First and second delay pulses are also generated by the delay line, and a delay for each delay cell in the delay line can then be adjusted if a rising edge of the second delay pulse is misaligned with a falling edge of the first delay pulse. | 05-16-2013 |
20140111366 | FINE GRAINED DUTY CYCLING AND TIMING CONTROL FOR PULSED RADAR - A method is provided. A first edge on a first gating signal is generated, and a local oscillator and a shared clocking circuit with the first edge on the first gating signal. A second edge on a second gating signal is generated following the first edge on the first gating signal, and a receiver circuit is activated with the second edge on the second gating signal, where the receiver circuit includes a mixer. A transmit pulse following the first edge on the first gating signal is generated with the transmit pulse having a third edge. A switch that short circuits outputs of the mixer is then released following the later of the third edge of the transmit pulse and a delay. | 04-24-2014 |
20140111394 | WAVEGUIDE COUPLER - An apparatus is provided. In the apparatus, there is an antenna package and an integrated circuit (IC). A circuit trace assembly is secured to the IC. A coupler (with an antenna assembly and a high impedance surface (HIS)) is secured to the circuit trace assembly. An antenna assembly has a window region, a conductive region that substantially surrounds the window region, a circular patch antenna that is in communication with the IC, and an elliptical patch antenna that is located within the window region, that is extends over at least a portion of the circular patch antenna, and that is in communication with the circular patch antenna. The HIS substantially surrounds the antenna assembly. | 04-24-2014 |
20140139297 | BALUN WITH INTEGRATED DECOUPLING AS GROUND SHIELD - An apparatus is provided. Transmission line cells are formed in a first region. A first metallization layer is formed over the transmission line cells within a portion of the first region. At least a portion of the first metallization layer is electrically coupled to the plurality of transmission line cells. A second metallization layer is formed over the first metallization layer with an interconnect portion, and overlay portion, and a first balun. The interconnect portion at least partially extends into the first region, and the overlay portion is within the first region. The first balun winding is electrically coupled to the overlay portion and partially extends into a second region. The first region partially surrounds the second region. A third metallization layer is formed over the second metallization layer having a second balun winding within the second region, where the second winding is generally coaxial with the first balun winding. | 05-22-2014 |
20140198550 | FREQUENCY MULTIPLIER - An apparatus is provided. A differential pair of transistors is configured to receive a first differential signal having a first frequency, and a transformer, having a primary side and a secondary side is provided. The primary side of the transformer is coupled to the differential pair of transistors, and the secondary side of the transformer is configured to output a second differential signal having a second frequency, where the second frequency is greater than the first frequency. A first transistor is coupled to the first supply rail, the primary side of the transformer, and the differential pair of transistors, where the first transistor is of a first conduction type. A second transistor is coupled to the second supply rail, the primary side of the transformer, and the differential pair of transistors, where the second transistor is of a second conduction type. | 07-17-2014 |
20140285277 | Dielectric Waveguide Manufactured Using Printed Circuit Board Technology - A dielectric waveguide may be manufactured by forming a set of parallel channels in a planar sheet that has a lower dielectric constant value. The set of channels is then filled with a material having a higher dielectric constant value. The planar sheet is sliced into a plurality of strips that each contain one or more of the channels. | 09-25-2014 |
20140287701 | Integrated Circuit with Dipole Antenna Interface for Dielectric Waveguide - An electronic device has a multilayer substrate that has an interface surface configured for interfacing to a dielectric waveguide. A conductive layer on the substrate is etched to form a dipole antenna disposed adjacent the interface surface to provide coupling to the dielectric waveguide. A reflector structure is formed in the substrate adjacent the dipole antenna opposite from the interface surface. | 09-25-2014 |
Patent application number | Description | Published |
20100078674 | INSULATED GATE BIPOLAR TRANSISTOR - A trench structure of an insulated gate bipolar transistor (IGBT) is formed as a trench net in a P region and extends into an N− layer. The trench net separates the P region into P wells and floating P layers. The P wells contact an emitter electrode while the floating P layers are not in direct contact with the emitter electrode. A gate formed of conductive material and having a surrounding insulation oxide layer is formed in the trench net. An N+ layer may be formed above each floating P layer under the gate. The floating P layers are isolated from the gate and are also not connected to the emitter electrode. | 04-01-2010 |
20110312137 | Vertical Power MOSFET and IGBT Fabrication Process with Two Fewer Photomasks - A process for fabrication of a power semiconductor device is disclosed in which a single photomask is used to define each of p-conductivity well regions and n-conductivity type source regions. In the process a single photomask is deposited on a layer of polysilicon on a wafer, the polysilicon layer is removed from first regions of the power semiconductor device where the p-conductivity well regions and the n-conductivity type source regions are to be formed, and both p-conductivity type and n-conductivity type dopants are introduced into the wafer through the first regions. | 12-22-2011 |
20120168861 | POWER TRANSISTOR WITH INCREASED AVALANCHE CURRENT AND ENERGY RATING - A field-effect transistor involves a drain electrode, a drift region, a body region, a source region, a gate insulator layer, and a gate electrode. The drift region is disposed above the drain electrode. The body region extends down into the drift region from a first upper semiconductor surface. The source region is ladder-shaped and extends down in the body region from a second upper semiconductor surface. The first and second upper semiconductor surfaces are substantially planar and are not coplanar. A first portion of the body region is surrounded laterally by a second portion of the body region. The second portion of the body region and the drift region meet at a body-to-drift boundary. The body-to-drift boundary has a central portion that is non-planar. A gate insulator layer is disposed over the source region and a gate electrode is disposed over the gate insulator. | 07-05-2012 |
20130107583 | Low forward voltage rectifier | 05-02-2013 |
20130127017 | Bipolar Junction Transistor For Current Driven Synchronous Rectifier - A Reverse Bipolar Junction Transistor (RBJT) integrated circuit comprises a bipolar transistor and a parallel-coupled distributed diode. The bipolar transistor involves many N-type collector regions. Each N-type collector region has a central hole so that P-type material from an underlying P-type region extends up into the hole. A collector metal electrode covers the central hole forming a diode contact at the top of the hole. When the distributed diode conducts, current flows from the collector electrode, down through the many central holes in the many collector regions, through corresponding PN junctions, and to an emitter electrode disposed on the bottom side of the IC. The RBJT and distributed diode integrated circuit has emitter-to-collector and emitter-to-base reverse breakdown voltages exceeding twenty volts. The collector metal electrode is structured to contact the collector regions, and to bridge over the base electrode, resulting in a low collector-to-emitter voltage when the RBJT is on. | 05-23-2013 |
20130128626 | Transformer Drive For Low Conduction Loss Rectifier In Flyback Converter - A flyback converter involves a bipolar transistor (BJT) and a parallel-connected diode as the rectifying element in the secondary side of the converter. The transformer of the converter has a primary winding, a first secondary winding, and a second secondary winding. A first end of the first secondary winding is coupled to the BJT base. A first end of the second secondary winding is coupled to the BJT collector and to the anode of the diode. The first and second secondary windings are wound such that when primary winding current stops, pulses of current flow out of the first ends of the first and second secondary windings. These currents are such that the BJT is maintained in saturation throughout at least most of the time current flows through the rectifying element, thereby achieving a low forward voltage across the rectifying element, reducing conduction loss, and increasing converter efficiency. | 05-23-2013 |
20130249529 | LOW FORWARD VOLTAGE RECTIFIER USING CAPACITIVE CURRENT SPLITTING - A Low Forward Voltage Rectifier (LFVR) circuit includes a bipolar transistor, a parallel diode, and a capacitive current splitting network. The LFVR circuit, when it is performing a rectifying function, conducts the forward current from a first node to a second node provided that the voltage from the first node to the second node is adequately positive. The capacitive current splitting network causes a portion of the forward current to be a base current of the bipolar transistor, thereby biasing the transistor so that the forward current experiences a low forward voltage drop across the transistor. The LFVR circuit sees use in as a rectifier in many different types of switching power converters, including in flyback, Cuk, SEPIC, boost, buck-boost, PFC, half-bridge resonant, and full-bridge resonant converters. Due to the low forward voltage drop across the LFVR, converter efficiency is improved. | 09-26-2013 |
20130285210 | FULL BRIDGE RECTIFIER MODULE - A full bridge rectifier includes four bipolar transistors, each of which has an associated parallel diode. A first pair of inductors provides inductive current splitting and thereby provides base current to/from one pair of the bipolar transistors so that the collector-to-emitter voltages of the bipolar transistors are low. A second pair of inductors similarly provides inductive current splitting to provide base current to/from the other pair of bipolar transistors. In one embodiment, all components are provided in a four terminal full bridge rectifier module. The module can be used as a drop-in replacement for a conventional four terminal full bridge diode rectifier. When current flows through the rectifier module, however, the voltage drop across the module is less than one volt. Due to the reduced low voltage drop, power loss in the rectifier module is reduced as compared to power loss in a conventional full bridge diode rectifier. | 10-31-2013 |
20140118055 | IGBT DIE STRUCTURE WITH AUXILIARY P WELL TERMINAL - An IGBT die structure includes an auxiliary P well region. A terminal, that is not connected to any other IGBT terminal, is coupled to the auxiliary P well region. To accelerate IGBT turn on, a current is injected into the terminal during the turn on time. The injected current causes charge carriers to be injected into the N drift layer of the IGBT, thereby reducing turn on time. To accelerate IGBT turn off, charge carriers are removed from the N drift layer by drawing current out of the terminal. To reduce V | 05-01-2014 |
20140119064 | LOW FORWARD VOLTAGE RECTIFIER - A Low Forward Voltage Rectifier (LFVR) includes a bipolar transistor, a parallel diode, and a base current injection circuit disposed in an easy-to-employ two-terminal package. In one example, the transistor is a Reverse Bipolar Junction Transistor (RBJT), the diode is a distributed diode, and the base current injection circuit is a current transformer. Under forward bias conditions (when the voltage from the first package terminal to the second package terminal is positive), the LFVR conducts current at a rated current level with a low forward voltage drop (for example, approximately 0.1 volts). In reverse bias conditions, the LFVR blocks current flow. Using the LFVR in place of a conventional silicon diode rectifier in the secondary of a flyback converter reduces average power dissipation and increases power supply efficiency. | 05-01-2014 |
20140273357 | Vertical Power MOSFET And IGBT Fabrication Process With Two Fewer Photomasks - A process for fabrication of a power semiconductor device is disclosed in which a single photomask is used to define each of p-conductivity well regions and n-conductivity type source regions. In the process a single photomask is deposited on a layer of polysilicon on a wafer, the polysilicon layer is removed from first regions of the power semiconductor device where the p-conductivity well regions and the n-conductivity type source regions are to be formed, and both p-conductivity type and n-conductivity type dopants are introduced into the wafer through the first regions. | 09-18-2014 |
20140273384 | POWER TRANSISTOR WITH INCREASED AVALANCHE CURRENT AND ENERGY RATING - A field-effect transistor involves a drain electrode, a drift region, a body region, a source region, a gate insulator layer, and a gate electrode. The drift region is disposed above the drain electrode. The body region extends down into the drift region from a first upper semiconductor surface. The source region is ladder-shaped and extends down in the body region from a second upper semiconductor surface. The first and second upper semiconductor surfaces are substantially planar and are not coplanar. A first portion of the body region is surrounded laterally by a second portion of the body region. The second portion of the body region and the drift region meet at a body-to-drift boundary. The body-to-drift boundary has a central portion that is non-planar. A gate insulator layer is disposed over the source region and a gate electrode is disposed over the gate insulator. | 09-18-2014 |
20150138839 | FORWARD CONVERTER WITH SELF-DRIVEN BJT SYNCHRONOUS RECTIFIER - An AC-to-DC converter circuit includes DC-to-DC converter that in turn includes a secondary side circuit. The secondary side circuit includes a secondary winding, a pair of bipolar transistor-based self-driven synchronous rectifiers, a pair of current splitting inductors, and an output capacitor. Each of the synchronous rectifiers includes a bipolar transistor and a diode whose anode is coupled to the transistor collector and whose cathode is coupled to the transistor emitter. The current splitting inductors provide the necessary base current to the bipolar transistors at the appropriate times such that the bipolar transistors operate as synchronous rectifiers. As compared to using conventional self-driven synchronous rectifiers based on field effect transistors in the secondary side, using the novel bipolar-transistor based synchronous rectifiers in the secondary side of the forward converter circuit results in lower power consumption and allows the converter to operate from a wider range of VAC input voltages. | 05-21-2015 |
20150155785 | BUCK CONVERTER HAVING SELF-DRIVEN BJT SYNCHRONOUS RECTIFIER - A switching converter has a self-driven bipolar junction transistor (BJT) synchronous rectifier. The BJT rectifier includes a BJT and a parallel-connected diode, and has a low forward voltage drop. In a first portion of a switching cycle, a main switch is on and the BJT rectifier is off. Current flows from an input, through the main switch, through the first inductor, to an output. Current also flows through the main switch, through the second inductor, to the output. In a second portion of the cycle, the main switch is turned off but the inductor currents continue to flow. Current flows from a ground node, through the BJT rectifier, through the first inductor, to the output. The BJT is on due to the second inductor drawing a base current from the BJT. In one example, the main switch is a split-source NFET that conducts separate currents through the two inductors. | 06-04-2015 |
20150200184 | Full Bridge Rectifier Module - A full bridge rectifier includes four bipolar transistors, each of which has an associated parallel diode. A first pair of inductors provides inductive current splitting and thereby provides base current to/from one pair of the bipolar transistors so that the collector-to-emitter voltages of the bipolar transistors are low. A second pair of inductors similarly provides inductive current splitting to provide base current to/from the other pair of bipolar transistors. In one embodiment, all components are provided in a four terminal full bridge rectifier module. The module can be used as a drop-in replacement for a conventional four terminal full bridge diode rectifier. When current flows through the rectifier module, however, the voltage drop across the module is less than one volt. Due to the reduced low voltage drop, power loss in the rectifier module is reduced as compared to power loss in a conventional full bridge diode rectifier. | 07-16-2015 |
20150236601 | Low Forward Voltage Rectifier Using Capacitive Current Splitting - A Low Forward Voltage Rectifier (LFVR) circuit includes a bipolar transistor, a parallel diode, and a capacitive current splitting network. The LFVR circuit, when it is performing a rectifying function, conducts the forward current from a first node to a second node provided that the voltage from the first node to the second node is adequately positive. The capacitive current splitting network causes a portion of the forward current to be a base current of the bipolar transistor, thereby biasing the transistor so that the forward current experiences a low forward voltage drop across the transistor. The LFVR circuit sees use in as a rectifier in many different types of switching power converters, including in flyback, Cuk, SEPIC, boost, buck-boost, PFC, half-bridge resonant, and full-bridge resonant converters. Due to the low forward voltage drop across the LFVR, converter efficiency is improved. | 08-20-2015 |
20150311811 | Low Forward Voltage Rectifier - A Low Forward Voltage Rectifier (LFVR) includes a bipolar transistor, a parallel diode, and a base current injection circuit disposed in an easy-to-employ two-terminal package. In one example, the transistor is a Reverse Bipolar Junction Transistor (RBJT), the diode is a distributed diode, and the base current injection circuit is a current transformer. Under forward bias conditions (when the voltage from the first package terminal to the second package terminal is positive), the LFVR conducts current at a rated current level with a low forward voltage drop (for example, approximately 0.1 volts). In reverse bias conditions, the LFVR blocks current flow. Using the LFVR in place of a conventional silicon diode rectifier in the secondary of a flyback converter reduces average power dissipation and increases power supply efficiency. | 10-29-2015 |
20160056723 | Buck Converter Having Self-Driven BJT Synchronous Rectifier - A switching converter has a self-driven bipolar junction transistor (BJT) synchronous rectifier. The BJT rectifier includes a BJT and a parallel-connected diode, and has a low forward voltage drop. In a first portion of a switching cycle, a main switch is on and the BJT rectifier is off. Current flows from an input, through the main switch, through the first inductor, to an output. Current also flows through the main switch, through the second inductor, to the output. In a second portion of the cycle, the main switch is turned off but the inductor currents continue to flow. Current flows from a ground node, through the BJT rectifier, through the first inductor, to the output. The BJT is on due to the second inductor drawing a base current from the BJT. In one example, the main switch is a split-source NFET that conducts separate currents through the two inductors. | 02-25-2016 |
Patent application number | Description | Published |
20160007325 | DOWNLINK PHYSICAL LAYER PROTOCOL DATA UNIT FORMAT IN A HIGH EFFICIENCY WIRELESS LAN - The present invention provides a new downlink frame format to support MU-MIMO and OFDMA, and methods, apparatuses, etc. therefor. In an aspect of the present invention, a method for transmitting data to a plurality of STAs by an AP in a WLAN may include generating a HE-LTF field for the plurality of STAs, and transmitting a PPDU frame to the plurality of STAs, the PPDU frame including the HE-LTF field and data for the plurality of STAs. The data for the plurality of STAs may be transmitted to different STA on each of a plurality of subchannels, and a starting point of the HE-LTF field may be same across the plurality of STAs and an end point of the HE-LTF field may be same across the plurality of STAs. | 01-07-2016 |
20160007342 | PHYSICAL LAYER PROTOCOL DATA UNIT FORMAT IN A HIGH EFFICIENCY WIRELESS LAN - The present invention provides a new uplink PPDU frame format to support MU-MIMO and OFDMA, and methods, apparatuses, etc. therefor. In an aspect of the present invention, a method by a STA for transmitting an UL PPDU frame to an AP simultaneously with one or more other STAs in a WLAN may include receiving a frame including a parameter for the PPDU frame from the AP; and participating in UL MU PPDU frame transmission based on the parameter. | 01-07-2016 |
20160029373 | DOWNLINK ACKNOWLEDGMENT IN RESPONSE TO UPLINK MULTIPLE USER TRANSMISSION - The present invention provides a method and apparatus for transmitting a downlink ACK in response to an uplink multi-user transmission in a HE WLAN. In an aspect of the present invention, a method for transmitting an ACK in response to uplink data received from a plurality of STAs by an AP in a WLAN may be provided. The method may include transmitting a frame triggering transmission of a plurality of uplink data units from the plurality of STAs to the plurality of STAs, receiving a PPDU frame including a plurality of uplink data units from the plurality of STAs a predetermined IFS after transmitting the trigger frame, and transmitting an ACK frame including ACKs for the plurality of data units from the plurality of STAs. | 01-28-2016 |
20160043855 | DYNAMIC INTER-FRAME SPACE PROCESSING IN HIGH EFFICIENCY WIRELESS LAN - The present invention relates to a transmission and receiving method and apparatus using a dynamically determined Inter-Frame Space (IFS) in a Wireless Local Area Network (WLAN). According to one aspect of the present invention, a method for processing a received frame by a Station (STA) in a WLAN may include receiving a first frame including downlink data for a plurality of STAs, if the received first frame has no error, transmitting a second frame including an ACKnowledgement (ACK) of the STA simultaneously with ACKs of one or more other STAs, and if the received first frame has an error, performing carrier sensing using a variably determined IFS. | 02-11-2016 |
20160044635 | INTERLEAVER FOR PHYSICAL LAYER PROTOCOL DATA UNIT IN A HIGH EFFICIENCY WIRELESS LAN - The present invention provides a method and apparatus for transmitting using an interleaver applied to a PPDU in a HE WLAN. In an aspect of the present invention, a method for transmitting data to a plurality of STAs through transmission channel by an AP in a WLAN system, wherein the transmission channel is divided into a plurality of subchannels which are allocated to the plurality of STAs respectively, the method may include interleaving a plurality of data units for the plurality of STAs based on characteristics of the plurality of subchannels allocated to the plurality of STAs to generate a plurality of interleaved data units; and transmitting, through the transmission channel, a Physical layer Protocol Data Unit (PPDU) frame including the plurality of interleaved data units respectively on the plurality of subchannels to the plurality of STAs. | 02-11-2016 |
20160050634 | TRANSMISSION POWER CONTROL FOR DEVICE IN HIGH EFFICIENCY WIRELESS LAN - The present invention relates to transmission power control for a device operating in a Wireless Local Area Network (WLAN) system, and a transmission and reception method and apparatus using the transmission power control. According to an aspect of the present invention, a method for transmitting an uplink frame to an Access Point (AP) by a Station (STA) in a WLAN system may include receiving first transmission power control information and second transmission power control information from the AP, if a type related to the uplink frame is a first type, determining a maximum transmission power based on the first transmission power control information, if the type related to the uplink frame is a second type, determining a maximum transmission power based on the second transmission power control information, and transmitting the uplink frame based on the determined maximum transmission power. The first type and the second type may correspond to different access schemes for uplink transmission. | 02-18-2016 |
20160050659 | RATE DETERMINATION IN HIGH EFFICIENCY WIRELESS LAN - The present invention relates to a method and apparatus for determining a transmission rate in a Wireless Local Area Network (WLAN). According to one aspect of the present invention, a method for receiving an uplink frame from a Station (STA) by an Access Point (AP) in a WLAN may be provided. The method may include transmitting to the STA a downlink frame eliciting the uplink frame, and receiving the uplink frame from the STA at a rate determined based on whether the type of the uplink frame is a single user type or a multi-user type. | 02-18-2016 |
20160056930 | PHYSICAL LAYER PROTOCOL DATA UNIT FORMAT APPLIED WITH SPACE TIME BLOCK CODING IN A HIGH EFFICIENCY WIRELESS LAN - The present invention relates to a method and apparatus for transmitting and receiving signals using a Physical layer Protocol Data unit (PPDU) format to which Space-Time Block Coding (STBC) is applied in a Wireless Local Area Network (WLAN). According to one aspect of the present invention, a method for transmitting data to a plurality of Stations (STAs) on a transmission channel by an Access Point (AP) in a WLAN may be provided. The transmission channel may be divided into a plurality of subchannels allocated to the plurality of STAs. The method may include generating a High Efficiency-Long Training Field (HE-LTF) field having a length determined based on whether Space-Time Block Coding (STBC) is applied to the plurality of subchannels, and transmitting a Physical layer Protocol Data Unit (PPDU) frame including the HE-LTF field and a plurality of data units for the plurality of STAs to the plurality of STAs. | 02-25-2016 |
20160057657 | PHYSICAL LAYER PROTOCOL DATA UNIT FORMAT INCLUDING PADDING IN A HIGH EFFICIENCY WIRELESS LAN - The present invention relates to a Physical layer Protocol Data unit (PPDU) format including a padding. According to one aspect of the present invention, a method for transmitting data to a plurality of stations on a transmission channel by an Access Point in a WLAN may be provided. The transmission channel may be divided into a plurality of subchannels allocated to the plurality of stations. The method may include generating a padding having a length individually for each of one or more subchannels to which paddings are applied among the plurality of subchannels, the length of the padding making transmissions end simultaneously on the plurality of subchannels, and transmitting a PPDU frame including a data unit without the padding or a data unit added with the padding for each of the plurality of subchannels to the plurality of stations on the transmission channel. | 02-25-2016 |
20160088602 | UPLINK ACKNOWLEDGMENT RESPONSE TO DOWNLINK MULTIPLE USER TRANSMISSION - The present invention provides a method and apparatus for transmitting an Uplink (UL) ACKnowledgement (ACK) in response to a Downlink (DL) Multi-User (MU) transmission in a Wireless Local Area Network (WLAN). According to one aspect of the present invention, a method for transmitting an ACK in response to a DL data transmission from an Access Point (AP) by a Station (STA) in a WLAN may be provided. The method may include receiving, from the AP, a downlink frame including downlink data for the STA and downlink data for one or other STAs, and transmitting an ACK frame to the AP in response to the downlink data for the S_TA, simultaneously with transmission of ACK frames from the one or more other STAs. The ACK frames transmitted by the STA and the one or more other STAs may have the same length. | 03-24-2016 |
20160100396 | BEAMFORMED TRANSMISSION IN HIGH EFFICIENCY WIRELESS LAN - The present invention relates to a method and apparatus for beamformed transmission in a wireless local area network. According to one aspect of the present invention, a method for transmitting a Physical layer Protocol Data Unit (PPDU) frame to a plurality of stations (STAs) by an Access Point (AP) in a wireless local area network may be provided. The method may include transmitting a SIGNAL field of the PPDU frame, the SIGNAL field including beamforming information indicating whether beamforming is applied to respective data units of the PPDU frame, and transmitting the data units of the PPDU frame, the data units being individually beamformed or not beamformed according to the beamforming information. | 04-07-2016 |
20160105836 | DYNAMIC RESOURCE ALLOCATION IN A HIGH EFFICIENCY WIRELESS LAN - The present invention relates to a method and apparatus for dynamically allocating resources in a High Efficiency WLAN (Wireless Local Area) (HEW). According to one aspect of the present invention, a method for resource switching in a WLAN may be provided. The method may include receiving, by a station (STA) from an access point (AP), a downlink multiple user (DL MU) frame on a resource indicated by first resource allocation information, the DL MU frame including the first resource allocation information and second resource allocation information for a next MU frame following the DL MU frame, and processing, by the STA, the next MU frame based on a resource indicated by the second resource allocation information. | 04-14-2016 |
20160113009 | BANDWIDTH DETERMINATION FOR MULTIPLE USER TRANSMISSION IN A HIGH EFFICIENCY WIRELESS LAN - The present disclosure relates to a method and apparatus for determining a bandwidth for Multi-User (MU) transmission in a High Efficiency WLAN (HEW). According to one aspect of the present disclosure, a method for transmitting by a Station (STA) to an Access point (AP) an uplink Physical layer Protocol Data Unit (PPDU) frame in a WLAN may be provided. The method may include receiving a trigger frame including bandwidth information, the trigger frame eliciting a transmission of the uplink PPDU frame including a data unit of the STA and at least one data unit of at least one other STA, and transmitting the data unit of the STA in the uplink PPDU frame, based on an available bandwidth of the STA and a bandwidth indicated by the bandwidth information included in the trigger frame. | 04-21-2016 |
20160113034 | METHOD AND APPARATUS FOR UPLINK CHANNEL ACCESS IN A HIGH EFFICIENCY WIRELESS LAN - The present disclosure relates to a method and apparatus for uplink channel access in a High Efficiency WLAN (HEW). According to one aspect, a method for transmitting an uplink frame by a station (STA) to an access point (AP) in a wireless local area network may be provided. The method may include receiving from the AP a trigger frame for eliciting an uplink transmission from the STA, transmitting to the AP the uplink frame according to a type of the trigger frame, wherein when the uplink frame is transmitted in an uplink multiple user (MU) transmission, the uplink frame includes a padding added by the STA such that transmissions from a plurality of STAs including the STA in the uplink MU transmission end at a same time indicated by the trigger frame, and receiving from the AP a frame in response to the uplink MU transmission a predetermined time after an end of the uplink MU transmission. | 04-21-2016 |