Il-Young
Il Young Han, Euiwang-Si KR
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20130139380 | CHIP BONDING APPARATUS AND CHIP BONDING METHOD USING THE SAME - A chip bonding apparatus configured to bond chips to a circuit board using induction heating generated by an AC magnetic field may be provided. In particular, the chip bonding apparatus includes at least one stage unit configured to support a circuit board on which a chip is placed, a rotating unit configured to rotatively move the at least one stage unit at a desired angle, and a bonding unit including an induction heating antenna configured to perform induction heating such the chip is bonded to the circuit board. | 06-06-2013 |
20130248114 | CHIP BONDING APPARATUS - A bonding apparatus includes at least one stage unit to support a circuit board having a chip thereon and a bonding unit coupled to the stage unit to define a chamber. The bonding unit has at least one inductive heater to heat to bond the chip to the circuit board, and the stage unit includes a vacuum generator configured to generate a vacuum between the stage unit and the circuit board. The vacuum is used to hold the circuit board on the stage unit during bonding of the chip to the circuit board. The induction heater may include one or more induction heating antennas, and the chamber may include one or more stage units. | 09-26-2013 |
Il Young Jeong, Suwon-Si KR
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20150108089 | METHOD FOR CUTTING SUBSTRATE - A method for cutting a substrate includes: radiating, as part of a first laser radiating process, a laser towards a surface of the substrate to form a first groove in a substrate. Radiating the laser towards the surface includes radiating, in sequence, the laser towards a first outer point (FOP), a second outer point (SOP), a first intermediate point (FIP), a second intermediate point (SIP), and a first cut point (FCP) of the surface, each of the points being spaced apart from one another by one or more distances. The FCP corresponds to a cut line of the substrate. The FOP and the SOP are respectively disposed at lateral sides of the FCP. The FIP is disposed between the FCP and the FOP. The SIP is disposed between the FCP and the SOP. The same kind and intensity of laser is radiated towards each of the points. | 04-23-2015 |
Il Young Kwon, Seoul KR
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20100027353 | Erase Method of Flash Device - In an erase method of a flash device, including a page buffer configured to transfer a virtual voltage in response to a discharge signal and further comprising strings each including memory cells and coupled to the page buffer via a respective bit line, applying a ground voltage to a gate of each of the memory cells and erasing the memory cells coupled to a selected bit line by supplying the virtual voltage wherein the virtual voltage is applied to the selected bit line and a unselected bit line. | 02-04-2010 |
20130240994 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, and a gate line, located over the substrate, which includes a first conductive layer and one or more second conductive pattern layers located in the first conductive layer. The second conductive pattern layer comprises a metal layer to thus reduce resistance of a gate line. | 09-19-2013 |
20140334230 | SEMICONDUCTOR MEMORY DEVICE AND SYSTEM HAVING THE SAME - A semiconductor memory device includes a first dummy transistor coupled to a bit line, a first select transistor formed where a first selection line surrounds a vertical channel layer, a second dummy transistor coupled to a common source line, a second select transistor formed where a second selection line surrounds the vertical channel layer, and main cell transistors coupled between the first and second select transistors. | 11-13-2014 |
20150056769 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, and a gate line, located over the substrate, which includes a first conductive layer and one or more second conductive pattern layers located in the first conductive layer. The second conductive pattern layer comprises a metal layer to thus reduce resistance of a gate line. | 02-26-2015 |
Il-Young Han, Uiwang-Si KR
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20090141275 | ALIGNMENT INSPECTION METHOD AND ALIGNMENT INSPECTION APPARATUS - A method of inspecting the alignment of a second structure with respect to a first structure, including emitting light from a first plane of a first structure to a second plane of a second structure in a first direction perpendicular to the first plane of the first structure, the first plane and the second plane facing each other. The incident light can be reflected from the second plane toward the first plane in a second direction parallel with the first direction. The position of the reflected light can be detected to inspect the alignment of the second structure with respect to the first structure. | 06-04-2009 |
20120234497 | DEBONDER TO MANUFACTURE SEMICONDUCTOR AND DEBONDING METHOD THEREOF - A debonder to manufacture a semiconductor that includes: a stage to support a carrier wafer that is attached to a chip stack assembly by a temporary adhesive layer coated on the surface of the carrier wafer; a chuck arranged above the stage to selectively secure the chip stack assembly; a lifting unit to lift the chuck from the stage; a lateral driving unit to move the chuck laterally with respect to the stage; and a controller to control the lifting unit and the lateral driving unit. | 09-20-2012 |
20120298656 | APPARATUS FOR FABRICATING SEMICONDUCTOR DEVICES - An apparatus for fabricating semiconductor devices includes a chamber having a bottom plane, a side wall and a lid. An irradiating unit is at an interior of the chamber. A substrate mounting unit is between the bottom plane of the chamber and the irradiating unit. The irradiating unit includes an irradiating tube and a hole penetrating the central region of the irradiating tube. The irradiating tube has a hollow disk shape, and a lower surface of the irradiating tube is opened to the substrate mounting unit. | 11-29-2012 |
Il-Young Han, Gyeonggi-Do KR
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20090134202 | REFLOW APPARATUS AND METHOD - Provided are a reflow apparatus and method. The reflow apparatus includes a loader unit, a heating unit, an unloader unit, and a moving unit. The loader unit has an input module and an input stacker. Processing objects are stored in vertical stacks in magazines, and a plurality of magazines is stored in the input stacker. The magazines stored in the input stacker are moved to the input module and are introduced into the heating unit by the moving unit. Solder balls provided on the processing objects within the heating unit are quickly processed using an induction heating method. The processing objects that have undergone a reflow process are loaded in a magazine on an output module of the unloader unit and are then stored in an output stacker. | 05-28-2009 |
Il-Young Jung, Bucheon KR
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20100327760 | INVERTER DEVICE AND DRIVING METHOD THEREOF - The present invention relates to an inverter and the driving method. The inverter according to exemplary embodiment of the present invention generates a plurality of feedback voltages corresponding to driving voltages of a plurality of discharge lamps. The inverter generates a first minimum voltage having a smaller feedback voltage of a plurality of feedback voltages and compares the first minimum voltage and a short circuit reference voltage in order to determine a short circuit of at least two discharge lamps. The inverter senses a short circuit lamp of a plurality of the discharge lamps by using the comparison result and a first sawtooth wave signal having a predetermined period. Also, the inverter generates a plurality of feedback voltages corresponding to driving currents of a plurality of discharge lamps, generates a second minimum voltage having a smaller feedback voltage of a plurality of the feedback voltages, and compares the second minimum voltage and an open circuit reference voltage in order to determine the open circuit of the at least two discharge lamps. The inverter senses an open circuit lamp of a plurality of discharge lamps by using the comparison result and a first sawtooth wave signal having a predetermined period. | 12-30-2010 |
20110037407 | LED LIGHT EMITTING DEVICE - The present invention relates to an LED light emitting device. An LED light emitting device includes a plurality of LED channels including a plurality of LEDs. The LED light emitting device further includes a transformer configured to convert an input voltage and supply an output voltage to the plurality of LED channels, a controller, and an LED driver. The controller controls the transformer according to a first feedback signal for interrupting power supply to the plurality of LED channels when a dimming off state in which currents are not supplied to the plurality of LED channels occurs or when a state in which the maximum channel voltage of a plurality of channel voltages corresponding to voltages applied to the plurality of LED channels, respectively, is an overvoltage and a defective state in which the plurality of LED channels include an open state are maintained during a predetermined threshold period. The LED driver generates information on the dimming off state and information on the defective state. Further, the LED driver is connected to a secondary side of the transformer, the controller is connected to a primary side of the transformer insulated from the secondary side, and the first feedback signal is generated according to the information on the dimming off state and the information on the defective state. | 02-17-2011 |
20120170165 | ADAPTIVE OVERVOLTAGE PROTECTION CIRCUIT AND METHOD, AND POWER SYSTEM INCLUDING THE SAME - An adaptive over-voltage protection circuit includes an over-voltage protection reference voltage provider and an over-voltage signal output unit. The over-voltage protection reference voltage provider provides a voltage of an over-voltage protection level higher than that of an over-voltage protection voltage corresponding to an output voltage supplied to a load from among a plurality of different over-voltage protection levels as an over-voltage protection reference voltage when the output voltage reaches a range of a rated voltage of the load. The over-voltage signal output unit outputs an over-voltage signal indicating an over-voltage by comparing the over-voltage protection voltage with the over-voltage protection reference voltage. | 07-05-2012 |
Il-Young Lee, Yongin-Si KR
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20150156445 | IMAGE PROCESSING APPARATUS AND CONTROL METHOD THEREOF - An image processing apparatus and control method is provided. The image processing apparatus includes a processor including one or more processing modules configured to process data, a power supply configured to supply an operating voltage to the one or more processing modules in a normal operation mode, a sensor configured to detect a temperature of the processor, and a controller configured to change the processor from the normal operation mode to one of a first operation mode and a second operation mode according to the temperature detected by the sensor, control the power supply to supply a lower level operating voltage to at least one of the one or more processing modules when the processor is in the first operation mode, and reset or disable at least one processing module selected from the one or more processing modules when the processor is in the second operation mode. | 06-04-2015 |
Il-Young Yoon, Gyeonggi-Do KR
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20080290446 | SHALLOW TRENCH ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES INCLUDING WET ETCH BARRIERS AND METHODS OF FABRICATING SAME - A semiconductor device includes a sidewall oxide layer covering an inner wall of a trench, a nitride liner on the sidewall oxide layer and a gap-fill insulating layer filling the trench on the nitride liner. A first impurity doped oxide layer is provided at edge regions of both end portions of the sidewall oxide layer so as to extend from an entry of the trench adjacent to an upper surface of the substrate to the nitride liner. A dent filling insulating layer is provided on the nitride liner in the trench to protect a surface of the first impurity doped oxide layer. Related methods are also disclosed. | 11-27-2008 |
20100007021 | Methods of Fabricating Semiconductor Devices Including Porous Insulating Layers - Semiconductor devices including a substrate and an uppermost insulating layer formed on the substrate and having pores is provided. A conductive wiring is provided in the uppermost insulating layer. Dummy vias are provided, each penetrating the uppermost insulating layer, being adjacent to the conductive wiring, and having a space therein. Related methods of fabricating semiconductor devices are also provided. | 01-14-2010 |
20150056795 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor devices includes providing a semiconductor substrate that includes a channel region. The method includes forming a gate electrode material film including a stepped portion on the channel region. A sacrificial material film that has an etch selectivity that is the same as an etch selectivity of the gate electrode material film is formed. The sacrificial material film is planarized until a top surface of the gate electrode material film is exposed. The stepped portion is reduced by removing an exposed portion of the gate electrode material film. | 02-26-2015 |