Patent application number | Description | Published |
20100254866 | NOVEL APPROACH IN CONTROLLING DSP SCALE IN BAYER PROCESS - The invention provides a method of controlling silica in the liquor circuit of the Bayer process. The method involves addition of a promoter material to enhance the precipitation of DSP and includes adding one or more silica dispersion materials or dry silica forms to those parts of the circuit where precipitation of DSP and removal of silica from solution is desirable; for example the desilication stage of a Bayer process plant. The removal of DSP from solution reduces silica concentration in the liquor and thereby enables better control of process issues such as silica contamination in alumina product and DSP formation in later stages of the process where precipitation as scale onto vessel walls and equipment is problematical. As a result, the invention provides a significant reduction in the total cost of operating a Bayer process. | 10-07-2010 |
20110076209 | REDUCING ALUMINOSILICATE SCALE IN THE BAYER PROCESS - The invention provides a method of inhibiting the accumulation of DSP scale in the liquor circuit of Bayer process equipment. The method includes adding one or more particular silane based small molecules to the liquor fluid circuit. These scale inhibitors reduce DSP scale formation and thereby increase fluid throughput, increase the amount of time Bayer process equipment can be operational and reduce the need for expensive and dangerous acid washes of Bayer process equipment. As a result, the invention provides a significant reduction in the total cost of operating a Bayer process. | 03-31-2011 |
20110200503 | COMPOSITION AND METHOD FOR IMPROVED ALUMINUM HYDROXIDE PRODUCTION - An improved method and composition for producing aluminum hydroxide crystals from precipitation liquor, involves the addition of an emulsified crystal growth modifier comprising a C | 08-18-2011 |
20110212006 | REDUCING ALUMINOSILICATE SCALE IN THE BAYER PROCESS - The invention provides a method of inhibiting the accumulation of DSP scale in the liquor circuit of Bayer process equipment. The method includes adding one or more particular silane based small molecules to the liquor fluid circuit. These scale inhibitors reduce DSP scale formation and thereby increase fluid throughput, increase the amount of time Bayer process equipment can be operational and reduce the need for expensive and dangerous acid washes of Bayer process equipment. As a result, the invention provides a significant reduction in the total cost of operating a Bayer process. | 09-01-2011 |
Patent application number | Description | Published |
20090090970 | SOI SUBSTRATE CONTACT WITH EXTENDED SILICIDE AREA - A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact. | 04-09-2009 |
20090093092 | SOI SUBSTRATE CONTACT WITH EXTENDED SILICIDE AREA - A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact. | 04-09-2009 |
20100084736 | SOI SUBSTRATE CONTACT WITH EXTENDED SILICIDE AREA - A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact. | 04-08-2010 |
20100164075 | TRENCH FORMING METHOD AND STRUCTURE - An electrical structure and method of forming. The method includes providing a semiconductor structure comprising a semiconductor substrate, a buried oxide layer (BOX) formed over the semiconductor substrate, and a silicon on insulator layer (SOI) formed over and in contact with the BOX layer. The SOI layer comprises shallow trench isolation (STI) structures formed between electrical devices. A first photoresist layer is formed over the STI structures and the electrical devices. Portions of said first photoresist layer, portions of the STI structures, and portions of the BOX layer are removed resulting in formed trenches. Ion implants are formed within portions of the semiconductor substrate. Remaining portions of the first photoresist layer are removed. A dielectric layer is formed over the electrical devices and within the trenches. A second photoresist layer is formed over the dielectric layer. Portions of the second photoresist layer are removed. | 07-01-2010 |
20100230752 | SOI (SILICON ON INSULATOR) SUBSTRATE IMPROVEMENTS - A structure, and a method for forming the same. The structure includes a semiconductor substrate which includes a top substrate surface, a buried dielectric layer on the top substrate surface, N active semiconductor regions on the buried dielectric layer, N active devices on the N active semiconductor regions, a plurality of dummy regions on the buried dielectric layer, a protection layer on the N active devices and the N active semiconductor regions, but not on the plurality of dummy regions. The N active devices comprise first active regions which comprise a first material. The plurality of dummy regions comprise first dummy regions which comprise the first material. A first pattern density of the first active regions and the first dummy regions is uniform across the structure. A trench in the buried dielectric layer such that side walls of the trench are aligned with the plurality of dummy regions. | 09-16-2010 |
20110278570 | SCALING OF BIPOLAR TRANSISTORS - Bipolar transistor structures, methods of designing and fabricating bipolar transistors, methods of designing circuits having bipolar transistors. The method of designing the bipolar transistor includes: selecting an initial design of a bipolar transistor; scaling the initial design of the bipolar transistor to generate a scaled design of the bipolar transistor; determining if stress compensation of the scaled design of the bipolar transistor is required based on dimensions of an emitter of the bipolar transistor after the scaling; and if stress compensation of the scaled design of the bipolar transistor is required then adjusting a layout of a trench isolation layout level of the scaled design relative to a layout of an emitter layout level of the scaled design to generate a stress compensated scaled design of the bipolar transistor. | 11-17-2011 |