Patent application number | Description | Published |
20100308310 | EMISSIVE ARYL-HETEROARYL ACETYLENES - Disclosed herein are compounds represented by a formula: R | 12-09-2010 |
20100326526 | EMISSIVE ARYL-HETEROARYL COMPOUNDS - Disclosed herein are compounds represented by Formula 1, wherein R | 12-30-2010 |
20100327269 | EMISSIVE TRIARYLS - Disclosed herein are compounds represented by Formula 1. Compositions and light-emitting devices related thereto are also disclosed. | 12-30-2010 |
20110062386 | COMPOUNDS FOR ORGANIC LIGHT EMITTING DIODE EMISSIVE LAYERS - Disclosed herein are compounds represented by a formula: | 03-17-2011 |
20120015998 | PHOTOTHERAPY METHODS AND DEVICES COMPRISING EMISSIVE ARYL-HETEROARYL COMPOUNDS - Disclosed herein are compounds represented by a formula: R | 01-19-2012 |
20120226046 | COMPOUNDS FOR POROUS FILMS IN LIGHT-EMITTING DEVICES - Compounds useful in porous films for light extraction and/or light scattering in electronic devices, such as light-emitting devices, are described herein. These compounds may be represented by Formula 1, as described herein. | 09-06-2012 |
20130075706 | SUBSTITUTED BIARYL COMPOUNDS FOR LIGHT-EMITTING DEVICES - Some substituted biaryl ring systems may be useful in light-emitting devices, such as those comprising a light-emitting diode. For example, substituted bipyridinyl or substituted phenylpyridinyl may be useful in these devices. The substituted biaryl ring system may have at least two different substituents, including one on each ring on the biaryl system. The first substituent may include optionally substituted carbazolyl, optionally substituted diphenylamine, optionally substituted diphenylaminophenyl, and optionally substituted carbazolylphenyl. The second substituent may include optionally substituted benzimidazol-2-yl, optionally substituted benzoxazol-2-yl, and an optionally substituted benzothiazol-2-yl. | 03-28-2013 |
20130284907 | EMISSIVE ARYL-HETEROARYL COMPOUNDS - Disclosed herein are compounds represented by Formula 1, wherein R | 10-31-2013 |
Patent application number | Description | Published |
20110157191 | METHOD AND SYSTEM FOR ARTIFICALLY AND DYNAMICALLY LIMITING THE FRAMERATE OF A GRAPHICS PROCESSING UNIT - Embodiments of the present invention are directed to provide a method and system for applying automatic power conservation techniques in a computing system. Embodiments are described herein that automatically limits the frame rate of an application executing in a discrete graphics processing unit operating off battery or other such exhaustible power source. By automatically limiting the frame rate in certain detected circumstances, the rate of power consumption, and thus, the life of the current charge stored in a battery may be dramatically extended. Another embodiment is also provided which allows for the more effective application of automatic power conservation techniques during detected periods of inactivity by applying a low power state immediately after a last packet of a frame is rendered and displayed. | 06-30-2011 |
20140092113 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR PROVIDING A DYNAMIC DISPLAY REFRESH - A system, method, and computer program product are provided for a dynamic display refresh. In use, a state of a display device is identified in which an entirety of an image frame is currently displayed by the display device. In response to the identification of the state, it is determined whether an entirety of a next image frame to be displayed has been rendered to memory. The next image frame is transmitted to the display device for display thereof, when it is determined that the entirety of the next image frame to be displayed has been rendered to the memory. Further, a refresh of the display device is delayed, when it is determined that the entirety of the next image frame to be displayed has not been rendered to the memory. | 04-03-2014 |
20140184508 | UNIVERSAL ADAPTIVE GAME CONTROLLER - One or more embodiments of the present invention may include a body comprising a user interface, wherein the user interface is operable to be configured for a first interactive media device and a second interactive media device. The one or more embodiments may further include memory operable to store a plurality of user interface configurations, wherein a first user interface configuration corresponds to the first interactive media device and the second interactive media device, and wherein the memory is further operable to store a software application state. The one or more embodiments may additionally include a communication interface operable to communicatively couple with the first interactive media device and the second interactive media device, wherein the communication interface is operable to send user inputs from the user interface to the first interactive media device and the second interactive media device. | 07-03-2014 |
Patent application number | Description | Published |
20100329058 | PROCESSOR INSTRUCTION CACHE WITH DUAL-READ MODES - A processor includes a cache memory. The cache memory includes an array of cells, word lines and bit lines. A control module enables a word line of the word lines to access a first cell in the enabled word line. The control module disables the word line and maintains the word line in a disabled state to access a second cell in the word line. | 12-30-2010 |
20120014196 | PROCESSOR INSTRUCTION CACHE WITH DUAL-READ MODES - A processor including a cache memory, a decoder, a precharge circuit, a control module, and an amplifier module. The decoder generates a first word line signal to access first instructions stored in a first word line, and (ii) generates a second word line signal to access second instructions stored in the first word line or a second word line. The precharge circuit (i) precharges first bit lines connected to the first word line prior to accessing each of the first and second instructions. The control module adjusts a rate of a clock signal from a first rate to a second rate. The amplifier module accesses the first instructions based on (i) the first word line signal and (ii) the clock signal at the first rate, and accesses the second instructions based on (i) the second word line signal and (ii) the clock signal at the second rate. | 01-19-2012 |
20130044555 | PROCESSOR WITH MEMORY DELAYED BIT LINE PRECHARGING - A processor includes an array of memory cells, a control module, a precharge circuit, and an amplifier module. The control module generates a clock signal at a first rate, reduces the first rate to a second rate for a predetermined period, and adjusts the second rate back to the first rate at an end of the predetermined period. The precharge circuit: based on the first rate, precharges first bit lines connected to memory cells in a first row of the array of memory cells; based on the second rate, refrains from precharging the first bit lines; and precharges the first bit lines subsequent to the end of the predetermined period. The amplifier module: based on the first rate, access first instructions stored in the first row; and based on the second rate, accesses second instructions stored in the first row or a second row of the array. | 02-21-2013 |