Patent application number | Description | Published |
20110148894 | DEMAND-PAGED TEXTURES - A method and system may include a chip having graphics rendering hardware, a cache and a processor to execute an application with texture allocation logic to receive notification of a page miss from the graphics rendering hardware. The logic can map the page miss to a tile of a texture image, store the tile as an entry to the cache, and map the entry to a virtual address space of a virtual image corresponding to the texture image. The system may also include off-chip memory to store the texture image. | 06-23-2011 |
20110153989 | SYNCHRONIZING SIMD VECTORS - A vector compare-and-exchange operation is performed by: decoding by a decoder in a processing device, a single instruction specifying a vector compare-and-exchange operation for a plurality of data elements between a first storage location, a second storage location, and a third storage location; issuing the single instruction for execution by an execution unit in the processing device; and responsive to the execution of the single instruction, comparing data elements from the first storage location to corresponding data elements in the second storage location; and responsive to determining a match exists, replacing the data elements from the first storage location with corresponding data elements from the third storage location. | 06-23-2011 |
20120079244 | METHOD AND APPARATUS FOR UNIVERSAL LOGICAL OPERATIONS - An apparatus and method are described for performing arbitrary logical operations specified by a table. For example, one embodiment of a method for performing a logical operation on a computer processor comprises: reading data from each of two or more source operands; combining the data read from the source operands to generate an index value, the index value identifying a subset of bits within an immediate value transmitted with an instruction; reading the bits from the immediate value; and storing the bits read from the immediate value within a destination register to generate a result of the instruction. | 03-29-2012 |
20120144089 | SCATTER/GATHER ACCESSING MULTIPLE CACHE LINES IN A SINGLE CACHE PORT - Methods and apparatus are disclosed for accessing multiple data cache lines for scatter/gather operations. Embodiment of apparatus may comprise address generation logic to generate an address from an index of a set of indices for each of a set of corresponding mask elements having a first value. Line or bank match ordering logic matches addresses in the same cache line or different banks, and orders an access sequence to permit a group of addresses in multiple cache lines and different banks. Address selection logic directs the group of addresses to corresponding different banks in a cache to access data elements in multiple cache lines corresponding to the group of addresses in a single access cycle. A disassembly/reassembly buffer orders the data elements according to their respective bank/register positions, and a gather/scatter finite state machine changes the values of corresponding mask elements from the first value to a second value. | 06-07-2012 |
20120166761 | VECTOR CONFLICT INSTRUCTIONS - A processing core implemented on a semiconductor chip is described having first execution unit logic circuitry that includes first comparison circuitry to compare each element in a first input vector against every element of a second input vector. The processing core also has second execution logic circuitry that includes second comparison circuitry to compare a first input value against every data element of an input vector. | 06-28-2012 |
20140052968 | SUPER MULTIPLY ADD (SUPER MADD) INSTRUCTION - A method of processing an instruction is described that includes fetching and decoding the instruction. The instruction has separate destination address, first operand source address and second operand source address components. The first operand source address identifies a location of a first mask pattern in mask register space. The second operand source address identifies a location of a second mask pattern in the mask register space. The method further includes fetching the first mask pattern from the mask register space; fetching the second mask pattern from the mask register space; merging the first and second mask patterns into a merged mask pattern; and, storing the merged mask pattern at a storage location identified by the destination address. | 02-20-2014 |
20140052969 | SUPER MULTIPLY ADD (SUPER MADD) INSTRUCTIONS WITH THREE SCALAR TERMS - A processing core is described having execution unit logic circuitry having a first register to store a first vector input operand, a second register to a store a second vector input operand and a third register to store a packed data structure containing scalar input operands a, b, c. The execution unit logic circuitry further include a multiplier to perform the operation (a*(first vector input operand))+(b*(second vector operand))+c. | 02-20-2014 |
20140095779 | PROCESSING MEMORY ACCESS INSTRUCTIONS THAT HAVE DUPLICATE MEMORY INDICES - A method of an aspect includes receiving an instruction indicating a first source packed memory indices, a second source packed data operation mask, and a destination storage location. Memory indices of the packed memory indices are compared with one another. One or more sets of duplicate memory indices are identified. Data corresponding to each set of duplicate memory indices is loaded only once. The loaded data corresponding to each set of duplicate memory indices is replicated for each of the duplicate memory indices in the set. A packed data result in the destination storage location in response to the instruction. The packed data result includes data elements from memory locations that are indicated by corresponding memory indices of the packed memory indices when not blocked by corresponding elements of the packed data operation mask. | 04-03-2014 |
20140095831 | APPARATUS AND METHOD FOR EFFICIENT GATHER AND SCATTER OPERATIONS - An apparatus and method are described for performing efficient gather operations in a pipelined processor. For example, a processor according to one embodiment of the invention comprises: gather setup logic to execute one or more gather setup operations in anticipation of one or more gather operations, the gather setup operations to determine one or more addresses of vector data elements to be gathered by the gather operations; and gather logic to execute the one or more gather operations to gather the vector data elements using the one or more addresses determined by the gather setup operations. | 04-03-2014 |
20140149651 | Providing Extended Cache Replacement State Information - In an embodiment, a processor includes a decode logic to receive and decode a first memory access instruction to store data in a cache memory with a replacement state indicator of a first level, and to send the decoded first memory access instruction to a control logic. In turn, the control logic is to store the data in a first way of a first set of the cache memory and to store the replacement state indicator of the first level in a metadata field of the first way responsive to the decoded first memory access instruction. Other embodiments are described and claimed. | 05-29-2014 |
20140164705 | PREFETCH WITH REQUEST FOR OWNERSHIP WITHOUT DATA - A method performed by a processor is described. The method includes executing an instruction. The instruction has an address as an operand. The executing of the instruction includes sending a signal to cache coherence protocol logic of the processor. In response to the signal, the cache coherence protocol logic issues a request for ownership of a cache line at the address. The cache line is not in a cache of the processor. The request for ownership also indicates that the cache line is not to be sent to the processor. | 06-12-2014 |
20140173203 | Block Memory Engine - In an embodiment, a processor is disclosed and includes a cache memory and a memory execution cluster coupled to the cache memory. The memory execution cluster includes a memory execution unit to execute instructions including non-block memory instructions, and block memory logic to execute one or more block memory operations. Other embodiments are described and claimed. | 06-19-2014 |
20140181464 | COALESCING ADJACENT GATHER/SCATTER OPERATIONS - According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location. | 06-26-2014 |
20140297991 | INSTRUCTIONS FOR STORING IN GENERAL PURPOSE REGISTERS ONE OF TWO SCALAR CONSTANTS BASED ON THE CONTENTS OF VECTOR WRITE MASKS - According to one embodiment, an occurrence of an instruction is fetched. The instruction's format specifies its only source operand from a single vector write mask register, and specifies as its destination a single general purpose register. In addition, the instruction's format includes a first field whose contents selects the single vector write mask register, and includes a second field whose contents selects the single general purpose register. The source operand is a write mask including a plurality of one bit vector write mask elements that correspond to different multi-bit data element positions within architectural vector registers. The method also includes, responsive to executing the single occurrence of the single instruction, storing data in the single general purpose register such that its contents represent either a first or second scalar constant based on whether the plurality of one bit vector write mask elements in the source operand are all zero. | 10-02-2014 |
20150052333 | Systems, Apparatuses, and Methods for Stride Pattern Gathering of Data Elements and Stride Pattern Scattering of Data Elements - Embodiments of systems, apparatuses, and methods for performing gather and scatter stride instruction in a computer processor are described. In some embodiments, the execution of a gather stride instruction causes a conditionally storage of strided data elements from memory into the destination register according to at least some of bit values of a writemask. | 02-19-2015 |
20150074354 | DEVICE, SYSTEM AND METHOD FOR USING A MASK REGISTER TO TRACK PROGRESS OF GATHERING ELEMENTS FROM MEMORY - A device, system and method for assigning values to elements in a first register, where each data field in a first register corresponds to a data element to be written into a second register, and where for each data field in the first register, a first value may indicate that the corresponding data element has not been written into the second register and a second value indicates that the corresponding data element has been written into the second register, reading the values of each of the data fields in the first register, and for each data field in the first register having the first value, gathering the corresponding data element and writing the corresponding data element into the second register, and changing the value of the data field in the first register from the first value to the second value. Other embodiments are described and claimed. | 03-12-2015 |
20160041827 | INSTRUCTIONS FOR MERGING MASK PATTERNS - A method is described that includes fetching an instruction and decoding the instruction. The method further includes fetching a first mask vector from a first mask register space location identified by the instruction. The method further includes fetching a second mask vector from a second mask register space location identified by the instruction. The method also includes executing the instruction by merging the first and second mask vectors into a single data structure and causing the single data structure to be written into a memory location identified by the instruction. | 02-11-2016 |
20160103684 | COALESCING ADJACENT GATHER/SCATTER OPERATIONS - According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location. | 04-14-2016 |
20160103786 | COALESCING ADJACENT GATHER/SCATTER OPERATIONS - According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location. | 04-14-2016 |
20160103787 | COALESCING ADJACENT GATHER/SCATTER OPERATIONS - According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location. | 04-14-2016 |
20160103788 | COALESCING ADJACENT GATHER/SCATTER OPERATIONS - According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location. | 04-14-2016 |
20160103789 | COALESCING ADJACENT GATHER/SCATTER OPERATIONS - According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location. | 04-14-2016 |
20160103790 | COALESCING ADJACENT GATHER/SCATTER OPERATIONS - According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location. | 04-14-2016 |
20160110196 | COALESCING ADJACENT GATHER/SCATTER OPERATIONS - According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location. | 04-21-2016 |
20160124749 | COALESCING ADJACENT GATHER/SCATTER OPERATIONS - According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location. | 05-05-2016 |
Patent application number | Description | Published |
20100332801 | Adaptively Handling Remote Atomic Execution - In one embodiment, a method includes receiving an instruction for decoding in a processor core and dynamically handling the instruction with one of multiple behaviors based on whether contention is predicted. If no contention is predicted, the instruction is executed in the core, and if contention is predicted data associated with the instruction is marshaled and sent to a selected remote agent for execution. Other embodiments are described and claimed. | 12-30-2010 |
20110154000 | Adaptive optimized compare-exchange operation - A technique to perform a fast compare-exchange operation is disclosed. More specifically, a machine-readable medium, processor, and system are described that implement a fast compare-exchange operation as well as a cache line mark operation that enables the fast compare-exchange operation. | 06-23-2011 |
20120254588 | SYSTEMS, APPARATUSES, AND METHODS FOR BLENDING TWO SOURCE OPERANDS INTO A SINGLE DESTINATION USING A WRITEMASK - Embodiments of systems, apparatuses, and methods for performing a blend instruction in a computer processor are described. In some embodiments, the execution of a blend instruction causes a data element-by-element selection of data elements of first and second source operands using the corresponding bit positions of a writemask as a selector between the first and second operands and storage of the selected data elements into the destination at the corresponding position in the destination. | 10-04-2012 |
20120254592 | SYSTEMS, APPARATUSES, AND METHODS FOR EXPANDING A MEMORY SOURCE INTO A DESTINATION REGISTER AND COMPRESSING A SOURCE REGISTER INTO A DESTINATION MEMORY LOCATION - Embodiments of systems, apparatuses, and methods for performing an expand and/or compress instruction in a computer processor are described. In some embodiments, the execution of an expand instruction causes the selection of elements from a source that are to be sparsely stored in a destination based on values of the writemask and store each selected data element of the source as a sparse data element into a destination location, wherein the destination locations correspond to each writemask bit position that indicates that the corresponding data element of the source is to be stored. | 10-04-2012 |
20130305020 | VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF - A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams. | 11-14-2013 |
20140149724 | VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF - A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams. | 05-29-2014 |
20140181466 | PROCESSORS HAVING FULLY-CONNECTED INTERCONNECTS SHARED BY VECTOR CONFLICT INSTRUCTIONS AND PERMUTE INSTRUCTIONS - An apparatus includes a decode unit to decode a permute instruction and a vector conflict instruction. A vector execution unit is coupled with the decode unit and includes a fully-connected interconnect. The fully-connected interconnect has at least four inputs to receive at least four corresponding data elements of at least one source vector. The fully-connected interconnect has at least four outputs. Each of the at least four inputs is coupled with each of the at least four outputs. The execution unit also includes a permute instruction execution logic coupled with the at least four outputs and operable to store a first vector result in response to the permute instruction. The execution unit also includes a vector conflict instruction execution logic coupled with the at least four outputs and operable to store a second vector result in a destination storage location in response to the vector conflict instruction. | 06-26-2014 |
Patent application number | Description | Published |
20080253497 | UPPER INTERNALS ARRANGEMENT FOR A PRESSURIZED WATER REACTOR - In a pressurized water reactor with ail of the in-core instrumentation gaining access to the core through the reactor head, each fuel assembly in which the instrumentation is introduced is aligned with an upper internals instrumentation guide-way. In the elevations above the upper internals upper support assembly, the instrumentation is protected and aligned by upper mounted instrumentation columns that are part of the instrumentation guide-way and extend from the upper support assembly towards the reactor head in hue with a corresponding head penetration. The upper mounted instrumentation columns are supported laterally at one end by an upper guide tube and at the other end by the upper support plate. | 10-16-2008 |
20090296877 | NUCLEAR REACTOR ALIGNMENT PLATE CONFIGURATION - An alignment plate that is attached to a core barrel of a pressurized water reactor and fits within slots within a top plate of a lower core shroud and upper core plate to maintain lateral alignment of the reactor internals. The alignment plate is connected to the core barrel through two vertically-spaced dowel pins that extend from the outside surface of the core barrel through a reinforcement pad and into corresponding holes in the alignment plate. Additionally, threaded fasteners are inserted around the perimeter of the reinforcement pad and into the alignment plate to further secure the alignment plate to the core barrel. A fillet weld also is deposited around the perimeter of the reinforcement pad. To accommodate thermal growth between the alignment plate and the core barrel, a gap is left above, below and at both sides of one of the dowel pins in the alignment plate holes through which the dowel pins pass. | 12-03-2009 |
20100150298 | CORE SHROUD CORNER JOINTS - A core shroud is provided, which includes a number of planar members, a number of unitary corners, and a number of subassemblies each comprising a combination of the planar members and the unitary corners. Each unitary corner comprises a unitary extrusion including a first planar portion and a second planar portion disposed perpendicularly with respect to the first planar portion. At least one of the subassemblies comprises a plurality of the unitary corners disposed side-by-side in an alternating opposing relationship. A plurality of the subassemblies can be combined to form a quarter perimeter segment of the core shroud. Four quarter perimeter segments join together to form the core shroud. | 06-17-2010 |
20120206011 | NOISE AND VIBRATION MITIGATION SYSTEM FOR NUCLEAR REACTORS EMPLOYING AN ACOUSTIC SIDE BRANCH RESONATOR - A method of designing/making an acoustic side branch resonator structured to be coupled to a standpipe of, for example, a nuclear power plant, wherein the acoustic side branch resonator includes a plurality of wire mesh elements for damping purposes. The method includes determining a resonant frequency of the standpipe, determining an active length of the acoustic side branch resonator using the resonant frequency, and determining a particular number of the wire mesh elements to be used in the acoustic side branch resonator and a pitch of each of the wire mesh elements using momentum and continuity equations of a compressible fluid. | 08-16-2012 |
20130334182 | CORE SHROUD CORNER JOINTS - A core shroud is provided, which includes a number of planar members, a number of unitary corners, and a number of subassemblies each comprising a combination of the planar members and the unitary corners. Each unitary corner comprises a unitary extrusion including a first planar portion and a second planar portion disposed perpendicularly with respect to the first planar portion. At least one of the subassemblies comprises a plurality of the unitary corners disposed side-by-side in an alternating opposing relationship. A plurality of the subassemblies can be combined to form a quarter perimeter segment of the core shroud. Four quarter perimeter segments join together to form the core shroud. | 12-19-2013 |
20150310943 | PRESSURIZED WATER REACTOR FLOW SKIRT APPARATUS - A pressurized water reactor vessel having a flow skirt formed from a perforated cylinder structure supported in the lower reactor vessel head at the outlet of the downcomer annulus, that channels the coolant flow through flow holes in the wall of the cylinder structure. The flow skirt is supported at a plurality of circumferentially spaced locations on the lower reactor vessel head that are not equally spaced or vertically aligned with the core barrel attachment points, and the flow skirt employs a unique arrangement of hole patterns that assure a substantially balanced pressure and flow of the coolant over the entire underside of the lower core support plate. | 10-29-2015 |
Patent application number | Description | Published |
20130329879 | APPARATUS AND METHODS FOR A SCALABLE COMMUNICATIONS NETWORK - A method that incorporates teachings of the subject disclosure may include, for example, transmitting a first request for an identity of a first regional name authority pointer server of a plurality of regional name authority pointer servers to a national domain name system server responsive to determining that a name authority pointer associated with a telephone number is not stored in cache memory, transmitting a second request for the name authority pointer to the first regional pointer server identified by the domain name system server, where the first regional name authority pointer server corresponds to a geographic region associated with the telephone number, and receiving the name authority pointer from the first regional name authority pointer server. Other embodiments are disclosed. | 12-12-2013 |
20140071979 | APPARATUS AND METHODS FOR A SCALABLE COMMUNICATIONS NETWORK - A method that incorporates teachings of the subject disclosure may include, for example, transmitting a first request for a name authority pointer to a first in-region name server of a plurality of in-region name servers of a first geographic region responsive to determining that a telephone number of a call is located in the first geographic region, transmitting a second request for the name authority pointer to an out-of-region name server associated with a second geographic region responsive to determining that the telephone number is located in the second geographic region, and receiving the name authority pointer from at least one of the in-region name server or the out-of-region server. Other embodiments are disclosed. | 03-13-2014 |
20140146813 | METHOD AND APPARATUS FOR PROVISIONING A SCALABLE COMMUNICATIONS NETWORK - A method that incorporates teachings of the subject disclosure may include, for example, determining at a first directory server of a first regional call processing system whether a new name authority pointer associated with a telephone number is within a first geographic region of the first regional call processing system, transmitting the new name authority pointer to a first name server of the first regional call processing system for provisioning the name authority pointer to the first name server responsive to determining that the telephone number is located within the first geographic region, and transmitting the new name authority pointer to a second directory server for provisioning the new name authority pointer to a second name server of a second regional call processing system responsive to determining that the telephone number is not located within the first geographic region. Other embodiments are disclosed. | 05-29-2014 |
20150098314 | METHOD AND APPARATUS FOR PROCESSING COMMUNICATION REQUESTS - A system that incorporates the subject disclosure may perform, for example, operations including receiving a request from a communication device to initiate a communication session, obtaining a first name authority pointer record that replaces a second name authority pointer record responsive to an undesirable fault level in a voice over long term evolution network, obtaining the second name authority pointer record responsive to determining that there is no fault or a tolerable level of faults in the voice over long term evolution network, and initiating the communication session according to one of the first name authority pointer record or the second name authority pointer record obtained by the system. The first name authority pointer record can include instructions for initiating the communication session utilizing a circuit-switched communication network, and the second name authority pointer record can include instructions for initiating the communication session utilizing the voice over long term evolution network. Other embodiments are disclosed. | 04-09-2015 |
20150098315 | METHOD AND APPARATUS FOR INITIATING COMMUNICATION SESSIONS - An aspect of the subject disclosure may include, for example, receiving a request from a communication device to initiate a communication session in a packet-switched network, obtaining a first name authority pointer record responsive to determining that there is an undesirable operational state in the packet-switched network, wherein the first name authority pointer record comprises a null record, obtaining a second name authority pointer record responsive to determining that there is a desirable operation state in the packet-switched network, wherein the second name authority pointer record comprises a record, and initiating the communication session according to one of the first name authority pointer record or the second name authority pointer record. Other embodiments are disclosed. | 04-09-2015 |
20150200908 | METHOD AND APPARATUS FOR PROVISIONING A SCALABLE COMMUNICATIONS NETWORK - A method that incorporates teachings of the subject disclosure may include, for example, determining at a first directory server of a first regional call processing system whether a new name authority pointer associated with a telephone number is within a first geographic region of the first regional call processing system, transmitting the new name authority pointer to a first name server of the first regional call processing system for provisioning the name authority pointer to the first name server responsive to determining that the telephone number is located within the first geographic region, and transmitting the new name authority pointer to a second directory server for provisioning the new name authority pointer to a second name server of a second regional call processing system responsive to determining that the telephone number is not located within the first geographic region. Other embodiments are disclosed. | 07-16-2015 |
20160119385 | METHOD AND APPARATUS FOR INITIATING COMMUNICATION SESSIONS - An aspect of the subject disclosure may include, for example, receiving a request from a communication device to initiate a communication session in a packet-switched network, obtaining a first name authority pointer record responsive to determining that there is an undesirable operational state in the packet-switched network, wherein the first name authority pointer record comprises a null record, obtaining a second name authority pointer record responsive to determining that there is a desirable operational state in the packet-switched network, wherein the second name authority pointer record comprises a record, and initiating the communication session according to one of the first name authority pointer record or the second name authority pointer record. Other embodiments are disclosed. | 04-28-2016 |
Patent application number | Description | Published |
20090130173 | BONE MATRIX COMPOSITIONS AND METHODS - Osteoinductive compositions and implants having increased biological activities, and methods for their production, are provided. The biological activities that may be increased include, but are not limited to, bone forming; bone healing; osteoinductive activity, osteogenic activity, chondrogenic activity, wound healing activity, neurogenic activity, contraction-inducing activity, mitosisinducing activity, differentiation-inducing activity, chemotactic activity, angiogenic or vasculogenic activity, and exocytosis or endocytosis-inducing activity. In one embodiment, a method for producing an osteoinductive composition comprises providing partially demineralized bone, treating the partially demineralized bone to disrupt the collagen structure of the bone, and optionally providing a tissue-derived extract and adding the tissue-derived extract to the partially demineralized bone. In another embodiment, an implantable osteoinductive and osteoconductive composition comprises partially demineralized bone, wherein the collagen structure of the bone has been disrupted, and, optionally, a tissue-derived extract. | 05-21-2009 |
20090155378 | OSTEOINDUCTIVE DEMINERALIZED CANCELLOUS BONE - An osteoinductive demineralized bone matrix, corresponding osteoimplants, and methods for making the osteoinductive demineralized bone matrix are disclosed. The osteoinductive demineralized bone matrix may be prepared by providing demineralized bone and altering the collagenous structure of the bone. The osteoinductive demineralized bone matrix may also be prepared by providing demineralized bone and compacting the bone, for example via mechanical compaction, grinding into a particulate, or treatment with a chemical. Additives such as growth factors or bioactive agents may be added to the osteoinductive demineralized bone matrix. The osteoinductive demineralized bone matrix may form an osteogenic osteoimplant. The osteoimplant, when implanted in a mammalian body, may induce at the locus of the implant the full developmental cascade of endochondral bone formation including vascularization, mineralization, and bone marrow differentiation. The osteoinductive demineralized bone matrix may also be used as a delivery device to administer bioactive agents. | 06-18-2009 |
20090157087 | DELIVERY SYSTEM ATTACHMENT - A covering for delivering a substance or material to a surgical site is provided. The covering, with substance provided therein, may be referred to as a delivery system. Generally, the covering may be a single or multi-compartment structure capable of at least partially retaining a substance provided therein until the covering is placed at a surgical site. Upon placement, the covering may facilitate transfer of the substance or surrounding materials. For example, the substance may be released (actively or passively) to the surgical site. The covering may participate in, control, or otherwise adjust, the release of the substance. | 06-18-2009 |
20090192474 | DELIVERY SYSTEM - A covering for delivering a substance or material to a surgical site is provided. The covering, with substance provided therein, may be referred to as a delivery system. Generally, the covering may be a single or multi-compartment structure capable of at least partially retaining a substance provided therein until the covering is placed at a surgical site. Upon placement, the covering may facilitate transfer of the substance or surrounding materials. For example, the substance may be released (actively or passively) to the surgical site. The covering may participate in, control, or otherwise adjust, the release of the substance. | 07-30-2009 |
20090220605 | BONE MATRIX COMPOSITIONS HAVING NANOSCALE TEXTURED SURFACES - Bone matrix compositions having nanoscale textured surfaces and methods for their production are provided. In some embodiments, bone matrix is prepared for implantation and retains nanoscale textured surfaces. In other embodiments, nanostructures are imparted to bone matrix wherein collagen fibrils on the surface of the bone matrix have been compromised, thus imparting a nanoscale textured surface to the bone matrix. Generally, these methods may be applied to mineralized or demineralized bone including partially or surface demineralized bone. | 09-03-2009 |
20090234277 | DELIVERY SYSTEM - A covering for delivering a substance or material to a surgical site is provided. The covering, with substance provided therein, may be referred to as a delivery system. Generally, the covering may be a single or multi-compartment structure capable of at least partially retaining a substance provided therein until the covering is placed at a surgical site. Upon placement, the covering may facilitate transfer of the substance or surrounding materials. For example, the substance may be released (actively or passively) to the surgical site. The covering may participate in, control, or otherwise adjust, the release of the substance. | 09-17-2009 |
20110054408 | DELIVERY SYSTEMS, DEVICES, TOOLS, AND METHODS OF USE - A covering for delivering a substance or material to a surgical site is provided. The covering, with substance provided therein, may be referred to as a delivery system. Generally, the covering may be a single or multi-compartment structure capable of at least partially retaining a substance provided therein until the covering is placed at a surgical site. Upon placement, the covering may facilitate transfer of the substance or surrounding materials. For example, the substance may be released (actively or passively) to the surgical site. The covering may participate in, control, or otherwise adjust the release of the substance. In various embodiments, the covering is suitable for a variety of procedure specific uses. Implantation tools may be provided for placing the covering at a surgical site. Kits may be provided including variously sized or shaped coverings and one or more tools for use in placing the covering. | 03-03-2011 |
20130013071 | Osteoimplants and Methods for their Manufacture - An osteoimplant is made up of a coherent aggregate of elongate bone particles. | 01-10-2013 |
20130136777 | Bone Matrix Compositions and Methods - Osteoinductive compositions and implants having increased biological activities, and methods for their production, are provided. The biological activities that may be increased include, but are not limited to, bone forming; bone healing; osteoinductive activity, osteogenic activity, chondrogenic activity, wound healing activity, neurogenic activity, contraction-inducing activity, mitosis-inducing activity, differentiation-inducing activity, chemotactic activity, angiogenic or vasculogenic activity, and exocytosis or endocytosis-inducing activity. In one embodiment, a method for producing an osteoinductive composition comprises providing partially demineralized bone, treating the partially demineralized bone to disrupt the collagen structure of the bone, and optionally providing a tissue-derived extract and adding the tissue-derived extract to the partially demineralized bone. In another embodiment, an implantable osteoinductive and osteoconductive composition comprises partially demineralized bone, wherein the collagen structure of the bone has been disrupted, and, optionally, a tissue-derived extract. | 05-30-2013 |
20140065239 | OSTEOINDUCTIVE DEMINERALIZED CANCELLOUS BONE - An osteoinductive demineralized bone matrix, corresponding osteoimplants, and methods for making the osteoinductive demineralized bone matrix are disclosed. The osteoinductive demineralized bone matrix may be prepared by providing demineralized bone and altering the collagenous structure of the bone. The osteoinductive demineralized bone matrix may also be prepared by providing demineralized bone and compacting the bone, for example via mechanical compaction, grinding into a particulate, or treatment with a chemical. Additives such as growth factors or bioactive agents may be added to the osteoinductive demineralized bone matrix. The osteoinductive demineralized bone matrix may form an osteogenic osteoimplant. The osteoimplant, when implanted in a mammalian body, may induce at the locus of the implant the full developmental cascade of endochondral bone formation including vascularization, mineralization, and bone marrow differentiation. The osteoinductive demineralized bone matrix may also be used as a delivery device to administer bioactive agents. | 03-06-2014 |
20140255506 | OSTEOINDUCTIVE DEMINERALIZED CANCELLOUS BONE - An osteoinductive demineralized bone matrix, corresponding osteoimplants, and methods for making the osteoinductive demineralized bone matrix are disclosed. The osteoinductive demineralized bone matrix may be prepared by providing demineralized bone and altering the collagenous structure of the bone. The osteoinductive demineralized bone matrix may also be prepared by providing demineralized bone and compacting the bone, for example via mechanical compaction, grinding into a particulate, or treatment with a chemical. Additives such as growth factors or bioactive agents may be added to the osteoinductive demineralized bone matrix. The osteoinductive demineralized bone matrix may form an osteogenic osteoimplant. The osteoimplant, when implanted in a mammalian body, may induce at the locus of the implant the full developmental cascade of endochondral bone formation including vascularization, mineralization, and bone marrow differentiation. The osteoinductive demineralized bone matrix may also be used as a delivery device to administer bioactive agents. | 09-11-2014 |
20140302112 | BONE MATRIX COMPOSITIONS AND METHODS - Osteoinductive compositions and implants having increased biological activities, and methods for their production, are provided. The biological activities that may be increased include, but are not limited to, bone forming; bone healing; osteoinductive activity, osteogenic activity, chondrogenic activity, wound healing activity, neurogenic activity, contraction-inducing activity, mitosis-inducing activity, differentiation-inducing activity, chemotactic activity, angiogenic or vasculogenic activity, and exocytosis or endocytosis-inducing activity. In one embodiment, a method for producing an osteoinductive composition comprises providing partially demineralized bone, treating the partially demineralized bone to disrupt the collagen structure of the bone. In another embodiment, an implantable osteoinductive and osteoconductive composition comprises partially demineralized bone, wherein the collagen structure of the bone has been disrupted, and, optionally, a tissue-derived extract. | 10-09-2014 |
20150258245 | METHOD OF DELIPIDATION AND/OR TERMINAL STERILIZATION FOR BONE MATERIAL - Methods for delipidation, viral inactivation and terminal sterilization are provided for bone grafting material. The methods include contacting bone material with an amount of supercritical fluid effective to remove at least lipids and at least contaminants from the bone material, thereby obtaining a terminally sterilized and delipidated bone material. In various embodiments, the substantially terminally sterilized and delipidated bone material is 99.0%, 99.5% or 99.9% free of lipids and contaminants. Contaminants that are removed from bone material by terminal sterilization with supercritical fluid include infectious organisms, such as bacteria, viruses, protozoa, parasites, fungi and mold. Bone material or bone compositions that can be treated with critical or supercritical fluids comprise mineralized or demineralized bone particles, mineralized or demineralized bone matrix, partially demineralized bone matrix or combinations thereof. | 09-17-2015 |