Patent application number | Description | Published |
20080253190 | Non-volatile memory device and method of operating the same - The present invention is directed to a non-volatile memory device and a method of operating the same. The non-volatile memory device includes a first transistor connected to an nth bitline and a second transistor connected to an (n+1)th bitline. The first transistor and the second transistor are serially coupled between the nth bitline and the (n+1)th bitline. The non-volatile memory device may include a 2-transistor 1-bit unit cell where a drain region and a source region of a memory cell have the same or similar structure. Since a cell array of a non-volatile memory device according to the invention may include a 2-transistor 2-bit unit cell, storage capacity of the non-volatile memory device may be doubled. | 10-16-2008 |
20090059664 | Electrically Erasable Programmable Read-Only Memory (EEPROM) Cell and Methods for Forming and Reading the Same - In a method of reading data in an EEPROM cell, a bit line voltage for reading is applied to the EEPROM cell including a memory transistor and a selection transistor. A first voltage is applied to a sense line of the memory transistor. A second voltage greater than the first voltage is applied to a word line of the selection transistor. A current passing through the EEPROM cell is compared with a predetermined reference current to read the data stored in the EEPROM cell. An on-cell current of the EEPROM cell may be increased in an erased state and the data in the cell may be readily discriminated. | 03-05-2009 |
20090065845 | Embedded semiconductor device and method of manufacturing an embedded semiconductor device - Provided are an embedded semiconductor device and a method of manufacturing an embedded semiconductor device. In a method of manufacturing the embedded semiconductor device, layers of at least one cell gate stack may be formed in a cell area of a substrate. A logic gate structure may be formed in a logic area of the substrate. First source/drain regions may be formed adjacent to the logic gate structure, and metal silicide patterns may be formed on the logic gate structure and the first source/drain regions. At least one hard mask may be formed on the layers of the at least one cell gate stack, and a blocking pattern may be formed to cover the logic gate structure and the first source/drain regions. The at least one cell gate stack may be formed in the cell area by etching the layers of the at least one cell gate stack using the at least one hard mask as an etching mask. A memory transistor in the cell area may have an increased integration degree and a logic transistor in the logic area may have an increased response speed and a decreased resistance. | 03-12-2009 |
20090189210 | Semiconductor Flash Memory Device and Method of Fabricating the Same - A semiconductor flash memory device. The flash memory device includes a floating gate electrode disposed in a recess having slanted sides in a semiconductor substrate. A gate insulation film is interposed between the floating gate electrode and the semiconductor substrate. A control gate electrode is disposed over the floating gate electrode. The floating gate electrode includes projections adjacent to the slanted sides of the recess. | 07-30-2009 |
20090239349 | NONVOLATILE MEMORY DEVICES AND METHODS OF FORMING THE SAME - In a nonvolatile memory device and a method of fabricating the same, a device isolation layer is formed defining an active region in a semiconductor substrate. A gate insulation layer and a first conductive layer are formed on the semiconductor substrate. A pair of stack patterns are formed, each having a intergate dielectric layer pattern and a second conductive layer pattern on the first conductive layer. A mask pattern is formed on the first conductive layer pattern between the stack patterns, the mask pattern being spaced apart from each of the stack patterns. The first conductive layer is patterned using the stack patterns and the mask patterns as an etching mask. Impurity ions are implanted into the active region to form a pair of nonvolatile memory transistors and a select transistor. The resulting nonvolatile memory device includes a memory cell unit that includes the pair of nonvolatile memory transistors and the select transistor. | 09-24-2009 |
20100059888 | Mask ROM and method of fabricating the same - A mask read-only memory (ROM) includes a dielectric layer formed on a substrate and a plurality of first conductive lines formed on the dielectric layer. A plurality of diodes are formed in the first conductive lines, and a plurality of final vias are formed for a first set of the diodes each representing a first type of memory cell, with no final via being formed for a second set of diodes each representing a second type of memory cell. Each of a plurality of second conductive lines is formed over a column of the diodes. | 03-11-2010 |
20100265765 | Non-volatile semiconductor memory device in which program disturb is reduced and method of programming the same - A non-volatile semiconductor memory device capable of reducing program disturb and a method of programming the same are provided. A bit line connected to a non-selected memory cell in the same block as a selected memory cell enters a floating state by inactivating a bit line selection switch, so that voltage levels of an first conductivity type channel and a source/drain terminal formed in a pocket second conductivity type well below a memory transistor have an intermediate level of a voltage level of a selection line and the pocket P type well. Therefore, program disturb caused by FN tunneling and junction hot electrons can be inhibited. | 10-21-2010 |
20100304540 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - There is provided a semiconductor device and a method of forming the same. The semiconductor device includes a memory device and a self-aligned selection device. A floating junction is formed between the self-aligned selection device and the memory device. | 12-02-2010 |
20110038210 | Electrically Erasable Programmable Read-Only Memory (EEPROM) Cell and Methods for Forming and Reading the Same - In a method of reading data in an EEPROM cell, a bit line voltage for reading is applied to the EEPROM cell including a memory transistor and a selection transistor. A first voltage is applied to a sense line of the memory transistor. A second voltage greater than the first voltage is applied to a word line of the selection transistor. A current passing through the EEPROM cell is compared with a predetermined reference current to read the data stored in the EEPROM cell. An on-cell current of the EEPROM cell may be increased in an erased state and the data in the cell may be readily discriminated. | 02-17-2011 |
20120044772 | NON-VOLATILE MEMORY DEVICE, SYSTEM, AND CELL ARRAY - A non-volatile memory cell array, comprising sector selection transistors controlled by a voltage applied to sector selection lines, first through fourth memory cells connected in series to the sector selection transistors, a first common source line connected between the first memory cell and the second memory cell, and a second common source line connected between the third memory cell and the fourth memory cell and separated from the first common source line. A first voltage is applied to the first common source line, and a second voltage different from the first voltage is applied to the second common source line. | 02-23-2012 |
20120181607 | SEMICONDUCTOR DEVICES HAVING ASYMMETRIC DOPED REGIONS AND METHODS OF FABRICATING THE SAME - A semiconductor device includes an active region in a substrate, first to third gate structures crossing the active region and sequentially arranged parallel to each other, a first doped region in the active region between the first and second gate structures and having a first horizontal width and a first depth, and a second doped region in the active region between the second and third gate structures and having a second horizontal width and a second depth. The second horizontal width is larger than the first horizontal width and the second depth is shallower than the first depth. A distance between the first and second gate structures adjacent to each other is smaller than that between the second and third gate structures adjacent to each other. Related fabrication methods are also described. | 07-19-2012 |
20140043896 | METHOD OF PREVENTING PROGRAM-DISTURBANCES FOR A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A method of preventing program-disturbances for a non-volatile semiconductor memory device having a plurality of memory cells of which each includes a selection transistor and a memory transistor coupled in series between a bit-line and a common source-line is provided. First non-selected memory cells that share a first selection-line with a selected memory cell, and second non-selected memory cells that do not share the first selection-line with the selected memory cell are determined when the selected memory cell is selected to be programmed among the memory cells. A negative voltage is applied to second selection-lines that are coupled to the second non-selected memory cells when the selected memory cell is programmed by applying a positive voltage to the first selection-line that is coupled to the selected memory cell. | 02-13-2014 |