Patent application number | Description | Published |
20080229321 | QUALITY OF SERVICE SCHEDULING FOR SIMULTANEOUS MULTI-THREADED PROCESSORS - A method and system for providing quality of service guarantees for simultaneous multithreaded processors are disclosed. Hardware and operating system communicate with one another providing information relating to thread attributes for threads executing on processing elements. The operating system controls scheduling of the threads based at least partly on the information communicated and provides quality of service guarantees. | 09-18-2008 |
20110126200 | Scheduling for functional units on simultaneous multi-threaded processors - A method and system for scheduling threads on simultaneous multithreaded processors are disclosed. Hardware and operating system communicate with one another providing information relating to thread attributes for threads executing on processing elements. The operating system determines thread scheduling based on the information. | 05-26-2011 |
20130263121 | METHOD TO EMBED A LIGHT-WEIGHT KERNEL IN A FULL-WEIGHT KERNEL TO PROVIDE A HETEROGENEOUS EXECUTION ENVIRONMENT - Enabling a Light-Weight Kernel (LWK) to run in a virtualized environment on a Full-Weight Kernel (FWK), in one aspect, may include replacing a FWK loader, e.g., FWK's dynamic library loader or linker, with a LWK library on a first computing entity for an application allocated to run on one or more second computing entities. The LWK library may be enabled to initialize the one or more second computing entities and associated memory allocated to run the application under the LWK library. The LWK library may be enabled to manage the one or more second computing entities and said associated memory and resources needed by the application. | 10-03-2013 |
20130263157 | METHOD TO UTILIZE CORES IN DIFFERENT OPERATING SYSTEM PARTITIONS - A system call utility may be provided on a first operating system managing a first hardware computing entity. The system call utility may take as an argument a pointer to a computer code a second operating system established to run on the first hardware computing entity. The first operating system is enabled to execute the computer code natively on the first hardware computing entity, and return a result of the computer code executed on the first hardware computing entity to the second operating system. | 10-03-2013 |
20140143570 | THREAD CONSOLIDATION IN PROCESSOR CORES - According to one embodiment, a method for thread consolidation is provided for a system that includes an operating system and a multi-core processing chip in communication with an accelerator chip. The method includes running an application having software threads on the operating system, mapping the software threads to physical cores in the multi-core processing chip, identifying one or more idle hardware threads in the multi-core processing chip and identifying one or more idle accelerator units in the accelerator chip. The method also includes executing the software threads on the physical cores and the accelerator unit. The method also includes the controller module consolidating the software threads executing on the physical cores, resulting in one or more idle physical cores and a consolidated physical core. The method also includes the controller module activating a power savings mode for the one or more idle physical cores. | 05-22-2014 |
20140143783 | THREAD CONSOLIDATION IN PROCESSOR CORES - According to one embodiment, a method for thread consolidation is provided for a system that includes an operating system and a multi-core processing chip in communication with an accelerator chip. The method includes running an application having software threads on the operating system, mapping the software threads to physical cores in the multi-core processing chip, identifying one or more idle hardware threads in the multi-core processing chip and identifying one or more idle accelerator units in the accelerator chip. The method also includes executing the software threads on the physical cores and the accelerator unit. The method also includes the controller module consolidating the software threads executing on the physical cores, resulting in one or more idle physical cores and a consolidated physical core. The method also includes the controller module activating a power savings mode for the one or more idle physical cores. | 05-22-2014 |
20150074367 | METHOD AND APPARATUS FOR FAULTY MEMORY UTILIZATION - A method for faulty memory utilization in a memory system includes: obtaining information regarding memory health status of at least one memory page in the memory system; determining an error tolerance of the memory page when the information regarding memory health status indicates that a failure is predicted to occur in an area of the memory system affecting the memory page; initiating a migration of data stored in the memory page when it is determined that the data stored in the memory page is non-error-tolerant; notifying at least one application regarding a predicted operating system failure and/or a predicted application failure when it is determined that data stored in the memory page is non-error-tolerant and cannot be migrated; and notifying at least one application regarding the memory failure predicted to occur when it is determined that data stored in the memory page is error-tolerant. | 03-12-2015 |
20150074469 | METHODS, APPARATUS AND SYSTEM FOR NOTIFICATION OF PREDICTABLE MEMORY FAILURE - A method for providing notification of a predictable memory failure includes the steps of: obtaining information regarding at least one condition associated with a memory; calculating a memory failure probability as a function of the obtained information; calculating a failure probability threshold; and generating a signal when the memory failure probability exceeds the failure probability threshold, the signal being indicative of a predicted future memory failure. | 03-12-2015 |
Patent application number | Description | Published |
20130030314 | DEVICES, SYSTEMS AND METHODS TO PERFORM ARRHYTHMIA DISCRIMINATION BASED ON THE ATRIAL AND VENTRICULAR ACTIVATION TIMES - Described herein are implantable systems and devices, and methods for use therewith, that can be used to perform arrhythmia discrimination based on activation times. A plurality of different sensing vectors are used to obtain a plurality of IEGMs that collectively enable electrical activations to be detected in the left atrial (LA) chamber, the right atrial (RA) chamber, and at least one ventricular chamber of a patient's heart. For each of a plurality of cardiac cycles, there is a determination, based on the plurality of obtained IEGMs, of an LA activation time, an RA activation time, and a ventricular activation time. Arrhythmia discrimination is then performed based on the determined activation times. | 01-31-2013 |
20130030315 | DEVICES, SYSTEMS AND METHODS TO MONITOR AND TREAT HEART FAILURE (HF) - Described herein are implantable systems and devices, and methods for use therewith, that can be used to monitor and treat heart failure (HF). Such implantable systems preferably includes a lead having at least two electrodes implantable in a patient's left ventricular (LV) chamber. A plurality of different sensing vectors are used to obtain a plurality of IEGMs each of which is indicative of an evoked response at a corresponding different region of the LV chamber. For each of the IEGMs, there is a determination of one or more evoked response metrics indicative of a localized cardiac function at the corresponding region of the LV chamber. The evoke response metrics can be, e.g., paced depolarization integral (PDI) and/or maximum upward slope of an R-wave, but are not limited thereto. The patient's HF condition is monitored based on the localized cardiac function at the plurality of different regions of the LV chamber as determined based on the one or more evoked response metrics determined for each of the IEGMs. | 01-31-2013 |