Hwang, Icheon-Si
Chang Youn Hwang, Icheon-Si KR
Patent application number | Description | Published |
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20100320605 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the semiconductor memory device. A contact plug is formed by wet etching. An aspect ratio of SAC is decreased and SAC fail is reduced so that a process margin is secured. The semiconductor device includes a semiconductor substrate comprising an active region and a device isolation layer defining the active region, a conductive pattern formed on the semiconductor substrate, and a nitride layer formed on the semiconductor substrate perpendicularly to the conductive pattern. | 12-23-2010 |
20110260226 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a gate formed over an active region of a semiconductor substrate, a first spacer formed at a sidewall of the gate, a first contact plug formed at a lower sidewall of the first spacer being coupled to the active region, a second spacer formed at a sidewall of the first spacer over the first contact plug, and a second contact plug formed over the first contact plug. | 10-27-2011 |
20120001333 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the semiconductor memory device. A contact plug is formed by wet etching. An aspect ratio of SAC is decreased and SAC fail is reduced so that a process margin is secured. The semiconductor device includes a semiconductor substrate comprising an active region and a device isolation layer defining the active region, a conductive pattern formed on the semiconductor substrate, and a nitride layer formed on the semiconductor substrate perpendicularly to the conductive pattern. | 01-05-2012 |
Hye-Rin Hwang, Icheon-Si KR
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20150339023 | DISPLAY DEVICE WITH WINDOW - A display device with a window includes a display panel configured to detect touch and to display an image, a back-facing photographing part configured to photograph a background that includes a space behind the display panel, and a panel driver configured to display a background image photographed by the back-facing photographing part on the display panel and to magnify or demagnify the background image by a touch gesture performed on the display panel so as to display the magnified or demagnified image on the display panel. | 11-26-2015 |
In Chul Hwang, Icheon-Si KR
Patent application number | Description | Published |
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20130037942 | SEMICONDUCTOR CHIPS HAVING A DUAL-LAYERED STRUCTURE, PACKAGES HAVING THE SAME, AND METHODS OF FABRICATING THE SEMICONDUCTOR CHIPS AND THE PACKAGES - Dual-layered structural semiconductor chips are provided. The semiconductor chip includes a first semiconductor chip and a second semiconductor chip bonded to the first semiconductor chip. The first semiconductor chip includes a first substrate having a first bottom surface. The second semiconductor chip includes a second substrate having a second bottom surface. The first bottom surface directly contacts the second bottom surface. The related packages and the related methods are also provided. | 02-14-2013 |
20130270694 | SUBSTRATES HAVING BUMPS WITH HOLES, SEMICONDUCTOR CHIPS HAVING BUMPS WITH HOLES, SEMICONDUCTOR PACKAGES FORMED USING THE SAME, AND METHODS OF FABRICATING THE SAME - Substrates and semiconductor chips are provided. The substrate or the semiconductor chip includes a body and a substantially pillar-shaped bump disposed on a first surface of the body. The pillar-shaped bump has a hole penetrating a portion thereof. Related semiconductor packages are also provided. Further, related methods are provided. | 10-17-2013 |
20150249075 | SEMICONDUCTOR CHIPS HAVING A DUAL-LAYERED STRUCTURE, PACKAGES HAVING THE SAME, AND METHODS OF FABRICATING THE SEMICONDUCTOR CHIPS AND THE PACKAGES - Dual-layered structural semiconductor chips are provided. The semiconductor chip includes a first semiconductor chip and a second semiconductor chip bonded to the first semiconductor chip. The first semiconductor chip includes a first substrate having a first bottom surface. The second semiconductor chip includes a second substrate having a second bottom surface. The first bottom surface directly contacts the second bottom surface. The related packages and the related methods are also provided. | 09-03-2015 |
Jeong Tae Hwang, Icheon-Si KR
Patent application number | Description | Published |
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20120081100 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a comparison voltage generation unit configured to generate a plurality of different comparison voltages, a reference voltage generation unit configured to receive a generation code from an external system, select one of the plurality of the different comparison voltages according to the generation code, and generate a reference voltage, and a reference voltage determination unit configured to receive the generation code and an expected reference voltage from the external system, check whether a level of the expected reference voltage is in a target range, and output a check result to the external system. | 04-05-2012 |
20120087200 | INTERNAL COLUMN ADDRESS GENERATING CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes first and second bank groups and an internal column address generating circuit. Each of the first and second bank groups includes at least one bank. The internal column address generating circuit converts a column address into a first internal column address and outputs the first internal column address through a first transmission line in response to a bank address if a read operation or a write operation is performed on a bank of the first bank group. Also, the internal column address generating circuit converts the column address into a second internal column address and outputs the second internal column address through a second transmission line in response to the bank address if a read operation or a write operation is performed on a bank of the second bank group. | 04-12-2012 |
Jin Ha Hwang, Icheon-Si KR
Patent application number | Description | Published |
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20160072487 | BUFFER CIRCUIT AND SYSTEM HAVING THE SAME - A buffer circuit includes a power supply voltage detection block which may detect a voltage level of a power supply voltage, a bias generation block which may generate a constant bias signal and a plurality of enable bias signals based on the detection result of the power supply voltage, and an input buffer which may amplify an input signal in response to the constant bias signal and the plurality of enable bias signals. | 03-10-2016 |
Kyo Seon Hwang, Icheon-Si KR
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20110212511 | SYSTEM FOR DETECTING BIOMOLECULE WITH HIGH SENSITIVITY USING MICRO-CANTILEVER - Provided is a protein detection system using a micro-cantilever and based on immune responses, wherein the micro-cantilever shows significantly improved sensitivity to allow detection of a trace amount of biomolecule. To the micro-cantilever, sandwich immunoassay is applied, and the sandwich immunoassay uses a polyclonal antibody or silica nanoparticles having a monoclonal antibody bound thereto, so that variations in the output signals of the cantilever are amplified and the detection sensitivity is significantly improved. The system enables detection of disease specific antigen at several femtomolar levels, and makes it possible to detect a trace amount of protein related to diseases, particularly to cancers, with ease. | 09-01-2011 |
Sung Min Hwang, Icheon-Si KR
Patent application number | Description | Published |
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20110159681 | Nonvolatile Memory Device and Method of Manufacturing the Same - A method of manufacturing a nonvolatile memory device includes forming a tunnel insulating layer over a semiconductor substrate, forming tunnel insulating patterns to expose portions of the semiconductor substrate by removing portions of the tunnel insulating layer formed over isolation regions of the semiconductor substrate, forming a first conductive layer of single crystalline material over the tunnel insulating patterns and exposed portions of the semiconductor substrate, and forming a second conductive layer over the first conductive layer. | 06-30-2011 |
20120199938 | Semiconductor Memory Device and Method of Manufacturing the same - A semiconductor memory device includes a semiconductor substrate defining active regions partitioned by an isolation region, conductive lines spaced apart from each other and crossing the active regions over the semiconductor substrate, a thin film pattern formed on a top portion of the conductive lines having opening portions exposing part of the conductive lines in a width wider than a width of the conductive lines, an insulating layer filling the opening portions and formed over the thin film pattern, and an air gap formed between the conductive lines below the insulating layer and the thin film pattern. | 08-09-2012 |
20140154866 | Method of Forming a Semiconductor Memory Device - A semiconductor memory device includes a semiconductor substrate defining active regions partitioned by an isolation region, conductive lines spaced apart from each other and crossing the active regions over the semiconductor substrate, a thin film pattern formed on a top portion of the conductive lines having opening portions exposing part of the conductive lines in a width wider than a width of the conductive lines, an insulating layer filling the opening portions and formed over the thin film pattern, and an air gap formed between the conductive lines below the insulating layer and the thin film pattern. | 06-05-2014 |
Sun Hwan Hwang, Icheon-Si KR
Patent application number | Description | Published |
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20090163013 | Method for Forming Gate of Non-Volatile Memory Device - Provided is a method for forming a gate of a non-volatile memory device. A tunneling layer, a charge trapping layer, a blocking layer, and a control gate layer are formed on a semiconductor substrate. A hard mask is formed on the control gate layer. The hard mask defines a region on which a gate is formed. A gate pattern is formed by etching the control gate layer, the blocking layer, the charge trapping layer, and the tunneling layer. A damage compensation layer on a side of the gate pattern is formed using ultra low pressure plasma of a pressure range from approximately 1 mT to approximately 100 mT. | 06-25-2009 |
Sun Kak Hwang, Icheon-Si KR
Patent application number | Description | Published |
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20100311232 | Method of Manufacturing Nonvolatile Memory Device - A method of manufacturing a nonvolatile memory device comprises providing a semiconductor substrate defining active regions and isolation regions with a gate insulating layer and a floating gate formed over each active region and isolation layer formed in the respective isolation regions, forming a dielectric layer on a surface of the isolation layers and the floating gates, forming a polysilicon layer over the dielectric layer through a polysilicon deposition process using a nitrogen source gas, a silicon source gas, and an impurity doping gas, and patterning the polysilicon layer to form a control gate. | 12-09-2010 |
Sun Young Hwang, Icheon-Si KR
Patent application number | Description | Published |
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20120275247 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR REPAIRING THE SAME - A semiconductor memory device includes a latch address generation unit configured to latch row addresses to generate first and second latch addresses when at least one of memory cells coupled to sub word lines is faulty, wherein the first and second latch addresses select different main word lines, and a repair unit configured to perform a repair operation on memory cells coupled to the main word lines selected by the first and second latch addresses. | 11-01-2012 |
20140368261 | SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME - Semiconductor systems are provided. The semiconductor system includes a controller and a semiconductor device. The controller generates a power voltage signal. The semiconductor device generates a power-up signal in response to the power voltage signal, generates a first selection pulse, a second selection pulse and an initialization pulse signal, generates a first fuse signal for controlling an internal operation according to a cut state of a first fuse, and generates a second fuse signal for controlling the internal operation according to a cut state of a second fuse. | 12-18-2014 |
Tae Jin Hwang, Icheon-Si KR
Patent application number | Description | Published |
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20140003482 | RECEIVER CIRCUIT | 01-02-2014 |
20150229300 | RECEIVER CIRCUIT - A receiver circuit includes a first amplification unit, a second amplification unit, a first equalizing unit, and a second equalizing unit. The first amplification unit is configured to differentially amplify an input signal and a reference signal and generate a positive intermediate output signal and a negative intermediate output signal. The second amplification unit is configured to receive the positive intermediate output signal as a positive input signal and the negative intermediate signal as a negative input signal, differentially amplify the positive and negative input signals and generate a positive output signal and a negative output signal. The first equalizing unit is configured to control the level of the negative intermediate output signal in response to the positive output signal. The second equalizing unit is configured to control the level of the positive intermediate output signal in response to the negative output signal | 08-13-2015 |
Won Seok Hwang, Icheon-Si KR
Patent application number | Description | Published |
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20120299758 | AMPLIFYING CIRCUIT AND ANALOG DIGITAL CONVERSION CIRCUIT WITH THE SAME - An analog to digital converting device includes a first digital conversion (ADC) circuit configured to convert an inputted analog signal into a first digital signal, a first multiplying digital to analog converting (MDAC) circuit configured to amplify a difference between a first converted signal and the inputted analog signal, a second ADC circuit configured to convert an output of the first MDAC circuit into a second digital signal, a second MDAC circuit configured to amplify difference between a second converted signal converted from the second digital signal and the output of the first MDAC circuit, a third ADC circuit configured to convert an output of the second MDAC circuit into a third digital signal, and a common amplifying circuit shared by the first and the second MDAC circuits, wherein the common amplifying circuit consumes current based on which MDAC circuit the common amplifying circuit operates with. | 11-29-2012 |
Yun Taek Hwang, Icheon-Si KR
Patent application number | Description | Published |
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20090146246 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - The present invention relates to a semiconductor device and a method of manufacture thereof, being capable of improving the high integration by increasing a cell region while securing the reliability of device and the process margin through forming a cell region and a core region with the stacking structure. | 06-11-2009 |
20090218604 | Semiconductor Device and Method for Manufacturing the Same - A semiconductor device includes a PMOS transistor of a peripheral circuit region. The PMOS transistor is formed over a silicon germanium layer to have a compressive strain structure, thereby increasing hole mobility of a channel region in operation of the device. The semiconductor device may include a second active region including a silicon layer connected to a first active region of a semiconductor substrate, a silicon germanium layer formed over the silicon layer expected to be a PMOS region, and a PMOS gate formed over the silicon germanium layer. | 09-03-2009 |
20090218628 | Semiconductor Device and Method for Manufacturing the Same - A semiconductor device includes a NMOS transistor of a peripheral circuit region. The NMOS transistor is formed over a relaxed silicon germanium layer and a silicon layer to have a tensile strain structure, thereby increasing electron mobility of a channel region in operation of the device. The semiconductor device may include a second active region including a first silicon layer connected to a first active region of a semiconductor substrate, a second silicon layer and a relaxed silicon germanium layer formed over the first silicon layer expected to be a NMOS region, and a NMOS gate formed over the second silicon layer. | 09-03-2009 |
20090218635 | Semiconductor Device and Method for Manufacturing the Same - A method for manufacturing a semiconductor device includes forming a transistor having a stacked structure in a peripheral circuit region to increase net die and forming a metal silicide layer over a source/drain region of a transistor formed over an upper layer to reduce a contact resistance. The semiconductor device may include: a second active region including a silicon layer connected to a first active region of a semiconductor substrate; a gate formed over the second active region; a spacer formed on sidewalls of the gate; a source/drain region form at both sides of the spacer; and a metal silicide layer formed over the gate and the source/drain region | 09-03-2009 |
20100117041 | RESISTIVE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A resistive memory device includes a first conductive line on a substrate, a vertical selection diode comprising a nanowire or a nanotube and being arranged over the first conductive line, a resistive element including a resistive layer arranged over the vertical selection diode; and a second conductive line arranged over the resistive element. | 05-13-2010 |
20110012207 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a PMOS transistor of a peripheral circuit region. The PMOS transistor is formed over a silicon germanium layer to have a compressive strain structure, thereby increasing hole mobility of a channel region in operation of the device. The semiconductor device may include a second active region including a silicon layer connected to a first active region of a semiconductor substrate, a silicon germanium layer formed over the silicon layer expected to be a PMOS region, and a PMOS gate formed over the silicon germanium layer. | 01-20-2011 |
20120040506 | Method for Forming Semiconductor Device - A method for manufacturing a semiconductor device includes forming a transistor having a stacked structure in a peripheral circuit region to increase net die and forming a metal silicide layer over a source/drain region of a transistor formed over an upper layer to reduce a contact resistance. The semiconductor device may include: a second active region including a silicon layer connected to a first active region of a semiconductor substrate; a gate formed over the second active region; a spacer formed on sidewalls of the gate; a source/drain region form at both sides of the spacer; and a metal silicide layer formed over the gate and the source/drain region. | 02-16-2012 |