Patent application number | Description | Published |
20080227301 | Control of bevel etch film profile using plasma exclusion zone rings larger than the wafer diameter - A method of cleaning a bevel edge of a semiconductor substrate is provided. A semiconductor substrate is placed on a substrate support in a reaction chamber of a plasma processing apparatus. The substrate has a dielectric layer overlying a top surface and a bevel edge of the substrate, the layer extending above and below an apex of the bevel edge. A process gas is introduced into the reaction chamber and energized into a plasma. The bevel edge is cleaned with the plasma so as to remove the layer below the apex without removing all of the layer above the apex. | 09-18-2008 |
20090272402 | METHOD AND APPARATUS FOR DETECTING PLASMA UNCONFINEMENT - A method for detecting plasma unconfinement in a reaction chamber during a bevel edge cleaning operation is provided. The method initiates with selecting a wavelength associated with expected by products of a bevel edge clean process. The method includes cleaning the bevel edge area of a substrate and monitoring the intensity of the selected wavelengths during the cleaning for deviation from a threshold wavelength intensity. The cleaning is terminated if the deviation from the threshold wavelength intensity exceeds a target deviation. | 11-05-2009 |
20120305189 | Method and Apparatus for Detecting Plasma Unconfinement - A method for detecting plasma unconfinement in a reaction chamber during a bevel edge cleaning operation is provided. The method initiates with selecting a wavelength associated with expected by products of a bevel edge clean process. The method includes cleaning the bevel edge area of a substrate and monitoring the intensity of the selected wavelengths during the cleaning for deviation from a threshold wavelength intensity. The cleaning is terminated if the deviation from the threshold wavelength intensity exceeds a target deviation. | 12-06-2012 |
20130264015 | CONTROL OF BEVEL ETCH FILM PROFILE USING PLASMA EXCLUSION ZONE RINGS LARGER THAN THE WAFER DIAMETER - A method of cleaning a bevel edge of a semiconductor substrate is provided. A semiconductor substrate is placed on a substrate support in a reaction chamber of a plasma processing apparatus. The substrate has a dielectric layer overlying a top surface and a bevel edge of the substrate, the layer extending above and below an apex of the bevel edge. A process gas is introduced into the reaction chamber and energized into a plasma. The bevel edge is cleaned with the plasma so as to remove the layer below the apex without removing all of the layer above the apex. | 10-10-2013 |
20140020708 | EDGE EXCLUSION CONTROL WITH ADJUSTABLE PLASMA EXCLUSION ZONE RING - Systems and methods for edge exclusion control are described. One of the systems includes a plasma chamber. The plasma processing chamber includes a lower electrode having a surface for supporting a substrate. The lower electrode is coupled with a radio frequency (RF) power supply. The plasma processing chamber further includes an upper electrode disposed over the lower electrode. The upper electrode is electrically grounded. The plasma processing chamber includes an upper dielectric ring surrounding the upper electrode. The upper dielectric ring is moved using a mechanism for setting a vertical position of the upper dielectric ring separate from a position of the upper electrode. The system further includes an upper electrode extension surrounding the upper dielectric ring. The upper electrode extension is electrically grounded. The system also includes a lower electrode extension surrounding the lower dielectric ring. The lower electrode extension is arranged opposite the upper electrode extension. | 01-23-2014 |
Patent application number | Description | Published |
20100309720 | Structure and Method for Shuffling Data Within Non-Volatile Memory Devices - Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. The techniques further allow for the data to be encoded with an error correction code (ECC) on the controller that takes into account its eventual multi-state storage prior to transferring the data to the memory to be written in binary form. A register structure allowing such a “folding” operation is also presented. One set of embodiments include a local internal data bus that allows data to between the registers of different read/write stacks, where the internal bus can used in the internal data folding process. | 12-09-2010 |
20110002169 | Bad Column Management with Bit Information in Non-Volatile Memory Systems - Column based defect management techniques are presented. Each column of the memory has an associated isolation latch or register whose value indicates whether the column is defective, but in addition to this information, for columns marked as defective, additional information is used to indicate whether the column as a whole is to be treated as defective, or whether just individual bits of the column are defective. The defective elements can then be re-mapped to a redundant element at either the appropriate bit or column level based on the data. When a column is bad, but only on the bit level, the good bits can still be used for data, although this may be done at a penalty of under programming for some bits, as is described further below. A self contained Built In Self Test (BIST) flow constructed to collect the bit information through a set of column tests is also described. Based on this information, the bad bits can be extracted and re-grouped into bytes by the controller or on the memory to more efficiently use the column redundancy area. | 01-06-2011 |
20120113716 | Structure and Method for Shuffling Data Within Non-Volatile Memory Devices - Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. A register structure allowing such a “folding” operation is also presented. One set of embodiments include a local internal data bus that allows data to between the registers of different read/write stacks, where the internal bus can used in the internal data folding process. | 05-10-2012 |
20120297245 | Bad Column Management with Bit Information in Non-Volatile Memory Systems - Column based defect management techniques are presented. Each column of the memory has an associated isolation latch or register whose value indicates whether the column is defective, but in addition to this information, for columns marked as defective, additional information is used to indicate whether the column as a whole is to be treated as defective, or whether just individual bits of the column are defective. The defective elements can then be re-mapped to a redundant element at either the appropriate bit or column level based on the data. When a column is bad, but only on the bit level, the good bits can still be used for data. | 11-22-2012 |
20130100740 | Compact Sense Amplifier for Non-Volatile Memory Suitable for Quick Pass Write - A compact and versatile sense amp is presented. Among its other features this sense amp arrangement provides a way to pre-charge bit lines while doing data scanning. Another feature is that the sense amp circuit can provide a way to set three different bit line levels used in the quick pass write (QPW) technique using dynamic latch, where quick pass write is a technique where cells along a given word line selected for programming can be enabled, inhibited, or partially inhibited for programming. Also, it can provide a convenient way to measure the cell current. | 04-25-2013 |
20130100744 | Compact Sense Amplifier for Non-Volatile Memory - A compact and versatile sense amp is presented. Among its other features this sense amp arrangement provides a way to pre-charge bit lines while doing data scanning. Another feature is that the sense amp circuit can provide a way to set three different bit line levels used in the quick pass write (QPW) technique using dynamic latch, where quick pass write is a technique where cells along a given word line selected for programming can be enabled, inhibited, or partially inhibited for programming. Also, it can provide a convenient way to measure the cell current. | 04-25-2013 |
20140133229 | BIT LINE RESISTANCE COMPENSATION - Methods for compensating for variations in bit line resistance during sensing of memory cells are described. The variations in bit line resistance may occur die-to-die or plane-to-plane on the same die. In some embodiments, for each die or memory plane on a die, a plurality of bit line read voltages associated with a plurality of zones may be determined based on sensing criteria. The sensing criteria may comprise a number of fail bits. Each zone of the plurality of zones may be associated with a memory array region within a die or memory plane. Prior to performing a read or verify operation on a group of memory cells, a bit line read voltage used during sensing of the group of memory cells may be determined based on the plurality of bit line read voltages and a zone associated with the group of memory cells. | 05-15-2014 |
20140133230 | BIT LINE RESISTANCE COMPENSATION - Methods for compensating for variations in bit line resistance during sensing of memory cells are described. The variations in bit line resistance may occur die-to-die or plane-to-plane on the same die. In some embodiments, for each die or memory plane on a die, a plurality of bit line read voltages associated with a plurality of zones may be determined based on sensing criteria such as a number of fail bits. Each zone of the plurality of zones may be associated with a memory array region within a memory plane. Within each zone, different bit line read voltages may be applied to different bit line groupings in order to compensate for systematic variations in bit line resistance between neighboring bit lines due to the use of multiple patterning lithography techniques such as spacer-based double patterning. | 05-15-2014 |
20140133231 | BIT LINE RESISTANCE COMPENSATION - Methods for compensating for variations in bit line resistance in non-volatile memories are described. In some embodiments, use of multiple patterning lithography for forming bit lines may lead to systematic variations in bit line resistance between groups of bit lines within a memory array. For example, in some cases, every fourth bit line of four neighboring (or adjacent) bit lines may be formed differently than the other three bit lines within a group of four neighboring bit lines. In one embodiment, bit line segment swapping may be used between blocks within a memory array in order to mitigate variations in bit line resistance. In another embodiment, each group of adjacent bit line segments may be offset (or staggered) per block such that the local routing necessary to connect bit line segments into bit lines may be simplified. | 05-15-2014 |
20140219023 | Bad Column Management with Bit Information in Non-Volatile Memory Systems - Column based defect management techniques are presented. Each column of the memory has an associated isolation latch or register whose value indicates whether the column is defective, but in addition to this information, for columns marked as defective, additional information is used to indicate whether the column as a whole is to be treated as defective, or whether just individual bits of the column are defective. The defective elements can then be re-mapped to a redundant element at either the appropriate bit or column level based on the data. When a column is bad, but only on the bit level, the good bits can still be used for data, although this may be done at a penalty of under programming for some bits, as is described further below. A self contained Built In Self Test (BIST) flow constructed to collect the bit information through a set of column tests is also described. Based on this information, the bad bits can be extracted and re-grouped into bytes by the controller or on the memory to more efficiently use the column redundancy area. | 08-07-2014 |
20140269100 | SHARED BIT LINE STRING ARCHITECTURE - Methods for programming and reading memory cells using a shared bit line string architecture are described. In some embodiments, memory cells and select devices may correspond with transistors including a charge storage layer. In some cases, the charge storage layer may be conductive (e.g., a polysilicon layer as used in a floating gate device) or non-conductive (e.g., a silicon nitride layer as used in a SONOS device). In some embodiments, selection of a memory cell in a first string of a pair of strings may include setting an SEO transistor into a conducting state and setting an SGD line controlling drain-side select transistors to a voltage that is greater than a first threshold voltage associated with a first drain-side select transistor of the first string and less than a second threshold voltage associated with a second drain-side select transistor of a second string of the pair of strings. | 09-18-2014 |
Patent application number | Description | Published |
20130000694 | PHOTOVOLTAIC MODULE AND LAMINATE - A photovoltaic module is disclosed. The photovoltaic module has a first side directed toward the sun during normal operation and a second, lower side. The photovoltaic module comprises a perimeter frame and a photovoltaic laminate at least partially enclosed by and supported by the perimeter frame. The photovoltaic laminate comprises a transparent cover layer positioned toward the first side of the photovoltaic module, an upper encapsulant layer beneath and adhering to the cover layer, a plurality of photovoltaic solar cells beneath the upper encapsulant layer, the photovoltaic solar cells electrically interconnected, a lower encapsulant layer beneath the plurality of photovoltaic solar cells, the upper and lower encapsulant layers enclosing the plurality of photovoltaic solar cells, and a homogenous rear environmental protection layer, the rear environmental protection layer adhering to the lower encapsulant layer, the rear environmental protection layer exposed to the ambient environment on the second side of the photovoltaic module. | 01-03-2013 |
20140034111 | PHOTOVOLTAIC MODULE AND LAMINATE - A photovoltaic module has a first side directed toward the sun during normal operation and a second, lower side. The photovoltaic module comprises a perimeter frame and a photovoltaic laminate at least partially enclosed by and supported by the perimeter frame. The photovoltaic laminate comprises a transparent cover layer positioned toward the first side of the photovoltaic module, an upper encapsulant layer beneath and adhering to the cover layer, a plurality of photovoltaic solar cells beneath the upper encapsulant layer, the photovoltaic solar cells electrically interconnected, a lower encapsulant layer beneath the plurality of photovoltaic solar cells, the upper and lower encapsulant layers enclosing the plurality of photovoltaic solar cells, and a homogenous rear environmental protection layer, the rear environmental protection layer adhering to the lower encapsulant layer, the rear environmental protection layer exposed to the ambient environment on the second side of the photovoltaic module. | 02-06-2014 |
20140116495 | BIFACIAL SOLAR CELL MODULE WITH BACKSIDE REFLECTOR - A bifacial solar cell module includes solar cells that are protected by front side packaging components and backside packaging components. The front side packaging components include a transparent top cover on a front portion of the solar cell module. The backside packaging components have a transparent portion that allows light coming from a back portion of the solar cell module to reach the solar cells, and a reflective portion that reflects light coming from the front portion of the solar cell module. The transparent and reflective portions may be integrated with a backsheet, e.g., by printing colored pigments on the backsheet. The reflective portion may also be on a reflective component that is separate from the backsheet. In that case, the reflective component may be placed over a clear backsheet before or after packaging. | 05-01-2014 |
20140144487 | CRACK RESISTANT SOLAR CELL MODULES - A crack resistant solar cell module includes a protective package mounted on a frame. The protective package includes a polyolefin encapsulant that protectively encapsulates solar cells. The polyolefin has less than five weight percent of oxygen and nitrogen in the backbone or side chain. In other words, the combined weight percent of oxygen and nitrogen in any location in the molecular structure of the polyolefin is less than five. The polyolefin also has a complex viscosity less than 10,000 Pa second at 90° C. as measured by dynamic mechanical analysis (DMA) before any thermal processing of the polyolefin. The protective package includes a top cover, the encapsulant, and a backsheet. The solar cell module allows for shipping, installation, and maintenance with less risk of developing cracks on the surfaces of the solar cells. | 05-29-2014 |
20150053248 | INTERCONNECTION OF SOLAR CELLS IN A SOLAR CELL MODULE - A solar cell module includes serially connected solar cells. A solar cell includes a carrier that is attached to the backside of the solar cell. Solar cells are attached to a top cover, and vias are formed through the carriers of the solar cells. A solar cell is electrically connected to an adjacent solar cell in the solar cell module with metal connections in the vias. | 02-26-2015 |
Patent application number | Description | Published |
20100328982 | CONTENT ADDRESSABLE MEMORY DESIGN - A static CAM includes a plurality of entries E each including a number of CAM cells B and a summary S. Each CAM cell B is associated with a memory cell M and a comparator C. Generally, the CAM receives as input i number of lookup data lines. When data is received, memory cells M provide compared data for corresponding comparators C in CAM cells B to compare the compared data to the received data. If all compared data match all received data lines for an entry, then there is a hit for that entry. But if any compared data does not match the corresponding data line, then there is a miss for that line and therefore a miss for that entry. Depending on applications, the CAM returns an address if there is a hit for one or a plurality of entries. | 12-30-2010 |
20110280096 | MEMORY CIRCUITS HAVING A PLURALITY OF KEEPERS - A memory circuit includes a first plurality of memory arrays disposed in a column fashion. The memory circuit includes a first plurality of keepers each of which is electrically coupled with a corresponding one of the first plurality of memory arrays. A first current limiter is electrically coupled with and shared by the first plurality of keepers. A first plurality of sector switches each are electrically coupled between the first current limiter and a respective one of the first plurality of keepers. | 11-17-2011 |
20120008376 | MEMORY WITH REGULATED GROUND NODES - Some embodiments regard a memory array comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns; wherein a column of the plurality of columns includes a column ground node; at least two voltage sources configured to be selectively coupled to the column ground node; and a plurality of memory cells having a plurality of internal ground nodes electrically coupled together and to the column ground node. | 01-12-2012 |
20120014201 | DUAL RAIL MEMORY - A memory comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A column of the plurality of columns including a first power supply node configured to provide a first voltage, a second power supply node configured to provide a second voltage, a plurality of internal supply nodes electrically coupled together and configured to receive the first voltage or the second voltage for a plurality of memory cells in the column and a plurality of internal ground nodes. The internal ground nodes electrically coupled together and configured to provide at least two current paths for the plurality of memory cells in the column. | 01-19-2012 |
20120019312 | RECYCLING CHARGES - A circuit includes a first node; a second node; a first PMOS transistor having a source coupled to the first node, a drain coupled to a first control transistor, and a gate driven by a first voltage; and a first NMOS transistor having a source coupled to the second node, a drain coupled to the first control transistor, and a gate driven by a second voltage. The first PMOS transistor is configured to automatically turn off based on the first voltage and a first node voltage at the first node. The first NMOS transistor is configured to automatically turn off based on the second voltage and a second node voltage at the second node. When the first PMOS transistor, the control transistor, and the first NMOS transistor are on, the first node voltage is lowered while the second voltage is raised. | 01-26-2012 |
20120134220 | WRITE ASSIST CIRCUITRY - A circuit includes a word line driver for driving a world line and a tracking word line driver for driving a tracking word line. The pulse width of a world line signal on the world line is driven to be larger than that of a tracking world line signal on the tracking world line to assist writing under difficult conditions. Because the tracking word line signal is activated later than the word line signal being activated but is deactivated at the same time with the word line, the pulse width of the word line signal is larger. | 05-31-2012 |
20120182819 | RECYCLING CHARGES - A circuit includes a first node; a second node; a first PMOS transistor having a source coupled to the first node, a drain coupled to a first control transistor, and a gate driven by a first voltage; and a first NMOS transistor having a source coupled to the second node, a drain coupled to the first control transistor, and a gate driven by a second voltage. The first PMOS transistor is configured to automatically turn off based on the first voltage and a first node voltage at the first node. The first NMOS transistor is configured to automatically turn off based on the second voltage and a second node voltage at the second node. When the first PMOS transistor, the control transistor, and the first NMOS transistor are on, the first node voltage is lowered while the second voltage is raised. | 07-19-2012 |
20130028040 | DUAL RAIL MEMORY - A memory array comprises a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A column of the plurality of columns includes a first voltage circuit coupled to internal first nodes of memory cells in the one of the plurality of columns and a second voltage circuit coupled to internal second nodes of the memory cells in the one of the plurality of columns. The first voltage circuit is configured to provide one of a first supply voltage and a second supply voltage lower than the first supply voltage to the internal first nodes. The second voltage circuit is configured to provide one of a first reference voltage and a second reference voltage higher than the first reference voltage to the internal second nodes. | 01-31-2013 |
20130155749 | CONTENT ADDRESSABLE MEMORY - A memory includes a plurality of content-addressable memory (CAM) cells and a summary circuit associated with the plurality of CAM cells. The summary circuit includes a first level of logic gates and a second level of logic gates. The first level of logic gates have inputs each configured to receive an output of a corresponding one of the plurality of CAM cell. The second level of logic gates have inputs each configured to receive an output of a corresponding one of the first level of logic gates. | 06-20-2013 |
20130182512 | MEMORY CIRCUITS HAVING A PLURALITY OF KEEPERS - A circuit including a memory circuit, the memory circuit includes a first plurality of memory arrays and a first plurality of keepers, each keeper of the first plurality of keepers is electrically coupled with a corresponding one of the first plurality of memory arrays. The memory circuit further includes a first current limiter electrically coupled with and shared by the first plurality of keepers. | 07-18-2013 |
20130215693 | TRACKING CAPACITIVE LOADS - A time delay is determined to cover a timing of a memory cell in a memory macro having a tracking circuit. Based on the time delay, a capacitance corresponding to the time delay is determined. A capacitor having the determined capacitance is utilized. The capacitor is coupled to a first data line of a tracking cell of the tracking circuit. A first transition of the first data line causes a first transition of a second data line of the memory cell. | 08-22-2013 |
20140043921 | METHOD OF MEMORY WITH REGULATED GROUND NODES - A method of reading data from an accessed memory cell of an accessed column of an accessed section of a memory array includes, in the accessed section, electrically coupling a first voltage source of at least three voltage sources to a corresponding column internal ground node of the accessed column; and electrically coupling the first voltage source to a corresponding column internal ground node of an un-accessed column. The memory array has at least one segment, the at least one segment has at least one section, and each section has at least one column. Each column has at least three switches and a column internal ground node capable of being electrically coupled to at least three voltage sources through a corresponding one of the at least three switches. | 02-13-2014 |
20140153345 | METHOD OF OPERATING WRITE ASSIST CIRCUITRY - A method includes causing, by a first circuit, a first signal transition at a first node based on a clock signal. A first edge, from a first level to a second level, of a word line signal is generated responsive to the first signal transition. A second signal transition at a second node is caused by a second circuit based on the clock signal. The second circuit and the first circuit are configured to cause the second signal transition to occur later than the first signal transition by a delay time. A first edge, from a third logic level to a fourth level, of a tracking word line signal is generated responsive to the second signal transition. | 06-05-2014 |
20140250416 | CONTENT ADDRESSABLE MEMORY - A method of designing a content-addressable memory (CAM) includes associating CAM cells with a summary circuit. The summary circuit includes a first level of logic gates and a second level of logic gates. The first level of logic gates have inputs each configured to receive an output of a corresponding one of the plurality of CAM cell. The second level of logic gates have inputs each configured to receive an output of a corresponding one of the first level of logic gates. Logic gates in at least one of the first level of logic gates or the second level of logic gates are selected to have an odd number of input pins so that an input pin and an output pin share a layout sub-slot. | 09-04-2014 |