Patent application number | Description | Published |
20100026329 | TEST APPARATUS AND ELECTRONIC DEVICE - Provided is a test apparatus that tests a device under test including an external interface circuit that transfers signals between an internal circuit inside a device and the outside of the device, the test apparatus comprising a pattern generating section that inputs, to the external interface circuit, a test pattern for testing the external interface circuit; an interface control section that causes the external interface circuit to loop back and output the test pattern; and an interface judging section that judges acceptability of the external interface circuit based on the test pattern looped back and output by the external interface circuit. | 02-04-2010 |
20100026541 | D-A CONVERTER AND D-A CONVERTING METHOD - Provided is a DA converter that converts an input digital signal into an analog signal, comprising an integrator that outputs an integration value of the digital signal for each cycle of a constant period; a level comparing section that makes a comparison to detect whether the integration value output by the integrator is in an excessive state of being greater than a prescribed reference value; a feedback section that subtracts a predetermined value from the integration value, based on the comparison result from the level comparing section; a timing information generating section that generates, for each cycle, timing information of a change point, at which a transition to the excessive state occurs, with units of temporal resolution shorter than the constant period, based on the integration value output by the integrator for the cycle and the integration value output by the integrator for an immediately prior cycle; a timing generating section that generates a pulse signal with units of temporal resolution shorter than the constant period based on the timing information; and a signal processing section that generates the analog signal based on the pulse signal. | 02-04-2010 |
20100026544 | A-D CONVERTER - Provided is an AD converter that converts an input analog signal into a digital signal, comprising an integrator that sequentially integrates signal levels of the analog signal to obtain an integrated waveform, and outputs the integrated waveform; a digital converting section that detects, with prescribed units of temporal resolution, a transition timing, which is a timing at which a magnitude relationship between a signal level of the integrated waveform and a prescribed reference value transitions to a predetermined state; a feedback section that controls the signal level of the integrated waveform with a control period longer than a unit of temporal resolution, according to a result of the detection by the digital converting section; and a signal processing section that generates the digital signal based on the detection result by the digital converting section. | 02-04-2010 |
20100066443 | DEMODULATION APPARATUS, TEST APPARATUS AND ELECTRONIC DEVICE - A demodulation apparatus that demodulates an amplitude-phase-modulated signal having a level and a transition phase selected from among a plurality of levels and a plurality of phases according to transmission data, comprising a clock recovering section that receives the amplitude-phase-modulated signal and recovers a clock signal synchronized with the amplitude-phase-modulated signal; an amplitude and phase detecting section that detects, with the clock signal as a reference, the level and the transition phase of the amplitude-phase-modulated signal; a data output section that outputs data corresponding to the level and the transition phase detected by the amplitude and phase detecting section; and a phase difference correcting section that outputs a correction signal for correcting an oscillation frequency of the clock signal output by the clock recovering section, according to the transition phase detected by the amplitude and phase detecting section. | 03-18-2010 |
20100090709 | TEST APPARATUS AND TEST METHOD - Provided is a test apparatus that tests a device under test, comprising a pattern generating section that generates a test pattern determined according to a test signal to be supplied to the device under test; a timing signal generating section that generates a timing signal indicating a timing for supplying the test signal to the device under test; a digital filter that filters the test pattern to output a jitter control signal representing jitter corresponding to the test pattern; a jitter injecting section that injects the timing signal with jitter by delaying the timing signal according to the jitter control signal; and a waveform shaping section that generates the test signal formed according to the test pattern, with the timing signal into which the jitter is injected as a reference. | 04-15-2010 |
20100148751 | NOISE MEASUREMENT APPARATUS AND TEST APPARATUS - Provided is a noise measurement apparatus that measures noise at a location under measurement, comprising a self-excited oscillator that is provided at the location under measurement and that outputs an oscillation signal in which is sequentially accumulated, in each cycle, the noise at the location under measurement; a transmission path that transmits the oscillation signal output by the self-excited oscillator; and a measuring unit that measures noise added to the oscillation signal transmitted through the transmission path. The measuring unit may measure the noise at the location under measurement by differentiating noise added to the oscillation signal transmitted through the transmission path. | 06-17-2010 |
20100158515 | TRANSMISSION SYSTEM AND TEST APPARATUS - Provided is a transmission system that transmits data, comprising a modulating section that modulates amplitude of a predetermined carrier signal according to the data to be transmitted; an electro-optical converting section that converts a modulated signal output by the modulating section into an optical signal; an optical fiber that transmits the optical signal; an optical-electric converting section that converts the optical signal transmitted by the optical fiber into a current signal; a current-voltage converting section that linearly converts the current signal into a voltage signal; and a demodulating section that demodulates the voltage signal. | 06-24-2010 |
20100161280 | ELECTRONIC DEVICE, HOST APPARATUS, COMMUNICATION SYSTEM, AND RECORDING MEDIUM - Provided is a communication system comprising a host apparatus and an electronic device that is implemented in an apparatus that communicates with the host apparatus via a network. The electronic device includes an operation circuit that operates when the electronic device is implemented; a diagnostic circuit that tests the operation circuit; and a result transmitting section that transmits a test result obtained by the diagnostic circuit to the host apparatus via the network. The host apparatus includes a test information storage section that stores in advance test information indicating test content to be performed by the diagnostic circuit; and a test information transmitting section that, when the test information is requested by the electronic device, transmits the test information to the electronic device. | 06-24-2010 |
20100208780 | TRANSFER CIRCUIT, TRANSMITTER, RECEIVER AND TEST APPARATUS - There is provided a transfer circuit including a transmitter that outputs a transmission signal and a receiver that receives the transmission signal. Here, the receiver supplies to the transmitter a feedback signal for controlling a common level of the transmission signal output from the transmitter, and the transmitter controls the common level of the transmission signal output therefrom, in accordance with the feedback signal received from the receiver. The receiver includes a receiving section that operates in accordance with the transmission signal, a reference level generating section that generates a reference level representing an expected level for the common level of the transmission signal input into the receiving section, and a comparing section that compares the common level of the transmission signal input into the receiving section against the reference level and generates the feedback signal in accordance with a result of the comparison. | 08-19-2010 |
20100308856 | Test apparatus and test method - Provided is a test apparatus for testing a device under test, including: a level comparing section that receives a signal under test output from the device under test and outputs a logical value, the logical value indicating a comparison result obtained by comparing a signal level of the signal under test with preset first threshold and second threshold; an acquiring section that acquires the logical value output from the level comparing section, according to a strobe signal supplied thereto; an expected value comparing circuit that determines whether the logical value acquired by the acquiring section corresponds to a preset expected value; and a threshold control section that sets an upper limit and a lower limit of a voltage of the eye mask to the level comparing section as the first threshold and the second threshold, when an eye mask test is performed for determining whether an eye opening of the signal under test is larger than a predefined eye mask. | 12-09-2010 |
20100327967 | TEST APPARATUS, DEMODULATION APPARATUS, TEST METHOD, DEMODULATION METHOD AND ELECTRIC DEVICE - Provided is a test apparatus for testing a device under test that outputs, as an output signal, an amplitude-phase modulated signal having a level and a transition point phase selected from among a plurality of levels and a plurality of phases according to transmission data, the test apparatus comprising a comparing section that compares the output signal to a first comparison level, which is less than the expected level, before the expected phase, and compares the output signal to a second comparison level, which is greater than the expected level, and to a third comparison level, which is less than the expected level, after the expected phase; and a judging section that judges that the output signal matches the expected values on a condition that (i) the output signal is less than or equal to the first comparison level before the expected phase and (ii) the output signal is less than or equal to the second comparison level and greater than or equal to the third comparison level after the expected phase. | 12-30-2010 |
20110074497 | POWER SUPPLY STABILIZING CIRCUIT, ELECTRONIC DEVICE AND TEST APPARATUS - A test apparatus that tests a device under test, comprising a signal input section that supplies a test signal to a device under test and a judging section that judges acceptability of the device under test based on a response signal output by the device under test in response to the test signal. The signal input section includes an operation circuit that operates to generate the test signal and a power supply stabilizing circuit provided in the same chip to stabilize power supply voltage supplied to the operation circuit. The power supply stabilizing circuit includes a high-speed compensating section compensating for a change in the power supply voltage supplied to the operation circuit, at a predetermined compensation speed, and a low-speed compensating section compensating for the change in the power supply voltage supplied to the operation circuit, at a predetermined compensation speed lower than that of the high-speed compensating section. | 03-31-2011 |
20110099443 | TEST APPARATUS - Provided is a test apparatus that tests a device under test, comprising a plurality of test circuits that each perform a predetermined test function; a plurality of I/O circuits that are provided between the test circuits and the device under test, where at least one of the circuits has electrical characteristics that differ from the electrical characteristics of the other circuits; and an I/O switching section that switches which of the I/O circuits is used to electrically connect at least one of the test circuits to the device under test. | 04-28-2011 |
20110109321 | TEST APPARATUS AND ELECTRICAL DEVICE - Provided is a test apparatus that tests a device under test, comprising a digital signal generator that outputs in parallel one or more n-bit digital test signals, where n is an integer greater than or equal to 1; a plurality of driver circuits that are connected respectively to a plurality of digital terminals of the device under test; and an analog signal generator that generates an analog test signal by converting, into an analog signal, an n×m-bit digital multi-bit signal based on the one or more digital test signals output by the digital signal generator to the plurality of driver circuits, where m is an integer greater than or equal to 2. | 05-12-2011 |
20110121815 | MEASURING APPARATUS, PARALLEL MEASURING APPARATUS, TESTING APPARATUS AND ELECTRONIC DEVICE - Provided is a measurement apparatus that measures a signal under measurement, comprising a first oscillation circuit that receives one pulse of the signal under measurement and begins oscillating according to the pulse of the signal under measurement to output a first oscillated signal; a second oscillation circuit that receives one pulse of a reference signal and begins oscillating according to the pulse of the reference signal to output a second oscillated signal having a period that is different from a period of the first oscillated signal; and a first sampling section that samples the first oscillated signal according to a pulse of the second oscillated signal. The first oscillation circuit and the second oscillation circuit each include a control section that selects one pulse; a delay section that delays the pulse; and a loop line that feeds the pulse back to an input terminal of the delay section | 05-26-2011 |
20110125308 | APPARATUS FOR MANUFACTURING SUBSTRATE FOR TESTING, METHOD FOR MANUFACTURING SUBSTRATE FOR TESTING AND RECORDING MEDIUM - A test substrate manufacturing apparatus comprising a test circuit database that stores circuit data of a plurality of types of test circuits in association with a plurality of types of testing content; a definition information storing section that stores definition information defining arrangements of device pads of devices under test and testing content to be performed for each of the device pads; and a lithography data generating section that generates lithography data for the test substrate by (i) selecting, from the test circuit database, circuit data of each test circuit to be connected to a device pad based on the testing content defined by the definition information stored in the definition information storing section and (ii) determining positions on the test substrate where the test circuits corresponding to the selected circuit data are formed using lithography, based on the arrangements of the device pads as defined by the definition information. | 05-26-2011 |
20110128027 | WAFER UNIT FOR TESTING AND TEST SYSTEM - Provided is a test wafer unit that tests a plurality of circuits under test formed on a wafer under test. The test wafer unit comprises a test wafer that is formed of a semiconductor material and exchanges signals with each of the circuits under test, and a plurality of loop-back sections that are provided in the test wafer to correspond to the plurality of circuits under test and that each supply the corresponding circuit under test with a loop-back signal corresponding to a signal received from the corresponding circuit under test. | 06-02-2011 |
20110128031 | TEST SYSTEM AND SUBSTRATE UNIT FOR TESTING - A test system that tests a plurality of chips under test formed on a wafer under test, the test system comprising a plurality of test substrates that are arranged in overlapping layers and that each have a plurality of test circuits, whose function is determined for each wafer, formed thereon; a plurality of connecting sections that electrically connect, to the chips under test, the test circuits formed on one of the test substrates; and a control apparatus that controls each of the test circuits. Each test substrate has test circuits, with a function predetermined for each substrate, formed thereon. | 06-02-2011 |
20110128032 | WAFER FOR TESTING, TEST SYSTEM, AND SEMICONDUCTOR WAFER - Provided is a test wafer that tests a plurality of semiconductor chips that are formed on a semiconductor wafer and that each include an operation circuit and an internal memory. The test wafer comprises a plurality of test circuits that correspond to the plurality of semiconductor chips, supply the operation circuits of the corresponding semiconductor chips with measurement signals, and measure electrical characteristics of signals output by the operation circuits in response to the measurement signals; and a plurality of write circuits that correspond to the plurality of semiconductor chips and each write, to the internal memory of the corresponding semiconductor chip, data corresponding to a measurement result of the corresponding test circuit. | 06-02-2011 |
20110133748 | SIGNAL OUTPUT CIRCUIT, TIMING GENERATE CIRCUIT, TEST APPARATUS AND RECEIVER CIRCUIT - Provided is a signal output circuit that outputs a signal, comprising an output circuit that changes a characteristic of a signal output therefrom according to a change in power supply voltage supplied thereto and a control signal supplied thereto; and a control section that changes the control signal to compensate for a change in the characteristic due to a change in the power supply voltage. | 06-09-2011 |
20110148454 | SEMICONDUCTOR WAFER, SEMICONDUCTOR CIRCUIT, SUBSTRATE FOR TESTING AND TEST SYSTEM - A test system includes a test substrate that transmits/receives signals to/from a semiconductor wafer, and a control apparatus to control the test substrate. The semiconductor wafer includes an external terminal coupled to an external measurement circuit, a plurality of selecting wiring lines provided to receive/transmit signals to/from the corresponding the measuring points, and a selecting section that selects one of the selecting wiring lines and that allows signal transmission between the corresponding measuring point and the external terminal through the selected selecting wiring line. The test substrate includes a measurement circuit that is coupled to the external terminal of the semiconductor wafer and that measures an electrical characteristic of a signal transmitted through the selecting wiring line selected by the selecting section, and a control section that controls which one of the measurement wiring lines is to be selected by the selecting section in the semiconductor wafer. | 06-23-2011 |
20110163771 | TEST APPARATUS AND DRIVER CIRCUIT - A test apparatus includes: a driver circuit that supplies, to a device under test, a test signal corresponding to an input signal; and a judging section that judges pass/fail of the device under test, based on the load voltage or the load current supplied to the device under test when supplying a test signal of a constant current or a constant voltage to the device under test from the driver circuit, where the driver circuit includes: a driver section that outputs the test signal; a supply current detecting section that detects a supply current supplied to the driver section; and an output control section that controls a voltage or a current of the test signal outputted from the driver section to the predetermined value, based on the supply current detected by the supply current detecting section. | 07-07-2011 |
20110193138 | ELECTRONIC DEVICE AND MANUFACTURING METHOD - Provided is an electronic device that generates an output signal corresponding to an input signal, comprising a signal processing section that receives the input signal and outputs the output signal corresponding to the input signal, and a floating electrode that accumulates a charge by being irradiated by an electron beam. The signal processing section adjusts electric characteristics of the output signal according to a charge amount accumulated in the floating electrode, and includes a transistor formed on the semiconductor substrate between an input terminal that receives the input signal and an output terminal that outputs the output signal. The floating electrode is formed between a gate electrode of the transistor and the semiconductor substrate | 08-11-2011 |
20110218752 | TEST APPARATUS AND MANUFACTURING METHOD - Provided is a test apparatus that tests a plurality of devices under test formed on a wafer under test. The test apparatus comprises a test substrate that faces the wafer under test and is electrically connected to the devices under test; a programmable device that is provided on the test substrate and changes a logic relationship of output logic data with respect to input logic data, according to program data supplied thereto; a plurality of input/output circuits that are provided on the test substrate to correspond to the devices under test and that each supply the corresponding device under test with a test signal corresponding to the output logic data of the programmable device; and a judging section that judges pass/fail of each device under test, based on operation results of each device under test according to the test signal. | 09-08-2011 |
20110234252 | WAFER UNIT FOR TESTING AND TEST SYSTEM - Provided is a test wafer unit for testing a plurality of semiconductor chips formed on a semiconductor wafer, the test wafer unit including: a test wafer having a shape corresponding to a shape of the semiconductor wafer; and a plurality of test circuits formed on the test wafer, each test circuit provided to correspond to two or more of the plurality of semiconductor chips and testing the two or more semiconductor chips. The test wafer unit may include a plurality of connection terminals formed on the test wafer in one to one relation with test terminals of the plurality of semiconductor chips, where each of the plurality of connection terminals is connected to a corresponding one of the test terminals. | 09-29-2011 |
20110242895 | MEMORY DEVICE, MANUFACTURING METHOD FOR MEMORY DEVICE AND METHOD FOR DATA WRITING - A memory device to which an electron beam is irradiated to store data therein is provided. The memory device includes a plurality of floating electrodes that store data through irradiation of the electron beam thereto, a charge amount detecting section that detects data stored in each of the floating electrodes based on a charge amount accumulated in each of the floating electrode. | 10-06-2011 |