Patent application number | Description | Published |
20130337637 | STRAINED SILICON AND STRAINED SILICON GERMANIUM ON INSULATOR METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS (MOSFETS) - A method of forming a semiconductor device that includes providing a first strained layer of a first composition semiconductor material over a dielectric layer. A first portion of the layer of the first composition semiconductor material is etched or implanted to form relaxed islands of the first composition semiconductor material. A second composition semiconductor material is epitaxially formed over the relaxed island of the first composition semiconductor material. The second composition semiconductor material is intermixed with the relaxed islands of the first composition semiconductor material to provide a second strained layer having a different strain than the first strained layer. | 12-19-2013 |
20140191286 | COMPRESSIVE STRAINED III-V COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICE - A semiconductor device including a first lattice dimension III-V semiconductor layer present on a semiconductor substrate, and a second lattice dimension III-V semiconductor layer that present on the first lattice dimension III-V semiconductor layer, wherein the second lattice dimension III-V semiconductor layer has a greater lattice dimension than the first lattice dimension III-V semiconductor layer, and the second lattice dimension III-V semiconductor layer has a compressive strain present therein. A gate structure is present on a channel portion of the second lattice dimension III-V semiconductor layer, wherein the channel portion of second lattice dimension III-V semiconductor layer has the compressive strain. A source region and a drain region are present on opposing sides of the channel portion of the second lattice dimension III-V semiconductor layer. | 07-10-2014 |
20140191287 | COMPRESSIVE STRAINED III-V COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICE - A semiconductor device including a first lattice dimension III-V semiconductor layer present on a semiconductor substrate, and a second lattice dimension III-V semiconductor layer that present on the first lattice dimension III-V semiconductor layer, wherein the second lattice dimension III-V semiconductor layer has a greater lattice dimension than the first lattice dimension III-V semiconductor layer, and the second lattice dimension III-V semiconductor layer has a compressive strain present therein. A gate structure is present on a channel portion of the second lattice dimension III-V semiconductor layer, wherein the channel portion of second lattice dimension III-V semiconductor layer has the compressive strain. A source region and a drain region are present on opposing sides of the channel portion of the second lattice dimension III-V semiconductor layer. | 07-10-2014 |
20140239394 | U-SHAPED SEMICONDUCTOR STRUCTURE - A method for forming a U-shaped semiconductor device includes forming trenches in a crystalline layer and epitaxially growing a U-shaped semiconductor material along sidewalls and bottoms of the trenches. The U-shaped semiconductor material is anchored, and the crystalline layer is removed. The U-shaped semiconductor material is supported by backfilling underneath the U-shaped semiconductor material with a dielectric material. A semiconductor device is formed with the U-shaped semiconductor material. | 08-28-2014 |
20140239398 | U-SHAPED SEMICONDUCTOR STRUCTURE - A method for forming a U-shaped semiconductor device includes forming trenches in a crystalline layer and epitaxially growing a U-shaped semiconductor material along sidewalls and bottoms of the trenches. The U-shaped semiconductor material is anchored, and the crystalline layer is removed. The U-shaped semiconductor material is supported by backfilling underneath the U-shaped semiconductor material with a dielectric material. A semiconductor device is formed with the U-shaped semiconductor material. | 08-28-2014 |
20140264594 | FORMATION OF BULK SiGe FIN WITH DIELECTRIC ISOLATION BY ANODIZATION - A method of fabricating a semiconductor device is provided that includes providing a material stack that includes a silicon layer, a doped semiconductor layer, and an undoped silicon germanium layer. At least one fin structure is formed from the material stack by etching through the undoped silicon germanium layer, the doped semiconductor layer, and etching a portion of the silicon-containing layer. An isolation region is formed in contact with at least one end of the at least one fin structure. An anodization process removes the doped semiconductor layer of the at least one fin structure to provide a void. A dielectric layer is deposited to fill the void that is present between the silicon layer and the doped semiconductor layer. Source and drain regions are then formed on a channel portion of the at least one fin structure. | 09-18-2014 |
20140264600 | FORMATION OF BULK SiGe FIN WITH DIELECTRIC ISOLATION BY ANODIZATION - A method of fabricating a semiconductor device is provided that includes providing a material stack that includes a silicon layer, a doped semiconductor layer, and an undoped silicon germanium layer. At least one fin structure is formed from the material stack by etching through the undoped silicon germanium layer, the doped semiconductor layer, and etching a portion of the silicon-containing layer. An isolation region is formed in contact with at least one end of the at least one fin structure. An anodization process removes the doped semiconductor layer of the at least one fin structure to provide a void. A dielectric layer is deposited to fill the void that is present between the silicon layer and the doped semiconductor layer. Source and drain regions are then formed on a channel portion of the at least one fin structure. | 09-18-2014 |
20140264746 | SELF ALIGNED CAPACITOR FABRICATION - A capacitor and method for fabricating the same. In one configuration, the capacitor has a silicon substrate, a first and a second silicon dioxide layer over the silicon substrate, and silicon nitride fins between the silicon dioxide layers. The capacitor further includes a dielectric layer over the silicon nitride fins and metal vias in the dielectric layer. | 09-18-2014 |
20140332900 | LOW EXTENSION RESISTANCE III-V COMPOUND FIN FIELD EFFECT TRANSISTOR - A gate stack including a gate dielectric and a gate electrode is formed over at least one compound semiconductor fin provided on an insulating substrate. The at least one compound semiconductor fin is thinned employing the gate stack as an etch mask. Source/drain extension regions are epitaxially deposited on physically exposed surfaces of the at least one semiconductor fin. A gate spacer is formed around the gate stack. A raised source region and a raised drain region are epitaxially formed on the source/drain extension regions. The source/drain extension regions are self-aligned to sidewalls of the gate stack, and thus ensure a sufficient overlap with the gate electrode. Further, the combination of the source/drain extension regions and the raised source/drain regions provides a low-resistance path to the channel of the field effect transistor. | 11-13-2014 |
20140335665 | LOW EXTENSION RESISTANCE III-V COMPOUND FIN FIELD EFFECT TRANSISTOR - A gate stack including a gate dielectric and a gate electrode is formed over at least one compound semiconductor fin provided on an insulating substrate. The at least one compound semiconductor fin is thinned employing the gate stack as an etch mask. Source/drain extension regions are epitaxially deposited on physically exposed surfaces of the at least one semiconductor fin. A gate spacer is formed around the gate stack. A raised source region and a raised drain region are epitaxially formed on the source/drain extension regions. The source/drain extension regions are self-aligned to sidewalls of the gate stack, and thus ensure a sufficient overlap with the gate electrode. Further, the combination of the source/drain extension regions and the raised source/drain regions provides a low-resistance path to the channel of the field effect transistor. | 11-13-2014 |
20140346587 | INTEGRATED CIRCUIT HAVING MOSFET WITH EMBEDDED STRESSOR AND METHOD TO FABRICATE SAME - A method includes forming a recess into a crystalline semiconductor substrate, the recess being disposed beneath and surrounding a channel region of a transistor; depositing a layer of crystalline dielectric material onto a surface of the substrate that is exposed within the recess; and depositing stressor material into the recess such that the layer of dielectric material is disposed between the stressor material and the surface of the substrate. A structure includes a gate stack or gate stack precursor disposed on a SOI layer disposed upon a BOX that is disposed upon a surface of a crystalline semiconductor substrate. A transistor channel is disposed within the SOI layer. The structure further includes a channel stressor layer disposed at least partially within a recess in the substrate and disposed about the channel, and a layer of crystalline dielectric material disposed between the stressor layer and a surface of the substrate. | 11-27-2014 |
20140346600 | Integrated Circuit Having MOSFET with Embedded Stressor and Method to Fabricate Same - A structure includes a gate stack or gate stack precursor disposed on a SOI layer disposed upon a BOX that is disposed upon a surface of a crystalline semiconductor substrate. A transistor channel is disposed within the SOI layer. The structure further includes a channel stressor layer disposed at least partially within a recess in the substrate and disposed about the channel, and a layer of crystalline dielectric material disposed between the stressor layer and a surface of the substrate. | 11-27-2014 |
20140353752 | MULTI-HEIGHT FINFETS WITH COPLANAR TOPOGRAPHY BACKGROUND - A semiconductor structure is provided that has semiconductor fins having variable heights without any undue topography. The semiconductor structure includes a semiconductor substrate having a first semiconductor surface and a second semiconductor surface, wherein the first semiconductor surface is vertically offset and located above the second semiconductor surface. An oxide region is located directly on the first semiconductor surface and/or the second semiconductor surface. A first set of first semiconductor fins having a first height is located above the first semiconductor surface of the semiconductor substrate. A second set of second semiconductor fins having a second height is located above the second semiconductor surface, wherein the second height is different than the first height and wherein each first semiconductor fin and each second semiconductor fin have topmost surfaces which are coplanar with each other. | 12-04-2014 |
20140357034 | MULTI-HEIGHT FINFETS WITH COPLANAR TOPOGRAPHY - A semiconductor structure is provided that has semiconductor fins having variable heights without any undue topography. The semiconductor structure includes a semiconductor substrate having a first semiconductor surface and a second semiconductor surface, wherein the first semiconductor surface is vertically offset and located above the second semiconductor surface. An oxide region is located directly on the first semiconductor surface and/or the second semiconductor surface. A first set of first semiconductor fins having a first height is located above the first semiconductor surface of the semiconductor substrate. A second set of second semiconductor fins having a second height is located above the second semiconductor surface, wherein the second height is different than the first height and wherein each first semiconductor fin and each second semiconductor fin have topmost surfaces which are coplanar with each other. | 12-04-2014 |
20140367752 | TRANSISTOR HAVING ALL-AROUND SOURCE/DRAIN METAL CONTACT CHANNEL STRESSOR AND METHOD TO FABRICATE SAME - An intermediate transistor structure includes a fin structure disposed on a surface of an insulating layer. The fin structure has a gate structure disposed thereon between first and second ends of the fin structure. A first portion of the fin structure is a first doped portion that is disposed over a first recess in the surface of the insulating layer and a second portion of the fin structure is a second doped portion disposed over a second recess in the surface of the insulating layer. The intermediate transistor structure further includes source and drain metal disposed around the first and second doped portions, each inducing one of compression strain or tensile strain in a portion of the fin structure that is disposed within the gate structure and that functions during operation of the transistor as a channel of the transistor. | 12-18-2014 |
20140374796 | SEMICONDUCTOR STRUCTURE WITH ASPECT RATIO TRAPPING CAPABILITIES - A semiconductor structure includes a first semiconductor region. The first semiconductor region includes a first semiconductor layer composed of a group IV semiconductor material having a top surface and a back surface. The first semiconductor layer has an opening in the top surface to at least a depth greater than an aspect ratio trapping (ART) distance. The first semiconductor region also has a second semiconductor layer composed of a group III/V semiconductor compound deposited within the opening and on the top surface of the first semiconductor layer. The second semiconductor layer forms an ART region from the bottom of the opening to the ART distance. | 12-25-2014 |
20150041853 | BONDED EPITAXIAL OXIDE STRUCTURES FOR COMPOUND SEMICONDUCTOR ON SILICON SUBSTRATES - A structure including a compound semiconductor layer epitaxially grown on an epitaxial oxide layer is provided wherein the lattice constant of the epitaxial oxide layer may be different from the semiconductor substrate on which it is grown. Fabrication of one structure includes growing a graded semiconductor layer stack to engineer a desired lattice parameter on a semiconductor substrate or layer. The desired compound semiconductor layer is formed on the graded layer. The epitaxial oxide layer is grown on and lattice matched to the desired layer. Fabrication of an alternative structure includes growing a layer of desired compound semiconductor material directly on a germanium substrate or a germanium layer formed on a silicon substrate and growing an epitaxial oxide layer on the layer of the desired material. Following implantation of a cleavage layer and wafer bonding to a handle wafer, the layer of desired compound semiconductor material is fractured along the cleavage layer and the residual portion thereof removed. A layer of the desired compound semiconductor material is then regrown on the epitaxial oxide layer. | 02-12-2015 |
20150041856 | Compound Semiconductor Integrated Circuit and Method to Fabricate Same - A structure includes a substrate having a surface and a first transistor disposed in a first region supported by the surface of the substrate. The first transistor has a channel formed in a first compound (Group III-V) semiconductor having a first energy bandgap. The structure further includes a second transistor disposed in a second region supported by the substrate. The second transistor has a channel formed in a second compound (Group III-V) semiconductor having a second energy bandgap that is larger than the first energy bandgap. In one embodiment the first compound semiconductor is a layer that overlies a first portion of the surface of the substrate and the substrate is the second compound semiconductor. In another embodiment the second compound semiconductor is provided as a second layer that overlies a second portion of the surface of the substrate. | 02-12-2015 |
20150044859 | COMPOUND SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD TO FABRICATE SAME - A structure includes a substrate having a surface and a first transistor disposed in a first region supported by the surface of the substrate. The first transistor has a channel formed in a first compound (Group III-V) semiconductor having a first energy bandgap. The structure further includes a second transistor disposed in a second region supported by the substrate. The second transistor has a channel formed in a second compound (Group III-V) semiconductor having a second energy bandgap that is larger than the first energy bandgap. In one embodiment the first compound semiconductor is a layer that overlies a first portion of the surface of the substrate and the substrate is the second compound semiconductor. In another embodiment the second compound semiconductor is provided as a second layer that overlies a second portion of the surface of the substrate. Methods to form the structure are also disclosed. | 02-12-2015 |
20150060981 | STACKED NANOWIRE - A method of fabricating stacked nanowire for a transistor gate and a stacked nanowire device are described. The method includes etching a fin as a vertical structure from a substrate and forming two or more pairs of spacers at vertically separated positions of the fin. The method also includes oxidizing to form the nanowires at the vertically separated positions of the fin. | 03-05-2015 |
20150064891 | STACKED NANOWIRE - A method of fabricating stacked nanowire for a transistor gate and a stacked nanowire device are described. The method includes etching a fin as a vertical structure from a substrate and forming two or more pairs of spacers at vertically separated positions of the fin. The method also includes oxidizing to form the nanowires at the vertically separated positions of the fin. | 03-05-2015 |
20150069327 | FIN FIELD-EFFECT TRANSISTORS WITH SUPERLATTICE CHANNELS - FinFET structures may be formed including superlattice fins. The structure may include a superlattice fin of alternating layers of silicon-germanium with a germanium concentration of approximately 10% to 80% and a second semiconductor material. In some embodiments, the second semiconductor material may include either silicon or carbon-doped silicon. Where the second semiconductor material is carbon-doped silicon, the carbon concentration may range from approximately 0.2% to approximately 4%. The superlattice fin may have a height ranging from approximately 5 nm to approximately 100 nm and include between 5 and 30 alternating layers of silicon-germanium and the second semiconductor material. A gate may be formed over the superlattice fin and a source/drain region may be formed over an end of the superlattice fin. | 03-12-2015 |
20150069465 | HIGH PERCENTAGE SILICON GERMANIUM ALLOY FIN FORMATION - A layer of a silicon germanium alloy containing 30 atomic percent or greater germanium and containing substitutional carbon is grown on a surface of a semiconductor layer. The presence of the substitutional carbon in the layer of silicon germanium alloy compensates the strain of the silicon germanium alloy, and suppresses defect formation. Placeholder semiconductor fins are then formed to a desired dimension within the layer of silicon germanium alloy and the semiconductor layer. The placeholder semiconductor fins will relax for the most part, while maintaining strain in a lengthwise direction. An anneal is then performed which may either remove the substitutional carbon from each placeholder semiconductor fin or move the substitutional carbon into interstitial sites within the lattice of the silicon germanium alloy. Free-standing permanent semiconductor fins containing 30 atomic percent or greater germanium, and strain in the lengthwise direction are provided. | 03-12-2015 |
20150069521 | NANOWIRE COMPATIBLE E-FUSE - An e-fuse is provided in one area of a semiconductor substrate. The E-fuse includes a vertical stack of from, bottom to top, base metal semiconductor alloy portion, a first metal semiconductor alloy portion, a second metal semiconductor portion, a third metal semiconductor alloy portion and a fourth metal semiconductor alloy portion, wherein the first metal semiconductor alloy portion and the third metal semiconductor portion have outer edges that are vertically offset and do not extend beyond vertical edges of the second metal semiconductor alloy portion and the fourth metal semiconductor alloy portion. | 03-12-2015 |
20150076604 | FIELD EFFECT TRANSISTOR INCLUDING A RECESSED AND REGROWN CHANNEL - At least one doped semiconductor material region is formed over a crystalline insulator layer. A disposable gate structure and a planarization dielectric layer laterally surrounding the disposable gate structure are formed over the at least one doped semiconductor material region. The disposable gate structure is removed selective to the planarization dielectric layer to form a gate cavity. Portions of the at least one doped semiconductor material region are removed from underneath the gate cavity. Remaining portions of the at least one doped semiconductor material region constitute a source region and a drain region. A channel region is epitaxially grown from a physically exposed surface of the crystalline insulator layer. The channel region has a uniform thickness that can be less than the thickness of the source region and the drain region, and is epitaxially aligned to the crystalline insulator layer. | 03-19-2015 |
20150083999 | Gate-All-Around Nanowire MOSFET and Method of Formation - A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench. | 03-26-2015 |
20150084001 | GATE-ALL-AROUND NANOWIRE MOSFET AND METHOD OF FORMATION - A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench. | 03-26-2015 |
20150123205 | FIELD EFFECT TRANSISTOR INCLUDING A REGROWN CONTOURED CHANNEL - At least one doped semiconductor material region is formed over a crystalline insulator layer. A disposable gate structure and a planarization dielectric layer laterally surrounding the disposable gate structure are formed over the at least one doped semiconductor material region. The disposable gate structure is removed selective to the planarization dielectric layer to form a gate cavity. Portions of the at least one doped semiconductor material region are removed from underneath the gate cavity. Remaining portions of the at least one doped semiconductor material region constitute a source region and a drain region. A faceted crystalline dielectric material portion is grown from a physically exposed surface of the crystalline insulator layer. A contoured channel region is epitaxially grown on the faceted crystalline dielectric material portion. The contoured channel region increases the distance that charge carriers travel relative to a separation distance between the source region and the drain region. | 05-07-2015 |
20150126009 | U-SHAPED SEMICONDUCTOR STRUCTURE - A method for forming a U-shaped semiconductor device includes growing a U-shaped semiconductor material along sidewalls and bottoms of trenches, which are formed in a crystalline layer. The U-shaped semiconductor material is anchored, and the crystalline layer is removed. Backfilling is formed underneath the U-shaped semiconductor material with a dielectric material for support. A semiconductor device is formed with the U-shaped semiconductor material. | 05-07-2015 |
20150228652 | SEMICONDUCTOR DEVICE INCLUDING NANOWIRE TRANSISTORS WITH HYBRID CHANNELS - A semiconductor device is provided that includes an n-type field effect transistor including a plurality of vertically stacked silicon-containing nanowires located in one region of a semiconductor substrate, and a p-type field effect transistor including a plurality of vertically stacked silicon germanium alloy nanowires located in another region of a semiconductor substrate. Each vertically stacked silicon-containing nanowire of the n-type field effect transistor has a different shape than the shape of each vertically stacked silicon germanium alloy nanowire of the p-type field effect transistor. | 08-13-2015 |
20150228653 | SiGe and Si FinFET Structures and Methods for Making the Same - FinFET structures and methods for making the same. A method includes: creating a plurality of Silicon fins on a first region of a substrate, creating a plurality of Silicon-Germanium fins on a second region of the substrate, adjusting a Silicon fin pitch of the plurality of Silicon fins to a predetermined value, and adjusting a Silicon-Germanium fin pitch of the plurality of Silicon-Germanium fins to a predetermined value, where the creating steps are performed in a manner that Silicon material and Silicon-Germanium material used in making the plurality of fins will be on the semiconductor structure at a same time. | 08-13-2015 |
20150228783 | FIELD EFFECT TRANSISTORS EMPLOYING A THIN CHANNEL REGION ON A CRYSTALLINE INSULATOR STRUCTURE - A single crystalline dielectric layer is provided on an insulator layer including an amorphous dielectric material. The single crystalline dielectric layer can be patterned into various crystalline dielectric portions including dielectric fins, dielectric nanowires, and a dielectric fin-plate assembly. A semiconductor material can be deposited on the single crystalline surfaces of the various crystalline dielectric portions by a selective epitaxial deposition process while not growing on the surfaces of the insulator layer. Single crystalline semiconductor material portions can be formed on the surfaces of the dielectric fins, around the dielectric nanowires, and on horizontal and vertical surfaces of the dielectric fin-plate assembly. Source and drain regions can be formed in the single crystalline semiconductor material portions, and gate electrodes can be formed to provide various field effect transistors. | 08-13-2015 |
20150236120 | NANOWIRE TRANSISTOR STRUCTURES WITH MERGED SOURCE/DRAIN REGIONS USING AUXILIARY PILLARS - A nanowire transistor structure is fabricated by using auxiliary epitaxial nucleation source/drain fin structures. The fin structures include semiconductor layers integral with nanowires that extend between the fin structures. Gate structures are formed between the fin structures such that the nanowires extend through the gate conductors. Following spacer formation and nanowire chop, source/drain regions are grown epitaxially between the gate structures. | 08-20-2015 |
20150249139 | METHODS OF FORMING GERMANIUM-CONTAINING AND/OR III-V NANOWIRE GATE-ALL-AROUND TRANSISTORS - Methods of forming gate-all-around transistors which include a germanium-containing nanowire and/or an III-V compound semiconductor nanowire. Each method includes the growth of a germanium-containing material or an III-V compound semiconductor material that includes an upper portion and a lower portion within a nano-trench and on an exposed surface of a semiconductor layer. In some instances, the upper portion of the grown semiconductor material is used as the semiconductor nanowire. In other instances, the upper portion is removed and then a semiconductor etch stop layer and a nanowire template semiconductor material of a Ge-containing material or an III-V compound semiconductor material can be formed atop the lower portion. Upon subsequent processing, each nanowire template semiconductor material provides a semiconductor nanowire. | 09-03-2015 |
20150255543 | STRAINED FinFET BY EPITAXIAL STRESSOR INDEPENDENT OF GATE PITCH - A semiconductor device fabrication process includes forming a fin and a plurality of gates upon a semiconductor substrate, forming sacrificial spacers upon opposing gate sidewalls, forming a mask upon an upper surface of the fin between neighboring gates, removing the sacrificial spacers, recessing a plurality of regions of the fin to create a dummy fin and fin segments, removing the mask, and epitaxially merging the dummy fin and fin segments. The fins may be partially recessed prior to forming the sacrificial spacers. The device may include the substrate, gates, fin segments each associated with a particular gate, the dummy fin between a fin segment pair separated by the wider pitch, and merged epitaxy connecting the dummy fin and the fin segment pair. The dummy fin may serve as a filler between the fin segment pair and may add epitaxial growth planes to allow for epitaxial merging within the wider pitch. | 09-10-2015 |
20150263091 | LATERAL BIPOLAR JUNCTION TRANSISTOR HAVING GRADED SiGe BASE - A lateral bipolar junction transistor is fabricated using a semiconductor-on-insulator substrate. The transistor includes a germanium gradient within a doped silicon base region, there being an increasing germanium content in the direction of the collector region of the transistor. The use of a substrate including parallel silicon fins to fabricate lateral bipolar junction transistors facilitates the inclusion of both CMOS FinFET devices and lateral bipolar junction transistors having graded silicon germanium base regions on the same chip. | 09-17-2015 |
20150263097 | INTEGRATED CIRCUIT HAVING HETEROSTRUCTURE FINFET WITH TUNABLE DEVICE PARAMETERS AND METHOD TO FABRICATE SAME - A field effect transistor (FET) device has a fin disposed over a substrate. The fin has opposing ends defining a source and a drain and intermediate the source and the drain a channel underlying a gate. The fin is formed as a heterostructure having at least one first layer of material and at least one second layer of material that is adjacent to the first layer of material. A thickness of at least one of the first layer of material and the second layer of material is selected to obtain a particular effective device width W. Methods to fabricate the FET device are also described. | 09-17-2015 |
20150270267 | ABRUPT SOURCE/DRAIN JUNCTION FORMATION USING A DIFFUSION FACILITATION LAYER - A method of forming a field effect transistor (FET) device includes forming a diffusion facilitation layer on top of a semiconductor substrate; forming a doped, raised source/drain (RSD) layer on the diffusion facilitation layer; removing a portion of the diffusion facilitation layer, corresponding to a region directly above a channel region of the FET device; and performing an anneal so as to define abrupt source and drain junctions in the semiconductor substrate, wherein dopant atoms from the doped RSD layer diffuse within the diffusion facilitation layer at a faster rate than with respect to the semiconductor substrate. | 09-24-2015 |
20150270340 | STRESSED NANOWIRE STACK FOR FIELD EFFECT TRANSISTOR - A disposable gate structure is formed over the alternating stack of first semiconductor material portions and second semiconductor material portions. The second semiconductor material portions are removed selective to the first semiconductor material portions to form suspended semiconductor nanowires. Isolated gate structures are formed in regions underlying the disposable gate structure by deposition and recessing of a first gate dielectric layer and a first gate conductor layer. After formation of a gate spacer, source regions, and drain regions, raised source and drain regions are formed on the source regions and the drain regions by selective deposition of a semiconductor material. The disposable gate structure is replaced with a replacement gate structure by deposition and patterning of a second gate dielectric layer and a second gate conductor layer. Distortion of the suspended semiconductor nanowires is prevented by the disposable gate structure and the isolated gate structures. | 09-24-2015 |
20150270343 | ABRUPT SOURCE/DRAIN JUNCTION FORMATION USING A DIFFUSION FACILITATION LAYER - A method of forming a field effect transistor (FET) device includes forming a diffusion facilitation layer on top of a semiconductor substrate; forming a doped, raised source/drain (RSD) layer on the diffusion facilitation layer; removing a portion of the diffusion facilitation layer, corresponding to a region directly above a channel region of the FET device; and performing an anneal so as to define abrupt source and drain junctions in the semiconductor substrate, wherein dopant atoms from the doped RSD layer diffuse within the diffusion facilitation layer at a faster rate than with respect to the semiconductor substrate. | 09-24-2015 |
20150295037 | Gate-All-Around Nanowire MOSFET and Method of Formation - A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench. | 10-15-2015 |
20150295038 | Gate-All-Around Nanowire MOSFET and Method of Formation - A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench. | 10-15-2015 |
20150295039 | Gate-All-Around Nanowire MOSFET and Method of Formation - A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench. | 10-15-2015 |
20150303251 | BONDED EPITAXIAL OXIDE STRUCTURES FOR COMPOUND SEMICONDUCTOR ON SILICON SUBSTRATES - A structure includes a handle substrate and an epitaxial oxide layer. The epitaxial oxide layer is bonded directly or indirectly to the handle substrate. Also included is a compound semiconductor layer adjoining and lattice matched to the epitaxial oxide layer. | 10-22-2015 |
20150303257 | Gate-All-Around Nanowire MOSFET and Method of Formation - A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench. | 10-22-2015 |
20150311109 | CHANNEL SiGe DEVICES WITH MULTIPLE THRESHOLD VOLTAGES ON HYBRID ORIENTED SUBSTRATES, AND METHODS OF MANUFACTURING SAME - Multiple threshold voltage devices on hybrid oriented substrates, and methods of manufacturing same are disclosed. A method for manufacturing a semiconductor device comprises performing a single epitaxy step on a hybrid orientation substrate including a first region having a first crystallographic orientation and a second region having a second crystallographic orientation different from the first crystallographic orientation, wherein the single epitaxy step forms a first layer disposed on the first region and a second layer disposed on the second region, the first layer has the first crystallographic orientation and a first composition, and the second layer has the second crystal orientation and a second composition different from the first composition. | 10-29-2015 |
20150318303 | FIELD EFFECT TRANSISTORS INCLUDING CONTOURED CHANNELS AND PLANAR CHANNELS - Disposable gate structures and a planarization dielectric layer are formed over doped semiconductor material portions on a crystalline insulator layer. Gate cavities are formed by removing the disposable gate structures selective to the planarization dielectric layer. Doped semiconductor material portions are removed from underneath the gate cavities to provide pairs of source and drain regions separated by a gate cavity. Within a first gate cavity, a faceted crystalline dielectric material portion is grown from a physically exposed surface of the crystalline insulator layer, while a second gate is temporarily coated with an amorphous material layer. A contoured semiconductor region is epitaxially grown on the faceted crystalline dielectric material portion in the first gate cavity, while a planar semiconductor region is epitaxially grown in the second gate cavity. The semiconductor regions can provide at least one contoured channel region and at least one planar channel region. | 11-05-2015 |
20150325664 | Gate-All-Around Nanowire MOSFET and Method of Formation - A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench. | 11-12-2015 |
20150332964 | SELF-LIMITING SILICIDE IN HIGHLY SCALED FIN TECHNOLOGY - A method of forming a metal semiconductor alloy on a fin structure that includes forming a semiconductor material layer of a polycrystalline crystal structure material or amorphous crystal structure material on a fin structure of a single crystal semiconductor material, and forming a metal including layer on the semiconductor material layer. Metal elements from the metal including layer may then be intermixed metal elements with the semiconductor material layer to provide a metal semiconductor alloy contact on the fin structure. A core of the fin structure of the single crystal semiconductor material is substantially free of the metal elements from the metal including layer. | 11-19-2015 |
20150333172 | METHOD TO CONTROLLABLY ETCH SILICON RECESS FOR ULTRA SHALLOW JUNCTIONS - A method of forming a semiconductor device that includes forming a germanium including material on source and drain region portions of a silicon containing fin structure, and annealing to drive germanium into the source and drain region portions of the fin structure. The alloyed portions of fin structures composed of silicon and germanium are then removed using a selective etch. After the alloyed portions of the fin structures are removed, epitaxial source and drain regions are formed on the remaining portions of the fin structure. | 11-19-2015 |
20150349123 | STRAINED FinFET BY EPITAXIAL STRESSOR INDEPENDENT OF GATE PITCH - A semiconductor device is fabricated by forming a fin and a plurality of gates upon a semiconductor substrate, forming sacrificial spacers upon opposing gate sidewalls, forming a mask upon an upper surface of the fin between neighboring gates, removing the sacrificial spacers, recessing a plurality of regions of the fin to create a dummy fin and fin segments, removing the mask, and epitaxially merging the dummy fin and fin segments. The fins may be partially recessed prior to forming the sacrificial spacers. The device may include the substrate, gates, fin segments each associated with a particular gate, the dummy fin between a fin segment pair separated by the wider pitch, and merged epitaxy connecting the dummy fin and the fin segment pair. The dummy fin may serve as a filler between the fin segment pair and may add epitaxial growth planes to allow for epitaxial merging within the wider pitch. | 12-03-2015 |
20150364361 | SHALLOW TRENCH ISOLATION REGIONS MADE FROM CRYSTALLINE OXIDES - A method of manufacturing a semiconductor device that involves etching a trench in a semiconductor substrate, epitaxially growing a crystalline structure in the trench and forming semiconductor structures on either side of the crystalline structure. Crystalline oxides may include rare earth oxides, aluminum oxides or Perovskites. | 12-17-2015 |
20160027870 | FABRICATION OF PERFECTLY SYMMETRIC GATE-ALL-AROUND FET ON SUSPENDED NANOWIRE USING INTERFACE INTERACTION - A semiconductor device including a plurality of suspended nanowires and a gate structure present on a channel region portion of the plurality of suspended nanowires. The gate structure has a uniform length extending from an upper surface of the gate structure to the base of the gate structure. The semiconductor device further includes a dielectric spacer having a uniform composition in direct contact with the gate structure. Source and drain regions are present on source and drain region portions of the plurality of suspended nanowires. | 01-28-2016 |
20160027929 | PERFECTLY SYMMETRIC GATE-ALL-AROUND FET ON SUSPENDED NANOWIRE - A semiconductor device including a plurality of suspended nanowires and a gate structure that is present on a channel region portion of the plurality of suspended nanowires. The gate structure includes a uniform length extending from an upper surface of the gate structure to the base of the gate structure. A dielectric spacer having a graded composition is present in direct contact with the gate structure. The dielectric spacer having a uniform length extending from an upper surface of the gate structure to the base of the gate structure. Source and drain regions are present on source and drain region portions of the plurality of suspended nanowires. | 01-28-2016 |
20160043087 | SiGe and Si FinFET Structures and Methods for Making the Same - FinFET structures and methods for making the same. A method includes: creating a plurality of Silicon fins on a first region of a substrate, creating a plurality of Silicon-Germanium fins on a second region of the substrate, adjusting a Silicon fin pitch of the plurality of Silicon fins to a predetermined value, and adjusting a Silicon-Germanium fin pitch of the plurality of Silicon-Germanium fins to a predetermined value, where the creating steps are performed in a manner that Silicon material and Silicon-Germanium material used in making the plurality of fins will be on the semiconductor structure at a same time. | 02-11-2016 |
20160064288 | DUAL CHANNEL MATERIAL FOR finFET FOR HIGH PERFORMANCE CMOS - Silicon fins are formed in a bulk silicon substrate and thereafter trench isolation regions are formed between each silicon fin. The silicon fins in nFET and pFET device regions are then recessed. A relaxed silicon germanium alloy fin portion is formed on a topmost surface of each recessed silicon fin portion or on exposed surface of the substrate. A compressively strained silicon germanium alloy fin portion is formed on each relaxed silicon germanium alloy fin portion within the pFET device region, and a strained silicon-containing fin portion is formed on each relaxed silicon germanium alloy fin portion within the nFET device region. Sidewall surfaces of each compressively strained silicon-containing germanium alloy fin portion and each tensile strained silicon-containing fin portion are then exposed. A functional gate structure is provided on the exposed sidewall surfaces of each compressively strained silicon-containing germanium alloy fin portion and each tensile strained silicon-containing fin portion. | 03-03-2016 |
20160064482 | NANOWIRE TRANSISTOR STRUCTURES WITH MERGED SOURCE/DRAIN REGIONS USING AUXILIARY PILLARS - A nanowire transistor structure is fabricated by using auxiliary epitaxial nucleation source/drain fin structures. The fin structures include semiconductor layers integral with nanowires that extend between the fin structures. Gate structures are formed between the fin structures such that the nanowires extend through the gate conductors. Following spacer formation and nanowire chop, source/drain regions are grown epitaxially between the gate structures. | 03-03-2016 |
20160071931 | METHOD OF FORMATION OF GERMANIUM NANOWIRES ON BULK SUBSTRATES - A material stack comprising alternating layers of a silicon etch stop material and a germanium nanowire template material is formed on a surface of a bulk substrate. The material stack and a portion of the bulk substrate are then patterned by etching to provide an intermediate fin structure including a base semiconductor portion and alternating portions of the silicon etch stop material and the germanium nanowire template material. After recessing each germanium nanowire template material and optionally the base semiconductor portion, and etching each silicon etch stop material to define a new fin structure, a spacer is formed on sidewall surfaces of the remaining portions of the new fin structure. The alternating layers of germanium nanowire template material are then suspended above a notched surface portion of the bulk substrate and thereafter a functional gate structure is formed. | 03-10-2016 |
20160071956 | HIGH GERMANIUM CONTENT SILICON GERMANIUM FINS - Thermal condensation is employed to obtain a finned structure including strained silicon germanium fins having vertical side walls and a germanium content that may be high relative to silicon. A hard mask is used directly on a low-germanium content silicon germanium layer. The hard mask is patterned and fins are formed beneath the hard mask from the silicon germanium layer. Thermal condensation in an oxidizing ambient causes the formation of regions beneath the hard mask that have a high germanium content. The hard mask is trimmed to a target critical dimension. The regions beneath the hard mask and adjoining oxide material are subjected to reactive ion etch, resulting in the formation of high-germanium content fins with planar, vertically extending sidewalls. | 03-10-2016 |
20160086886 | NANOWIRE COMPATIBLE E-FUSE - An e-fuse is provided in one area of a semiconductor substrate. The E-fuse includes a vertical stack of from, bottom to top, base metal semiconductor alloy portion, a first metal semiconductor alloy portion, a second metal semiconductor portion, a third metal semiconductor alloy portion and a fourth metal semiconductor alloy portion, wherein the first metal semiconductor alloy portion and the third metal semiconductor portion have outer edges that are vertically offset and do not extend beyond vertical edges of the second metal semiconductor alloy portion and the fourth metal semiconductor alloy portion. | 03-24-2016 |
20160093695 | FORMING IV FINS AND III-V FINS ON INSULATOR - A method of forming a semiconductor structure. The method may include; forming first fins in a pFET region and an nFET region using epitaxial growth, the first fins are a group IV semiconductor; forming a spacer layer on the first fins; removing the spacer layer from a top surface and a first side of the first fins in the nFET region, a portion of the first fins are exposed on the top surface and the first side of the first fins in the nFET region; and forming second fins on the exposed portion of the first fins using epitaxial growth, the second fins are a group IV semiconductor, the second fins have a second pitch between adjacent second fins, the first pitch is equal to the second pitch, the first fins and the second fins have a shared bottom surface. | 03-31-2016 |