Patent application number | Description | Published |
20080252365 | APPARATUS AND METHOD FOR TUNING CENTER FREQUENCY OF A FILTER - A method for tuning a filter is provided. The method includes: enabling a VCO circuit, wherein at least a portion of the VCO circuit is selected from the filter; generating an oscillation signal by the VCO circuit according to a driving signal; comparing the oscillation signal with a reference signal and generating a comparison result; and adjusting the driving signal according to the comparison result. | 10-16-2008 |
20090085532 | DC-DC CONVERTER - A DC-DC converter providing a DC output voltage at an output node. The DC-DC converter comprises an output stage, a digital controller, and a controller. The output stage comprises a pull-up circuit having a control terminal and coupled between a first fixed voltage and a internal node, a pull-down circuit coupled between the internal node and a second fixed voltage, and a low pass filter coupled between the internal node and the output node. The digital controller is powered by the DC output voltage and adjusts the DC output voltage by controlling the output stage. The controller controls a connection of a feedback path, comprising the digital controller, between the output node and the control terminal according to the DC output voltage. | 04-02-2009 |
20090167369 | LVDS OUTPUT DRIVER - An output driver is disclosed. The output driver has a pair of differential outputs coupled to a first supply voltage via a pair of load devices and comprises a current source, a pair of low voltage transistors, a pair of high voltage transistors, and a resistor. The current source has one end coupled to a second supply voltage. Each of the low voltage transistors has a first terminal coupled to the other end of the current source, a second terminal receiving a low voltage signal, and a third terminal. Each of the high voltage transistors has a first terminal coupled to the third terminal of a corresponding one of the low voltage transistors, a second terminal coupled to a bias voltage and a third terminal coupled to the output. The resistor is connected between the third terminals of the high voltage transistors. | 07-02-2009 |
20090168943 | CLOCK GENERATION DEVICES AND METHODS - A clock generation device provided for a transmitter is provided and comprises a clock generator, a calculator and a first phase locked loop (PLL) circuit. The clock generator generates a first clock signal. The calculator calculates a frequency difference between the first and second clock signals. The first PLL circuit generates an output clock signal according to a first reference clock signal related to the first clock signal, and a frequency of the output clock signal is changed according to the frequency difference. The transmitter transmits data according to the output clock signal. | 07-02-2009 |
20090184732 | DIFFERENTIAL DRIVING CIRCUIT CAPABLE OF OPERATING AT LOW SUPPLY VOLTAGE WITHOUT REQUIRING COMMON MODE REFERENCE VOLTAGE - A driving circuit includes a pair of input ports, a pair of differential output ports, a first differential pair, a second differential pair, a load unit, and a current source. The first differential pair is directly connected to a first voltage level, and is coupled to the pair of input ports and the pair of differential output ports. The second differential pair is coupled to the pair of input ports and the pair of differential output ports. The load unit is coupled to the pair of differential output ports. The current source is coupled between the second differential pair and a second voltage level. | 07-23-2009 |
20090237283 | METHOD AND APPARATUS FOR DIGITAL TO ANALOG CONVERSION - A Delta-Sigma DAC and a digital to analog conversion method are provided. A FIR filter receives a shaped digital signal to generate a first current on a first output node, and a second current on a second output node. A current inverter is coupled to the second output node, outputting a reversed current having opposite polarity and identical magnitude of the second current. A current to voltage converter is coupled to the first output node and the output of current inverter, generating an analog signal according to the first and reversed currents. A first current source compensates DC offset for the first current, and a second current source compensates DC offset for the second current. The first and second current sources are implemented by NMOS. | 09-24-2009 |
20090278574 | Frequency Divider, Frequency Dividing Method Thereof, and Phase Locked Loop Utilizing the Frequency Divider - A frequency divider reduces jitter and power consumption, and includes a phase selector for receiving a plurality of clock signals and outputting an intermediate signal corresponding to phase characteristic of at least one of the clock signals, and an adjustable delay circuit for receiving the intermediate signal and generating an output signal by delaying the received intermediate signal. | 11-12-2009 |
20090278579 | Delay Line Calibration Mechanism and Related Multi-Clock Signal Generator - A delay line calibration mechanism includes a delay line, a phase detector, and a controller. The delay line receives an input pulse, a calibration pulse, a first delay selection signal, and a second delay selection signal, delays the input pulse for a delay period according to the first delay selection signal to output a delayed pulse, and delays the calibration pulse for a calibration delay period according to the second delay selection signal to output a delayed calibration pulse. The controller is for generating the input pulse, the calibration pulse, and a reference pulse. The controller also generates the first delay selection signal, and generates the second delay selection signal according to a phase difference signal. The phase detector is for generating the phase difference signal indicating the difference between the delayed calibration pulse and the reference pulse by comparing the delayed calibration pulse and the reference pulse. | 11-12-2009 |
20090289674 | PHASE-LOCKED LOOP - A phase-locked loop includes a phase detector, a charge pump and a controllable oscillator. The phase detector is supplied by a first supply voltage and is utilized for comparing a phase difference between an reference input signal and a feedback signal based on an output signal to generate at least one detect signal. The charge pump is supplied by a second supply voltage, and is utilized for generating a control signal with charge amounts according to the detect signal, where the first supply voltage is different from the second supply voltage. The controllable oscillator is utilized for generating the output signal according to the control signal, wherein a frequency of the output signal is adjusted by the control signal. | 11-26-2009 |
20090296869 | COMMUNICATION SYSTEMS, CLOCK GENERATION CIRCUITS THEREOF, AND METHOD FOR GENERATING CLOCK SIGNAL - A clock generation circuit is provided and includes a phase locked loop (PLL) and a calibrator. The PLL is arranged to receive a first clock signal and generate the output clock signal. The PLL adjusts the frequency of the output clock signal according to a control signal. The calibrator is arranged to receive the output clock signal and a second clock signal, execute a frequency calibration between the output clock signal and the second clock signal, and generate the control signal according to results of the frequency calibration. | 12-03-2009 |
20090296870 | COMMUNICATION SYSTEMS AND CLOCK GENERATION CIRCUITS THEREOF WITH REFERENCE SOURCE SWITCHING - A clock generation circuit for a transmitter which transmits data according to an output clock signal is provided. The clock generation circuit include a clock generator and a phase locked loop (PLL). The clock generator generates a first clock signal. The PLL initially generates the output clock signal according to the first clock signal. When a frequency of the output clock signal generated according to the first clock signal is not within a range required for specification of the transmitter, the PLL switches to generate the output clock signal according to a second clock signal. | 12-03-2009 |
20100259303 | REFERENCE BUFFER CIRCUIT - A reference buffer circuit is provided, comprising a reference buffering stage and a driving stage. The buffering stage provides a first driving voltage based on a first input voltage. The driving stage is driven by the first driving voltage to output a first output voltage. In the buffering stage, a first operational amplifier has a first input end for receiving the first input voltage, a second input end, and an output end for outputting a first tracking voltage. A first level shifter is coupled to the output end of the first operational amplifier, shifting a level of the first tracking voltage to generate the first driving voltage. A first buffering transistor has a drain coupled to a first supply voltage, a source connected to the second input end of the first operational amplifier, and a gate coupled to the first charge pump for receiving the first driving voltage. | 10-14-2010 |
20110043179 | DC-DC Converter - A DC-DC converter providing a DC output voltage at an output node. The DC-DC converter comprises an output stage, a digital controller, and a controller. The output stage comprises a pull-up circuit having a control terminal and coupled between a first fixed voltage and a internal node, a pull-down circuit coupled between the internal node and a second fixed voltage, and a low pass filter coupled between the internal node and the output node. The digital controller is powered by the DC output voltage and adjusts the DC output voltage by controlling the output stage. The controller controls a connection of a feedback path, comprising the digital controller, between the output node and the control terminal according to the DC output voltage. | 02-24-2011 |
20110089985 | Delay Line Calibration Mechanism and Related Multi-Clock Signal Generator - A delay line calibration mechanism includes a first delay line, a second delay line, a phase detector, and a controller. The first delay line receives a first pulse and a first delay selection signal, and delays the first pulse for a first delay period according to the first delay selection signal to output a first delayed pulse. The second delay line receives a second pulse and a second delay selection signal, and delays the second pulse for a second delay period according to the second delay selection signal to output a second delayed pulse. The phase detector generates a phase difference signal indicating the phase difference between the first delayed pulse and the second delayed pulse by comparing the first delayed pulse and the second delayed pulse. The controller generates the second delay selection signal, and generates the first delay selection signal according to the phase difference signal. | 04-21-2011 |
20110122006 | CALIBRATION METHOD AND RELATED CALIBRATION APPARATUS FOR CAPACITOR ARRAY - A capacitor array includes a plurality of capacitor components each having a first node and a second node, and first nodes of the capacitor components are coupled to each other. A calibration method for the capacitor array utilizes a calibration capacitor component to couple the first nodes. Then, the calibration method determines a capacitance indication value regarding the specific capacitor component by coupling different references voltage to a second node of the specific capacitor component and coupling different test voltages to a second node of the calibration capacitor component. Accordingly, the calibration method calibrates the capacitance mismatches of the capacitor array in the digital domain. | 05-26-2011 |
20110254606 | Frequency Divider, Frequency Dividing Method Thereof, and Phase Locked Loop Utilizing the Frequency Divider - A frequency divider reduces jitter and power consumption, and includes a phase selector for receiving a plurality of clock signals and outputting an intermediate signal corresponding to phase characteristic of at least one of the clock signals, and an adjustable delay circuit for receiving the intermediate signal and generating an output signal by delaying the received intermediate signal. | 10-20-2011 |
20120112794 | DIFFERENTIAL DRIVER WITH CALIBRATION CIRCUIT AND RELATED CALIBRATION METHOD - A calibration circuit for calibrating a differential driver with a differential output port including a first output node and a second output node includes: a comparing circuit arranged to receive a first output voltage corresponding to the first output node and a second output voltage corresponding to the second output node, and generate a comparison result according to the first output voltage, the second output voltage, and a predetermined voltage; and a controlling circuit coupled to the comparing circuit, a first resistive element and a second resistive element. The controlling circuit is arranged to adjust the first resistive element and the second resistive element according to the comparison result, wherein the first resistive element is coupled between the first output node and a reference voltage, and the second resistive element is coupled between the second output node and the reference voltage. | 05-10-2012 |
20130009250 | DUMMY PATTERNS FOR IMPROVING WIDTH DEPENDENT DEVICE MISMATCH IN HIGH-K METAL GATE PROCESS - A semiconductor integrated circuit device including: a diffusion area defined by an isolation region in a substrate; a PMOS transistor comprising a metal gate and a high-k dielectric over the diffusion area and source/drain regions sandwiching the metal gate in a first direction; a plurality of dummy diffusion areas surrounding and spaced apart from the diffusion area; and a plurality of first dummy patterns at the two sides of the PMOS transistor in a second direction perpendicular to the first direction and between the dummy diffusion areas and the diffusion area. | 01-10-2013 |