Jou, TW
Amily F. Jou, Taipei TW
Patent application number | Description | Published |
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20160130653 | POLYNUCLEOTIDE PROBE, METHOD FOR DETECTING A TARGET NUCLEIC ACID BY USING THE SAME AND KIT COMPRISING THE SAME - The present invention provides a method for detecting a target nucleic acid that comprises a step of providing a sample; contacting the sample with a polynucleotide probe comprising a first sequence and a second sequence complementary to the target nucleic acid; and adding a nuclease for cleaving the second sequence of the polynucleotide probe. The present invention further provides a polynucleotide probe for detecting a target nucleic acid that comprises a first sequence and a second sequence complementary to the target nucleic acid. Moreover, the present invention provides a kit for detecting a target nucleic acid. | 05-12-2016 |
Chewn-Pu Jou, Hsinchu County TW
Patent application number | Description | Published |
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20140070366 | SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided. The semiconductor structure includes a floating substrate; and a capacitor grounded and connected to the floating substrate. A method of manufacturing a semiconductor structure is also provided. | 03-13-2014 |
20140368285 | VOLTAGE-CONTROLLED OSCILLATOR - An apparatus is disclosed that includes a first cross-coupled transistor pair, a second cross-coupled transistor pair, at least one capacitance unit, and an inductive unit. The first cross-coupled transistor pair and second cross-coupled transistor pair are coupled to a pair of first output nodes and a pair of second output nodes, respectively. The at least one capacitance unit is coupled to at least one of the pair of first output nodes and the pair of second output nodes. The inductive unit is coupled to the first cross-coupled transistor pair at the first output nodes and coupled to the second cross-coupled transistor pair at the second output nodes. The inductive unit generates mutual magnetic coupling between one of the first output nodes and one of the second output nodes and between the other of the first output nodes and the other of the second output nodes. | 12-18-2014 |
Chewn-Pu Jou, Hsinchu TW
Patent application number | Description | Published |
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20110068766 | REFERENCE VOLTAGE GENERATORS, INTEGRATED CIRCUITS, AND METHODS FOR OPERATING THE REFERENCE VOLTAGE GENERATORS - A reference voltage generator includes a proportional to absolute temperature (PTAT) current source and a voltage divider. The PTAT current source is capable of providing a first current that is proportional to a temperature. The voltage divider is capable of receiving a second current that is proportional to the first current. The voltage divider is capable of outputting a reference voltage. The reference voltage is substantially independent from a change of the temperature. | 03-24-2011 |
20110090012 | CIRCUIT AND METHOD FOR RADIO FREQUENCY AMPLIFIER - A radio frequency amplifier circuit includes a substrate that is capable of receiving a substrate bias voltage. The source of a transistor is capable of receiving a source bias voltage. The drain of the transistor is capable of receiving a drain bias voltage. The gate of the transistor is located between the source and the drain. A radio frequency input signal is coupled to the gate. A substrate bias circuit provides the substrate bias voltage. The substrate bias voltage and the source bias voltage forward bias the first diode formed by the source and the substrate. The substrate bias voltage and the drain bias voltage reverse bias the second diode formed by the drain and the substrate. | 04-21-2011 |
20110108950 | VERTICAL METAL INSULATOR METAL CAPACITOR - A capacitor includes a first electrode. The first electrode includes a bottom conductive plane and a plurality of first vertical conductive structures. The bottom conductive plane is disposed over a substrate. The capacitor includes a second electrode. The second electrode includes a top conductive plane and a plurality of second vertical conductive structures. The capacitor includes an insulating structure between the first electrode and the second electrode. The first vertical conductive structures and the second vertical conductive structures are interlaced with each other thereby providing higher capacitance density. | 05-12-2011 |
20110193658 | FILTER USING A WAVEGUIDE STRUCTURE - A representative filter comprises a silicon-on-insulator substrate having a top surface, a metal shielding positioned above the top surface of the silicon-on-insulator substrate, and a band-pass filter device positioned above the metal shielding. The band-pass filter device includes a first port, a second port, and a coupling metal positioned between the first and second ports. | 08-11-2011 |
20110204969 | GATED-VARACTORS - Various embodiments of the invention provide a varactor structure that, depends on configurations, can provide a C-V characteristic based on one or a combination of a reverse bias junction capacitor, a channel capacitor, and an oxide capacitor. The junction capacitor is formed by reverse biasing the P+ source region and the N-well. The channel capacitance is formed between the P+ source region and the N+ drain region, and the oxide capacitor is formed in the gate oxide area. Depending on biasing one or a combination of the gate voltage VG, the source voltage VS, and the drain voltage VD, embodiments can utilize one or a combination of the above capacitors. Other embodiments using the varactors in a Voltage-Controlled Oscillator (VCO) are also disclosed. | 08-25-2011 |
20110215420 | CASCODE CMOS STRUCTURE - A MOS device includes an active area having first and second contacts. First and second gates are disposed between the first and second contacts. The first gate is disposed adjacent to the first contact and has a third contact. The second gate is disposed adjacent to the second contact and has a fourth contact coupled to the third contact. A transistor defined by the active area and the first gate has a first threshold voltage, and a transistor defined by the active area and the second gate has a second threshold voltage. | 09-08-2011 |
20120017192 | METHOD AND APPARATUS FOR LOW POWER SEMICONDUCTOR CHIP LAYOUT AND LOW POWER SEMICONDUCTOR CHIP - A layout system is described comprising a layout unit configured to layout cells in a mask design for a semiconductor chip based on library cells for a specified process node; a non-critical path determination unit configured to determine a non-critical path in the semiconductor chip; a cell determination unit configured to determine a group of cells in the mask design that form a part of the non-critical path and determine the corresponding library cell for at least one of the group of cells; a library cell modifying unit configured to modify one or more corresponding library cells to form a corresponding modified library cell; and a cell replacement unit configured to replace a library cell in the group of cells in the mask design that form a part of the non-critical path with the corresponding modified library cell. | 01-19-2012 |
20120068742 | METHOD AND APPARATUS FOR EFFICIENT TIME SLICING - Apparatus for efficient time slicing including a phase lock loop circuit having a voltage controlled oscillator, an auto-frequency calibration circuit coupled with the phase lock loop circuit configured to output a value to select a range of the voltage controlled oscillator, and a burst mode detector connected with the auto-frequency calibration circuit. The burst mode detector having a register adapted to store the output of the auto-frequency calibration circuit. | 03-22-2012 |
20120092077 | CAPACITOR COUPLED QUADRATURE VOLTAGE CONTROLLED OSCILLATOR - A quadrature oscillator includes a first oscillator having a first second-order harmonic node, a second oscillator having a second second-order harmonic node, and at least one capacitor coupling the first second-order harmonic node and the second second-order harmonic node. The first oscillator is configured to supply an in-phase signal and the second oscillator is configured to supply a quadrature signal. | 04-19-2012 |
20120092121 | BALANCED TRANSFORMER STRUCTURE - A multi-chip electronic device includes a first winding having a first port (P+) and a second port (P−). The first winding is formed in a metal layer of a first chip. The device further includes a second winding having a third (S+) and a fourth port (S−). The second winding is formed in a metal layer of a second chip. A center tap of the second winding is connected to a reference potential. | 04-19-2012 |
20120098592 | FILTER AUTO-CALIBRATION USING MULTI-CLOCK GENERATOR - A filter auto-calibration system includes a multi-clock module. The multi-clock module includes a multi-clock generator that is configured to generate a clock signal with a variable frequency based on a channel setting. There is at least one filter to be calibrated. An auto-calibration control module is configured to control calibration of the at least one filter based on the channel setting. The multi-clock module is configured to supply the variable frequency clock signal to the at least one filter and to the auto-calibration control module, and the at least one filter is coupled to the auto-calibration control module. | 04-26-2012 |
20120122395 | THROUGH CHIP COUPLING FOR SIGNAL TRANSPORT - Through-chip coupling is utilized for signal transport, where an interface is formed between a first coil on a first integrated circuit (IC) chip and a second coil on a second IC chip. The first coil is coupled to an antenna. The second coil is coupled to an amplifier circuit. The second coil is not in direct contact with the first coil. The first coil and the second coil communicatively transmit signals between the antenna and the first amplifier circuit. | 05-17-2012 |
20120262216 | UP-CONVERSION MIXER - According to some embodiments, an up-conversion mixer includes a mixer cell having an output node arranged to provide an output. An input stage is coupled to the mixer cell and arranged to receive an input signal. The mixer cell is configured to generate the output with an up-converted frequency compared to an input frequency of the input signal. The input stage is configured to reduce a third order harmonic term of the output so that an output power plot of the third order harmonic term with respect to an input power has a notch with a local minimum. | 10-18-2012 |
20120319176 | GATED-VARACTORS - In at least one embodiment, a method of manufacturing a varactor includes forming a well over a substrate. The well has a first type doping. A first source region and a second source region are formed in the well, and the first source region and the second source region have a second type doping. A drain region is formed in the well, and the drain region has the first type doping. A first gate region is formed over the well between the drain region and the first source region. Moreover, a second gate region is formed over the well between the drain region and the second source region. | 12-20-2012 |
20130093504 | REFERENCE VOLTAGE GENERATORS, INTEGRATED CIRCUITS, AND METHODS FOR OPERATING THE REFERENCE VOLTAGE GENERATORS - A reference voltage generator is described. The reference voltage generator includes a proportional to absolute temperature (PTAT) current source, the PTAT current source being capable of providing a first current that is proportional to a temperature. The reference voltage generator further includes a current mirror comprising a first transistor and a second transistor, the current mirror configured to generate a second current proportional to the first current, wherein a ratio of the first current to the second current is equal to a ratio of a gate width of the first transistor to a gate width of the second transistor. The reference voltage generator further includes a voltage divider, the voltage divider being capable of receiving the second current, the voltage divider capable of outputting a reference voltage, the reference voltage being substantially independent from a change of the temperature. | 04-18-2013 |
20130120035 | LOCK DETECTOR AND METHOD OF DETECTING LOCK STATUS FOR PHASE LOCK LOOP - A lock detector for a PLL circuit includes a first signal counting circuit, a second signal counting circuit, a comparator, and a lock status unit. The first signal counting circuit is configured to define a plurality of observation periods according to a first oscillating signal and a predetermined cycle value. The second signal counting circuit is configured to determine a maximum counter value according to a second oscillating signal within each of the observation periods, and the second oscillating signal is generated in relation to the first oscillating signal. The comparator is configured to determine, for each of the observation periods, whether the maximum counter value equals the predetermined cycle value. The lock status unit is configured to generate a lock signal based on the maximum counter value being equal to the predetermined cycle value for a predetermined number of consecutive ones of the observation periods. | 05-16-2013 |
20130135011 | PHASE FREQUENCY DETECTOR CIRCUIT - A phase frequency detector circuit includes an edge detector circuit, a plurality of phase frequency detector sub-circuits, and a decision circuit. The edge detector circuit is configured to receive a first input signal and a second input signal. The decision circuit is configured to detect whether a blind condition exits based on outputs of the edge detector circuit and outputs of the plurality of phase frequency detector sub-circuits. Responsive to a result of the decision circuit, a corresponding frequency detector sub-circuit of the plurality of phase frequency detector sub-circuit is configured to provide signals for use in determining a phase difference between the first input signal and the second input signal. | 05-30-2013 |
20130135018 | PHASE-LOCKED LOOPS THAT SHARE A LOOP FILTER - A die stack of an integrated circuit includes a plurality of dies. Each die in the die stack includes a phase lock loop (PLL). The PLLs in each of the dies share a loop filter and other corresponding circuits. | 05-30-2013 |
20130147023 | INTEGRATED CIRCUIT GROUND SHIELDING STRUCTURE - The present disclosure provides an Integrated Circuit (IC) device. The IC device includes a first die that contains an electronic component. The IC device includes second die that contains a ground shielding structure. The IC device includes a layer disposed between the first die and the second die. The layer couples the first die and the second die together. The present disclosure also involves a microelectronic device. The microelectronic device includes a first die that contains a plurality of first interconnect layers. An inductor coil structure is disposed in a subset of the first interconnect layers. The microelectronic device includes a second die that contains a plurality of second interconnect layers. A patterned ground shielding (PGS) structure is disposed in a subset of the second interconnect layers. The microelectronic device includes an underfill layer disposed between the first and second dies. The underfill layer contains one or more microbumps. | 06-13-2013 |
20130154752 | VOLTAGE-CONTROLLED OSCILLATOR - A voltage-controlled oscillator circuit includes a first transistor, a second transistor, a first resonator circuit, a second resonator circuit, a first current path and a second current path. A drain of the first transistor is coupled to a gate of the second transistor and to a first end of the first resonator circuit. A source of the first transistor is coupled to the first current path and to a first end of the second resonator circuit. A drain of the second transistor is coupled to a gate of the first transistor and to a second end of the first resonator circuit. A source of the second transistor is coupled to the second current path and a second end of the second resonator circuit. | 06-20-2013 |
20130241634 | RF CALIBRATION THROUGH-CHIP INDUCTIVE COUPLING - An integrated circuit includes a first chip and a second chip coupled to the first chip in a vertical stack. The first chip includes a radio frequency circuit and a first coil electrically coupled to the radio frequency circuit. The second chip includes a calibration circuit and a second coil electrically coupled to the calibration circuit. The calibration circuit is configured to calibrate the radio frequency circuit disposed on the first chip through inductive coupling between the first and second coils. | 09-19-2013 |
20130278303 | AUTO FREQUENCY CALIBRATION FOR A PHASE LOCKED LOOP AND METHOD OF USE - A phase locked loop includes a phase difference detector configured to receive a reference frequency and a divider frequency and output a phase difference signal. The phase locked loop includes a code generator configured to receive the reference frequency and the phase difference signal, and output a coarse tuning signal and a reset signal. The phase locked loop includes a digital loop filter configured to receive the phase difference signal and output a fine tuning signal. The phase locked loop includes a voltage control oscillator configured to receive the coarse and fine tuning signals, and output an output frequency. The phase locked loop includes a divider configured to receive the reset signal, a divider number control signal and the output frequency, and output the divider frequency. The phase locked loop includes a delta-sigma modulator configured to receive a divisor ratio and the reset signal, and output divider number control signal. | 10-24-2013 |
20140015576 | PHASE-LOCKED LOOPS THAT SHARE A LOOP FILTER - An integrated circuit includes a first die and a second die. The first die comprising a first phase-locked loop (PLL) and the second die comprising a second PLL. The integrated circuit includes a shared loop filter, wherein the first PLL in the first die is combined with the shared loop filter to form a first PLL feedback loop, the second PLL in the second die is combined with the shared loop filter to form a second PLL feedback loop and the shared loop filter is configured to provide configurable bandwidths to each of the first PLL feedback loop and the second PLL feedback loop. | 01-16-2014 |
20140021989 | PHASE-LOCKED LOOPS THAT SHARE A LOOP FILTER AND FREQUENCY DIVIDER - An integrated circuit die stack includes a first die having a first phase locked loop (PLL) and a second die having a second PLL. The first PLL includes a first voltage controlled oscillator (VCO) and the second PLL includes a second VCO. The first VCCO and the second VCCO share a frequency divider and a loop filter. | 01-23-2014 |
20140029205 | Band Pass Filter for 2.5D/3D Integrated Circuit Applications - The present disclosure relates to a device and method for a band pass filter with a reduced cost, area penalty, and manufacturing complexity relative to current solutions. An integrated passive device chip comprising a plurality of capacitors embedded in a common molding compound along with a transceiver chip, and arranged within a polymer package. Ultra-thick metallization layers are disposed within the polymer package and configured to couple the integrated passive device chip to the transceiver chip. The ultra-thick metallization layers also form a plurality of transmission lines, wherein the combined integrated passive device chip and transmission lines form a band pass filter with improved frequency response, noise immunity, and cost and area penalty as compared to conventional solutions. The band pass filter may also be coupled to a plurality of solder balls comprising a Flip Chip Ball Grid Array suitable for 2.5D and 3D integrated circuit applications. | 01-30-2014 |
20140043148 | THREE-DIMENSIONAL INTEGRATED CIRCUIT AND METHOD FOR WIRELESS INFORMATION ACCESS THEREOF - A three-dimensional integrated circuit (3DIC) and wireless information access methods thereof are provided. The proposed 3DIC includes a semiconductor structure, and a wireless power device (WPD) formed on the semiconductor structure for wirelessly receiving a power for operating a function selected from a group consisting of probing the semiconductor structure, testing the semiconductor structure and accessing a first information from the semiconductor structure. | 02-13-2014 |
20140049309 | UP-CONVERSION MIXER HAVING A REDUCED THIRD ORDER HARMONIC - An up-conversion mixer includes a mixer cell having at least one output node configured to generate an output. The up-conversion mixer further includes a first cascaded transconductance input stage coupled to the mixer cell, the first cascaded transconductance input stage configured to receive an input signal and to reduce a third order harmonic of the output. The up-conversion mixer further includes a second cascaded transconductance input stage coupled to the mixer cell, the second cascaded transconductance input stage configured to receive the input signal and to reduce a third order harmonic of the output. | 02-20-2014 |
20140103961 | PHASE FREQUENCY DETECTOR CIRCUIT - A phase frequency detector circuit includes an edge detector circuit, a plurality of phase frequency detector sub-circuits, and a decision circuit. The edge detector circuit is configured to receive a first input signal and a second input signal. The decision circuit is configured to detect whether a blind condition exits based on outputs of the edge detector circuit and outputs of the plurality of phase frequency detector sub-circuits. Responsive to a result of the decision circuit, a corresponding frequency detector sub-circuit of the plurality of phase frequency detector sub-circuit is configured to provide signals for use in determining a phase difference between the first input signal and the second input signal. | 04-17-2014 |
20140111273 | INDUCTOR WITH CONDUCTIVE TRACE - Among other things, an inductor comprising a conductive trace and a method for forming the inductor are provided. The inductor comprises a magnetic structure, such as a ferrite core. A molding material, such as a dielectric, is formed around the magnetic structure. A conductive trace, comprising one or more conductive pillars interconnected by one or more upper interconnects and one or more lower interconnects, is formed around the magnetic structure to form the inductor. The conductive trace allows physical limitations associated with winding a wire to be avoided, and thus allows the inductor to be smaller than wire wound inductors. In one example, the inductor is formed within an integrated circuit package comprising an active device, such as an integrated circuit. In this way, the inductor can be connected to the integrated circuit within the integrated circuit package. | 04-24-2014 |
20140183660 | POWER CELL AND POWER CELL CIRCUIT FOR A POWER AMPLIFIER - A power cell includes a fin over a substrate, the fin extending in a direction substantially perpendicular to a bottom surface of the substrate. The fin includes a first dopant type. The power cell further includes at least one isolation region over the substrate between the fin and an adjacent fin. The power cell further includes a gate structure in contact with the fin and the at least one isolation region, wherein the gate structure comprises a doped region in the fin, wherein the doped region has a second dopant type different from the first dopant type and the doped region defines a channel region in the fin. | 07-03-2014 |
20140184275 | POWER CELL, POWER CELL CIRCUIT FOR A POWER AMPLIFIER AND A METHOD OF MAKING AND USING A POWER CELL - A power cell including an isolation region having a first dopant type formed in a substrate. The power cell further includes a bottom gate having a second dopant type different from the first dopant type formed on the isolation region and a channel layer having the first dopant type formed on the bottom gate. The power cell further includes source/drain regions having the first dopant type formed in the channel layer and a first well region having the second dopant type formed around the channel layer and the source/drain regions, and the first well region electrically connected to the bottom gate. The power cell further includes a second well region having the first dopant type formed around the channel layer and contacting the isolation region and a gate structure formed on the channel layer. | 07-03-2014 |
20140184296 | MCML RETENTION FLIP-FLOP/LATCH FOR LOW POWER APPLICATIONS - The present disclosure relates to a device and method to reduce the dynamic/static power consumption of an MCML logic device. In order to retain register contents during power off mode, an MCML retention latch and flip-flop are disclosed. Retention Latch circuits in MCML architecture are used to retain critical register contents during power off mode, wherein combination logic including clock buffers on the clock tree paths are powered off to reduce dynamic/static power consumption. The MCML retention flip-flop comprises a master latch and a slave latch, wherein a power switch is added to the master latch to power the master latch off during power off mode. The slave latch includes pull-down circuits that remain active to enable the slave latch to retain data at a proper voltage level during power off mode. Other devices and methods are also disclosed. | 07-03-2014 |
20140203881 | Ultra-Low Voltage-Controlled Oscillator with Trifilar Coupling - The present disclosure relates to a device and method to reduce voltage headroom within a voltage-controlled oscillator by utilizing trifilar coupling or transformer feedback with a capacitive coupling technique. In some embodiments of trifilar coupling, a VCO comprises cross-coupled single-ended oscillators, wherein the voltage of first gate within a first single-ended oscillator is separated from the voltage of a second drain within a second single-ended oscillator within the cross-coupled pair. A trifilar coupling network is composed of a drain inductive component, a source inductive component, and a gate inductive component for a single-ended oscillator, wherein a coupling between drain inductive components and gate inductive components between single-ended oscillators along with a negative feedback loop within each single-ended oscillator forms a cross-coupled pair of transistors which reduces the drain-to-source voltage headroom to approximately a saturation voltage of a transistor within the cross-coupled pair. Other devices and methods are also disclosed. | 07-24-2014 |
20140210528 | PHASE LOCKED LOOP (PLL) WITH MULTI-PHASE TIME-TO-DIGITAL CONVERTER (TDC) - One or more techniques or systems for locking a phase locked loop (PLL) are provided herein. In some embodiments, a multi-phase time-to-digital converter (TDC) includes a first phase finder, a phase predictor, a second phase finder, and a phase switch. For example, the first phase finder is configured to generate a first fractional phase signal based on a multi-phase variable clock (CKV) signal. For example, the phase predictor is configured to generate a phase select (QSEL) signal or a multi-phase CKV select (CKVSEL) signal based on a frequency command word (FCW) signal or the multi-phase CKV signal. For example, the second phase finder is configured to generate a second fractional phase signal based on the CKVSEL signal or the QSEL signal. For example, the phase switch is configured to select the first or second fractional phase signal based on a phase error (PHE) signal. | 07-31-2014 |
20140264745 | Transmission Line Formed Adjacent Seal Ring - An integrated circuit device includes a semiconductor body, active components formed over the semiconductor body, one or more seal rings surrounding the active components, and a signal line. One or more of the seal rings are configured to provide the primary return path for current flowing through the signal line. | 09-18-2014 |
20140265632 | MiM CAPACITOR - One or more systems and techniques for managing one or more electronic devices are provided. A determination is made that a first capacitor in a set of one or more capacitors has a defect. Responsive to the determination, the first capacitor is disabled, and a second capacitor is enabled. | 09-18-2014 |
20140266344 | VARAINDUCTOR, VOLTAGE CONTROLLED OSCILLATOR INCLUDING THE VARAINDUCTOR, AND PHASE LOCKED LOOP INCLUDING THE VARAINDUCTOR - A varainductor including a signal line disposed over a substrate. The varainductor further includes a first ground plane over the substrate, the first ground plane disposed on a first side of the signal line, and a second ground plane over the substrate, the second ground plane disposed on a second side of the signal line opposite the first side of the signal line. The varainductor further includes a first floating plane over the substrate, the first floating plane disposed between the first ground plane and the signal line, and a second floating plane over the substrate, the second floating plane disposed between the second ground plane and the signal line. The varainductor further includes an array of switches, the array of switches is configured to selectively connect the first ground plane to the first floating plane, and to selectively connect the second ground plane to the second floating plane. | 09-18-2014 |
20140292400 | FILTER AUTO-CALIBRATION USING MULTI-CLOCK GENERATOR - A filter auto-calibration system comprises a multi-clock module that includes a multi-clock generator configured to generate a first variable frequency signal based on a channel setting, the multi-clock generator comprising a quadrature signal generator configured to generate an in-phase component and a quadrature component of the first variable frequency signal; and a mixer configured to generate an in-phase component and a quadrature component of a quadrature signal from a received signal other than the first variable frequency signal. The system also comprises at least one filter to be calibrated, and an auto-calibration control module coupled to the multi-clock module and the at least one filter, the auto-calibration control module configured to receive the in-phase component and quadrature component of the first variable frequency signal from the multi-clock module, and configured to control calibration of the at least one filter based on the channel setting. | 10-02-2014 |
20140333355 | PHASE-LOCKED LOOPS THAT SHARE A LOOP FILTER AND FREQUENCY DIVIDER - A shared loop filter includes an input port configured to selectively receive a first input from a first charge pump. The first charge pump is connected to a first phase locked loop (PLL) in a first die. The input port is further configured to selectively receive a second input from a second charge pump, the second charge pump connected to a second PLL in a second die separate from the first die. The shared loop filter further includes an output port configured to selectively provide an output to a first voltage controlled oscillator (VCO). The first VCO is connected to the first PLL. The output port is further configured to selectively output a second output to a second VCO. The second VCO is connected to the second PLL. | 11-13-2014 |
20140334063 | VERTICAL METAL INSULATOR METAL CAPACITOR - A method of forming a capacitor comprises forming a first electrode of the capacitor over a substrate. The first electrode includes a bottom conductive plane and a plurality of first vertical conductive structures on the bottom conductive plane. The method also comprises forming an insulating structure over the first electrode. The method further comprises forming a second electrode of the capacitor over the insulating structure. The second electrode includes a top conductive plane and a plurality of second vertical conductive structures under the top conductive plane. The first vertical conductive structures of the plurality of first vertical conductive structures and the second vertical conductive structures of the plurality of second vertical conductive structures are interlaced with each other. | 11-13-2014 |
20150020039 | CASCODE CMOS STRUCTURE - A MOS device includes an active area having first and second contacts. First and second gates are disposed between the first and second contacts. The first gate is disposed adjacent to the first contact and has a third contact. The second gate is disposed adjacent to the second contact and has a fourth contact coupled to the third contact. A transistor defined by the active area and the first gate has a first threshold voltage, and a transistor defined by the active area and the second gate has a second threshold voltage. | 01-15-2015 |
20150130518 | AUTO FREQUENCY CALIBRATION FOR A PHASE LOCKED LOOP AND METHOD OF USE - An apparatus comprises a code generator configured to generate a coarse tuning signal and a reset signal based on a reference frequency and a phase difference signal. The apparatus also comprises a digital loop filter configured to generate a fine tuning signal based on the phase difference signal. The apparatus further comprises a voltage control oscillator configured to generate an output signal based on the coarse tuning signal and the fine tuning signal. The apparatus additionally comprises a divider configured to generate a divider frequency based on a divider control signal and the output signal. The phase difference signal is based, at least in part, on the divider frequency, and the divider is configured to be reset based on the reset signal. | 05-14-2015 |
20150130543 | METHOD AND APPARATUS OF SYNCHRONIZING OSCILLATORS - A circuit includes a first oscillator and a second oscillator. The first oscillator includes an inductive device, a capacitive device, and an active feedback device configured to output a first output signal having a predetermined frequency according to electrical characteristics of the inductive device of the first oscillator and electrical characteristics of the capacitive device of the first oscillator. The second oscillator includes an inductive device, a capacitive device, and an active feedback device configured to output a second output signal having the predetermined frequency according to electrical characteristics of the inductive device of the second oscillator and electrical characteristics of the capacitive device of the second oscillator. The inductive device of the first oscillator and the inductive device of the second oscillator are magnetically coupled. | 05-14-2015 |
20150130545 | COUPLING STRUCTURE FOR INDUCTIVE DEVICE - A circuit includes a coupling structure and a first inductive device. The coupling structure includes two or more conductive loops and a set of conductive paths electrically connecting the two or more conductive loops. The first inductive device is magnetically coupled with a first conductive loop of the two or more conductive loops. | 05-14-2015 |
20150131204 | VERTICAL METAL INSULATOR METAL CAPACITOR - A capacitor structure includes at least two capacitors. A first electrode includes a bottom conductive plane and first vertical conductive structures. The bottom conductive plane is disposed over a substrate. The bottom conductive plane has a first area and a first shape. At least two second electrodes include top conductive planes and second vertical conductive structures. A combined area of the top conductive planes and a gap area between adjacent top conductive planes has a second area and a second shape. The first area and the second area are about the same and the first shape and the second shape are about the same. An insulating structure is disposed between the first electrode and the second electrodes. The first vertical conductive structures and the second vertical conductive structures are interlaced with each other. The capacitors share the bottom conductive plane and have separate top conductive planes. | 05-14-2015 |
20150145612 | ULTRA-LOW VOLTAGE-CONTROLLED OSCILLATOR WITH TRIFILAR COUPLING - The present disclosure relates to a device and method to reduce voltage headroom within a voltage-controlled oscillator by utilizing trifilar coupling or transformer feedback with a capacitive coupling technique. In some embodiments of trifilar coupling, a VCO comprises cross-coupled single-ended oscillators, wherein the voltage of first gate within a first single-ended oscillator is separated from the voltage of a second drain within a second single-ended oscillator within the cross-coupled pair. A trifilar coupling network is composed of a drain inductive component, a source inductive component, and a gate inductive component for a single-ended oscillator, wherein a coupling between drain inductive components and gate inductive components between single-ended oscillators along with a negative feedback loop within each single-ended oscillator forms a cross-coupled pair of transistors which reduces the drain-to-source voltage headroom to approximately a saturation voltage of a transistor within the cross-coupled pair. Other devices and methods are also disclosed. | 05-28-2015 |
20150162921 | CIRCUIT AND OPERATING METHOD OF PLL - A phase locked loop (PLL) includes a voltage controlled oscillator (VCO), a loop filter, and a feedback control unit. The VCO is configured to generate a first oscillating signal and a second oscillating signal according to a VCO control signal. The loop filter is configured to output the VCO control signal by low-pass filtering a signal at an input node of the loop filter. The feedback control unit has an output node coupled to the input node of the loop filter, the feedback control unit is configured to apply a first predetermined amount of current, along a first current direction, to the first feedback control output node during a variable period of time; and to apply one of K second predetermined amounts of current, along a second current direction opposite the first current direction, to the first feedback control output node during a predetermined period of time. | 06-11-2015 |
20150162923 | CIRCUITS AND METHODS OF SYNCHRONIZING DIFFERENTIAL RING-TYPE OSCILLATORS - A circuit includes a first differential ring-type oscillator, a second differential ring-type oscillator, and a coupling structure. The coupling structure capacitively couples the first and second differential ring-type oscillators. A method of synchronizing the first and second differential ring-type oscillators is also disclosed. | 06-11-2015 |
20150188741 | UP-CONVERSION MIXER HAVING A REDUCED THIRD ORDER HARMONIC - An up-conversion mixer includes a mixer cell having at least one output node configured to generate an output. The up-conversion mixer further includes an input stage coupled to the mixer cell, the input stage configured to receive an input signal and to produce a local minimum in a third order harmonic of the output with respect to an input power. The up-conversion mixer further includes a power supply input configured to receive a power supply voltage and a ground, and a maximum number of transistor stages between the power supply input and the ground is two. | 07-02-2015 |
20150214892 | FINFET VARACTOR - The present disclosure relates to a FinFET varactor circuit having one or more control elements that control a relationship between capacitance and voltage of a FinFET MOS varactor without introducing changes to process parameters used in fabrication of the FinFET MOS varactor. In some embodiments, the FinFET varactor circuit has a FinFET MOS varactor with a first terminal connected to a gate terminal of the FinFET MOS varactor and a second terminal connected to connected source and drain terminals of the FinFET MOS varactor. One or more control elements are connected to the first or second terminals of the FinFET MOS varactor and vary one or more operating characteristics of the FinFET MOS varactor. Using the control elements to vary the operating characteristics of the FinFET MOS varactor, allows for the characteristics to be adjusted without making changes to process parameters used in the fabrication of the FinFET MOS varactor. | 07-30-2015 |
20150249051 | THREE DIMENSIONAL CIRCUIT INCLUDING SHIELDED INDUCTOR AND METHOD OF FORMING SAME - The three dimensional (3D) circuit includes a first tier including a semiconductor substrate, a second tier disposed adjacent to the first tier, a three dimensional inductor including an inductive element portion, the inductive element portion including a conductive via extending from the first tier to a dielectric layer of the second tier. The 3D circuit includes a ground shield surrounding at least a portion of the conductive via. In some embodiments, the ground shield includes a hollow cylindrical cage. In some embodiments, the 3D circuit is a low noise amplifier. | 09-03-2015 |
20150311160 | SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF - A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a first dielectric layer surrounding a first transmission line and a magnetic layer surrounding the first dielectric layer. The magnetic layer increases the inductance of the transmission line. The semiconductor arrangement having the magnetic layer surrounding the first transmission line has increased impedance, which promotes current flow through the transmission line, without having increased resistance as compared to a semiconductor arrangement that does not have a magnetic layer. Increased resistance requires increased power, which results in a shorter semiconductor arrangement life span than the semiconductor arrangement without the increased resistance. | 10-29-2015 |
20150323589 | COMPOSITE INTEGRATED CIRCUITS AND METHODS FOR WIRELESS INTERACTIONS THEREWITH - A composite integrated circuit (IC) includes a first circuit layer, a second circuit layer having a first chip and a second chip, and a first wireless power transfer (WPT) device in the first chip or the first circuit layer. The first WPT device generates a power supply voltage by extracting energy from an electromagnetic signal. A first tracking circuit in the second chip or the first circuit layer is powered by the power supply voltage from the first WPT device and stores or outputs tracking data in response to an instruction extracted from the electromagnetic signal. | 11-12-2015 |
20150371772 | INDUCTOR WITH CONDUCTIVE TRACE - Among other things, a method for forming an inductor is provided. The method includes forming an insulating layer on a carrier. The method includes forming a trench in the insulating layer. The method also includes forming a magnetic structure within the trench. The method includes forming a conductive trace around the magnetic structure to form the inductor. | 12-24-2015 |
20160049912 | BANDGAP REFERENCE CIRCUIT - An integrated circuit comprises a first doped region and a second doped region in a substrate. The second doped region is separated from the first doped region by a first spacing. The integrated circuit further comprises a dielectric layer over the substrate and a gate over the dielectric layer. The gate is positioned having the first doped region on a first substrate side of the gate and the second doped region on a second substrate side of the gate opposite the first substrate side of the gate. The integrated circuit also comprises a third doped region in the substrate separated from the first doped region by a second spacing. The integrated circuit further comprises a fourth doped region in the substrate. The gate and the third doped region are coupled with a first voltage supply, and the fourth doped region is coupled with a second voltage supply. | 02-18-2016 |
20160056228 | CAPACITOR HAVING A GRAPHENE STRUCTURE, SEMICONDUCTOR DEVICE INCLUDING THE CAPACITOR AND METHOD OF FORMING THE SAME - A capacitor includes a first graphene structure having a first plurality of graphene layers. The capacitor further includes a dielectric layer over the first graphene structure. The capacitor further includes a second graphene structure over the dielectric layer, wherein the second graphene structure has a second plurality of graphene layers. | 02-25-2016 |
20160071805 | INTERPOSER AND SEMICONDUCTOR PACKAGE WITH NOISE SUPPRESSION FEATURES - Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise. | 03-10-2016 |
20160077293 | DIFFERENTIAL SILICON INTERFACE FOR DIELECTRIC SLAB WAVEGUIDE - The present disclosure relates to an integrated chip having differential coupling elements that couple electromagnetic radiation having a frequency outside of the visible spectrum between a silicon substrate and a dielectric waveguide overlying the silicon substrate. In some embodiments, the integrated chip has a dielectric waveguide disposed within an inter-level dielectric (ILD) material overlying a semiconductor substrate. A differential driver circuit generates a differential signal having a first transmission signal component at a first output node and a complementary second transmission signal component at a second output node. A first transmission electrode located along a first side of the dielectric waveguide receives the first transmission signal component from the first output node, and a second transmission electrode located along a second side of the dielectric waveguide receives the complementary second transmission signal component from the second output node. | 03-17-2016 |
20160077294 | SILICON INTERFACE FOR DIELECTRIC SLAB WAVEGUIDE - The present disclosure relates to an integrated chip having coupling elements that couple electromagnetic radiation having a frequency outside of the visible spectrum between a silicon substrate and a dielectric waveguide overlying the silicon substrate. In some embodiments, the integrated chip has a dielectric waveguide disposed within an inter-level dielectric (ILD) material overlying a semiconductor substrate. A first coupling element couples a first electrical signal generated by a driver circuit disposed within the semiconductor substrate to a first end of the dielectric waveguide as electromagnetic radiation having a frequency outside of the visible spectrum. A second coupling element couples the electromagnetic radiation from a second end of the dielectric waveguide to a second electrical signal. By coupling electromagnetic radiation having a frequency outside of the visible spectrum to and from the dielectric waveguide, the disclosed integrated chip is able to overcome a number of drawbacks of optical integrated waveguides. | 03-17-2016 |
Chewn-Pu Jou, Hsinchu-City TW
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20140266512 | CMOS BAND-PASS FILTER - A band-pass filter is provided that is configured to output a signal with a frequency within a desired frequency range and to attenuate signals with frequencies outside the desired frequency range. The band-pass filter comprises a CMOS resonator that comprises a resonator cavity and a reflector. The band-pass filter also comprises an impedance convertor that is configured to inhibit at least some insertion losses on the band-pass filter. The band-pass filter also comprises a variable capacitor that is connected between the CMOS resonator and the impedance convertor. The desired frequency range of the band-pass filter can be tuned by adjusting the capacitance of the variable capacitor. | 09-18-2014 |
20150116018 | PHASE-LOCKED LOOP CIRCUIT - A phase-locked loop circuit, a phase converter module thereof and a phase-locked controlling method are disclosed herein. The phase converter module is suitable for a phase-locked loop circuit including a digitally-controlled oscillator (DCO) for generating an oscillator output signal and a divider for converting the oscillator output signal into N-phased oscillator output signals. The phase converter module includes a period extender, a phase finder and a time-to-digital converter. The period extender is configured for extending the N-phased oscillator output signals into M*N-phased oscillator output signals corresponding to M oscillation period of the digitally-controlled oscillator. The phase finder is configured for sampling the oscillator output signal with the M*N-phased oscillator output signals to calculate an estimated value of the fractional phase part. The time-to-digital converter is configured to calculate a precise value of the fractional phase part within one sub-period. | 04-30-2015 |
20150236644 | VOLTAGE-CONTROLLED OSCILLATOR - An apparatus is disclosed that includes a first cross-coupled transistor pair, a second cross-coupled transistor pair, at least one capacitance unit, and a first, second, third, and fourth inductive elements. The first cross-coupled transistor pair and second cross-coupled transistor pair are coupled to a pair of first output nodes and a pair of second output nodes, respectively. The at least one capacitance unit is coupled to at least one of the pair of first output nodes and the pair of second output nodes. The first and second inductive elements are electrically coupled to the first output nodes, respectively. The third inductive element is electrically coupled to one of the second output nodes and DC-biased and magnetically coupled to the first inductive element. The fourth inductive element is electrically coupled to the other of the second output nodes and DC-biased and magnetically coupled to the second inductive element. | 08-20-2015 |
20160133686 | VERTICAL METAL INSULATOR METAL CAPACITOR - A semiconductor device and a method are disclosed herein. The semiconductor device includes a device die, a molding layer surrounding the device die, a plurality of first vertical conductive structures formed within the molding layer, and a plurality of second vertical conductive structures formed within the molding layer. The first vertical conductive structures and the second vertical conductive structures are interlaced with each other, and an insulating structure is formed between the first vertical conductive structures and the second vertical conductive structures. | 05-12-2016 |
Chewn-Pu Jou, Chutung TW
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20110186909 | ESD PROTECTION CIRCUIT FOR RFID TAG - An electrostatic discharge (ESD) protection circuit structure includes a dual directional silicon controlled rectifier (SCR) formed in a substrate. The SCR includes first and second P-wells laterally interposed by an N-well. A deep N-well is disposed underneath the P-wells and the N-well. First and second N-type regions are disposed in the first and second P-wells, respectively, and are coupled to a pair of pads. First and second P-type regions are disposed in the first and second P-wells, respectively, are coupled to the pads, and are disposed closer to the N-well than the first and second N-type regions, respectively. | 08-04-2011 |
20110233678 | JUNCTION VARACTOR FOR ESD PROTECTION OF RF CIRCUITS - An ESD protection device includes a first well of a first semiconductor type disposed in a substrate of a second semiconductor type forming a first diode. A second well of the second semiconductor type is formed in the substrate to form a second diode with the first well. A first plurality of doped regions of the first semiconductor type are formed in an upper surface of the first well. A second plurality of doped regions of the second semiconductor type are formed in the upper surface of the first well forming a third diode with the first well. A plurality of STI regions are formed in the upper surface of the first well. Each STI region is disposed between a doped region of the first and second semiconductor types. The third diode provides a current bypass when an ESD voltage spike is received at one of the first or second plurality of doped regions. | 09-29-2011 |
20110260819 | CONTINUOUSLY TUNABLE INDUCTOR WITH VARIABLE RESISTORS - An integrated tunable inductor includes a primary inductor having a plurality of inductor turns, at least one closed loop eddy current coil proximate the primary inductor, and at least one variable resistor integrated in series with the eddy current coil. | 10-27-2011 |
20110304372 | METHOD AND APPARATUS FOR AMPLIFYING A TIME DIFFERENCE - A time amplifier circuit has first and second inverters and first and second pull-down paths. Each inverter includes a first NMOS transistor and a first PMOS transistor. A source of the first NMOS transistor is coupled to a ground node directly or through a first additional NMOS transistor having a gate coupled to a respective input node. The first and second inverters are coupled to first and second input nodes and to first and second output nodes, respectively. The first pull-down path is from the first output node to the ground node and is enabled in response to the first input signal and the second output signal being high. The second pull-down path is from the second output node to ground and is enabled in response to the second input signal and the first output signal being high. | 12-15-2011 |
20120019968 | TRANSMISSION-LINE-BASED ESD PROTECTION - An ESD protection circuit includes a signal pad, a short circuited shunt stub on-chip with and coupled to the signal pad, an open circuited shunt stub on-chip and coupled to the signal pad. | 01-26-2012 |
20120032742 | CMOS MILLIMETER-WAVE VARIABLE-GAIN LOW-NOISE AMPLIFIER - A low-noise amplifier (LNA) includes a first cascode gain stage coupled to an input node for increasing an amplitude of an RF input signal. A first variable gain network is coupled to the first cascode gain stage and includes a first inductor for boosting a gain of the first cascode gain stage, a first capacitor coupled to the first inductor for blocking a direct current (DC) voltage, and a first switch coupled to the first inductor and to the first capacitor. The first switch is configured to selectively couple the first inductor to the first cascode gain stage in response to a first control signal. | 02-09-2012 |
20120032743 | LOW-NOISE AMPLIFIER WITH GAIN ENHANCEMENT - A low-noise amplifier (“LNA”) includes a first cascode gain stage including a first complementary metal oxide semiconductor (“CMOS”) transistor configured to receive a radio frequency (“RF”) input signal and a second CMOS transistor coupled to an output node. The first inductive gate network is coupled to a gate of the second CMOS transistor for increasing a gain of the first cascode gain stage. The first inductive gate network has a non-zero inductive input impedance and includes at least one passive circuit element. | 02-09-2012 |
20120056769 | METHOD AND SYSTEM FOR TIME TO DIGITAL CONVERSION WITH CALIBRATION AND CORRECTION LOOPS - Methods and apparatuses for time to digital conversion (TDC) are disclosed. A timing circuit comprises a TDC circuit, a calibration module, and a correction module. The TDC circuit is configured to provide a timing signal indicative of a timing difference between edges of a periodic reference clock signal and a variable feedback signal. The TDC circuit is also configured to provide a delay signal that is variably delayed relative to the reference clock signal. The calibration module is configured to provide a calibration signal to increase and decrease a total delay of the TDC circuit based on a time delay of the calibration signal plus a time delay of a correction signal. The correction module, which is configured to receive the timing signal and provide the correction signal, minimizes harmonic spurs in a frequency response of the timing signal by operating at a frequency of the reference clock signal. | 03-08-2012 |
20120068745 | INJECTION-LOCKED FREQUENCY DIVIDER - A representative injection-locked frequency divider includes a differential direct injection pair that is configured to receive and mix differential injection signals and an oscillator that is electrically connected to the differential direct injection pair and produces an operating frequency based on the mixed differential injection signals. | 03-22-2012 |
20120146747 | MILLIMETER-WAVE WIDEBAND FREQUENCY DOUBLER - A millimeter-wave wideband frequency doubler stage for use in a distributed frequency doubler includes: a differential input pair of transistors, each transistor having respective gate, drain and source terminals, wherein the source terminals are coupled together to a first power supply node and the drain terminals are coupled together at a first node to a second power supply node; first and second pairs of bandpass gate lines coupled to the gate terminals of the transistors; and a pair of bandpass drain lines coupled to the drain terminals of the transistors. | 06-14-2012 |
20130134553 | INTERPOSER AND SEMICONDUCTOR PACKAGE WITH NOISE SUPPRESSION FEATURES - Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise. | 05-30-2013 |
20130271223 | AMPLIFIER WITH FLOATING WELL - A low-noise amplifier includes a first transistor having a gate configured to receive an oscillating input signal and a source coupled to ground. A second transistor has a source coupled to a drain of the first transistor, a gate coupled to a bias voltage, and a drain coupled to an output node. At least one of the first and second transistors includes a floating deep n-well that is coupled to an isolation circuit. | 10-17-2013 |
20130320553 | NOVEL BEAD FOR 2.5D/3D CHIP PACKAGING APPLICATION - An integrated circuit package having a multilayer interposer has one or more metal wiring beads provided in the interposer, each of the one or more metal wiring beads has a convoluted wiring pattern that is formed in one of the multiple layers of wiring structures in the interposer, and two terminal end segments connected to the power lines in the integrated circuit package, wherein the one or more metal wiring beads operate as power noise filters. | 12-05-2013 |
20140001609 | INTERPOSER AND SEMICONDUCTOR PACKAGE WITH NOISE SUPPRESSION FEATURES | 01-02-2014 |
20140252546 | SWITCHED CAPACITOR STRUCTURE - A capacitor structure comprising semiconductor substrate and a matrix of capacitor units formed over the semiconductor substrate each capacitor unit. The matrix includes an interior structure comprised of one or more vertical plates, each vertical plate of the interior structure formed from a plurality of conductive portions connected vertically to each other, an exterior structure comprised of one or more vertical plates, each vertical plate of the exterior structure formed from a plurality of conductive portions connected vertically to each other, the exterior structure substantially encompassing the interior structure, and insulative material separating the interior and exterior structures. The structure also comprises a switching mechanism included in the capacitor structure to switch between ones of the plural capacitor units. | 09-11-2014 |
20140266419 | VOLTAGE CONTROLLER FOR RADIO-FREQUENCY SWITCH - One or more systems and techniques for limiting a voltage potential between an antenna and a radio-frequency switch circuit are provided. A voltage controller comprises a voltage generator, a voltage detection circuit and a switch cell. The voltage detection circuit is coupled to the voltage generator and to the switch cell, and the switch cell is coupled to a voltage source, and to a node between the radio-frequency switch circuit and the antenna. When the voltage potential exceeds a specified threshold, the voltage generator produces a voltage which the voltage detection circuit measures such that the voltage detection circuit activates the switch cell, resulting in a short circuit between the radio-frequency switch circuit and the voltage source. This serves to inhibit the voltage potential from exceeding the specified threshold, for example. | 09-18-2014 |
20150014786 | HIGH PERFORMANCE POWER CELL FOR RF POWER AMPLIFIER - A power cell designed for an RF power amplifier comprises an enhancement MOSFET formed in an P-Well in an P-Substrate and a depletion or Schottky MOSFET formed in an N-Well in the same P-Substrate with a horizontal or a vertical channel between the source, drain, and gate electrodes of the depletion or Schottky MOSFET. The source node of the enhancement MOSFET and source node of the depletion or Schottky MOSFET are connected together to form the power cell. | 01-15-2015 |
20150015336 | CMOS CASCODE POWER CELLS - A circuit includes a first CMOS device forming a gain stage of a power amplifier and a second CMOS device forming a voltage buffer stage of the power amplifier. The first CMOS device includes a first doped well formed in a substrate, a first drain region and a first source region spaced laterally from one another in the first doped well, and a first gate structure formed over a first channel region in the first doped well. The second CMOS device includes a second doped well formed in the semiconductor substrate such that the first doped well and the second is disposed adjacent to the second doped well. A second drain region and a second source region are spaced laterally from one another in the second doped well, and a second gate structure formed over a second channel region in the second doped well. | 01-15-2015 |
20150084158 | THREE DIMENSIONAL CIRCUIT INCLUDING SHIELDED INDUCTOR AND METHOD OF FORMING SAME - The three dimensional (3D) circuit includes a first tier including a semiconductor substrate, a second tier disposed adjacent to the first tier, a three dimensional inductor including an inductive element portion, the inductive element portion including a conductive via extending from the first tier to a dielectric layer of the second tier. The 3D circuit includes a ground shield surrounding at least a portion of the conductive via. In some embodiments, the ground shield includes a hollow cylindrical cage. In some embodiments, the 3D circuit is a low noise amplifier. | 03-26-2015 |
20150205267 | TUNABLE DELAY CELLS FOR TIME-TO-DIGITAL CONVERTER` - A time-to-digital converter (TDC) comprises a first delay line including a plurality of first delay cells connected in series, wherein each of the first delay cells include a plurality of first delay units connected in series, wherein each of the first delay units includes a tunable PMOS transistor, a first poly on oxide definition (OD) edge (PODE) transistor, and a pull-up PMOS transistor. The TDC further comprises a second delay line including a plurality of second delay cells connected in series, wherein each of the second delay cells include a plurality of second delay units connected in series, wherein each of the second delay units includes a tunable NMOS transistor, a second PODE transistor, and a pull-down NMOS transistor. | 07-23-2015 |
Chew-Pu Jou, Chutung TW
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20130163127 | ESD PROTECTION CIRCUIT - An electrostatic discharge protection circuit includes an input node coupled to receive an input signal and an output node coupled to output the input signal to an internal circuit. A first inductor is coupled to the input node and to the output node, and a second inductor is coupled to the output node and to a first power supply node through a resistance. A plurality of protection devices are coupled to the first and second inductors and are disposed in parallel with each other. | 06-27-2013 |
Chon-Shin Jou, Hsinchu TW
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20140327038 | POWER SEMICONDUCTOR AND MANUFACTURING METHOD THEREOF - A power semiconductor includes a semiconductor substrate, a metal oxide semiconductor layer, a N-type buffer layer and a P-type injection layer. The semiconductor substrate has a first surface and a second surface. The metal oxide semiconductor layer is formed on the first surface for defining a N-type drift layer of the semiconductor substrate. The N-type buffer layer is formed on the second surface through ion implanting, and the P-type injection layer is formed on the N-type buffer layer through ion implanting. By utilizing the semiconductor substrate having drift layer and forming the N-type buffer layer and the P-type injection layer on the second surface of the semiconductor substrate through ion implanting, the ion concentration is adjustable. As a result, the electron hole injection efficiency and the width of depletion region are easily adjusted, the fabricating processes are simplified, and the fabricating time and cost are reduced. | 11-06-2014 |
Dze-Min Jou, Taipei City TW
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20150143361 | SOFTWARE ROAMING SYSTEM, METHOD AND COMPUTER READABLE STORAGE MEDIUM THEREOF - A software roaming system, method and a computer readable storage medium thereof are disclosed herein. The software roaming system includes a first electronic device having a plurality of widget software. The first electronic device includes a device description data. The device description data includes virtual units corresponding to the widget software, wherein the first electronic device establishes the virtual units in accordance with a universal plug and play (UPNP) protocol. The first electronic device searches a second electronic device through an network in accordance with the UPNP protocol and copies a first widget software of the widget software and a runtime data thereof to the second electronic device, and thus the second electronic device installs the first widget software and recovers the runtime data. | 05-21-2015 |
20150145721 | METHOD OF POSITIONING AND ELECTRONIC APPARATUS USING THE SAME - An electronic apparatus includes a selection unit, a storage unit and a processing unit. The selection unit and the storage unit are coupled to the processing unit. The selection unit selects a first reference point proximate to the electronic apparatus. The storage unit stores a plurality of second locations of a plurality of second reference points. The processing unit executes a single-point distance measurement between the electronic apparatus and a first location of the selected first reference point, provides the electronic apparatus auxiliary positioning information by selecting the second locations stored in the storage unit and generates a speculative location of the electronic apparatus by further computing the results of the single-point distance measurement and the auxiliary positioning information. | 05-28-2015 |
20150149389 | ELECTRICITY LOAD MANAGEMENT DEVICE AND ELECTRICITY LOAD MANAGEMENT METHOD THEREOF - An electricity load management device and an electricity load management method thereof are provided. The electricity load management device is connected to a plurality of data centers via a network. Each of the data centers comprises at least one server. For each data center, the electricity load management device allocates a plurality of data allocation percents of a plurality of service requests sequentially according to a schedule so as to receive a piece of electricity consumption information from each data center. The electricity load management device creates a cost profile of each data center according to the electricity consumption information of each data center, and determines an electricity load allocation percent of each data center according to the cost profiles and the electricity charge information. Finally, the electricity load management device allocates the subsequent service requests to the data centers according to the electricity load allocation percents. | 05-28-2015 |
Fan-Di Jou, Taoyuan County TW
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20090167866 | METHODS AND SYSTEMS FOR IMAGE PROCESSING IN A MULTIVIEW VIDEO SYSTEM - A system for image processing in a multiview video environment including a first camera and a second camera is disclosed. The system comprises a region of interest (ROI) module configured to receive first video signals from the first camera and detect at least one ROI in a first image related to the first video signals, a first lookup table configured to generate an attribute value in response to a type of a block, wherein the type of a block is related to a first vanishing point defined in the first image, a labeling module configured to identify a first point “p” most close to the first vanishing point, a second point “q” most remote to the first vanishing point and a length “h” between the first point “p” and the second point “q” in each of the at least one ROI, and generate first information on p, q and h, a second lookup table configured to generate second information on p′, q′ and h′ in response to the first information, wherein p′ is a first point most close to a second vanishing point defined in a second image related to the second camera, q′ is a second point most remote to the second vanishing point and h′ is a length between the first point p′ and the second point q′ in each of at least one ROI in the second image, and a transforming module configured to transform each of the at least one ROI in the first image into an ROI in the second image based on the second lookup table. | 07-02-2009 |
Fan-Di Jou, Chiayi City TW
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20110113079 | INFORMATION SWITCH MODULE AND RELATED FILE TRANSFER METHOD - An information switch module and a related file transfer method are disclosed. The information switch module is coupled to a first and a second host. The information switch module includes a switch and a storage device, and the switch includes at least a system controller, a first and a second USB controllers and an input device connection module. The system controller uses the storage device to simulate at least two USB mass storage device, and sets up an output storage space and an input storage space in the at least two USB mass storage devices, respectively. The first and second hosts access the output storage space and the input storage space through the first and second USB controllers, respectively. After the first host stores a file into the output storage space, the system controller provides a corresponding data of the file to the input storage space for the second host. | 05-12-2011 |
Fan-Di Jou, Hsinchu County TW
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20150189333 | METHOD AND SYSTEM FOR IMAGE PROCESSING, DECODING METHOD, ENCODER, AND DECODER - Image processing and decoding methods for intra block copy and a system, encoder and decoder thereof are provided. The image processing method includes dividing a coding unit in an encoding frame into a plurality of sub-blocks, wherein the size of the coding unit is 2N×2N, and the size of the sub-blocks is N×2N or 2N×N, wherein N is a positive integer. The image processing method also includes searching a reference block corresponding to one of the sub-blocks within a searching range in the encoding frame and recording a relative position between the one of the sub-blocks and the reference block corresponding to the one of the sub-blocks. The image processing method further includes encoding the one of the sub-blocks according to the relative position. | 07-02-2015 |
Fan-Di Jou, Hsinchu TW
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20120250758 | METHOD AND APPARATUS FOR FRAME MEMORY COMPRESSION - A method for frame memory compression divides each of a plurality of image frames in a frame memory into a plurality of blocks for taking a block as a compression unit. It quantizes a plurality of pixel values inside the block according to a predefined parameter, thereby generating a quantized block and a plurality of removed bits from the binary representation of the plurality of pixel values. A predictor is used to produce a residual block for the quantized block. A variable length encoder takes the residual block as an input and produces a coded bitstream. A packing unit is used to take the coded bitstream and the number of removed bits generated by the quantizer as inputs, so as to produce an entire codeword sequence of the block that meets a target bit rate by using a structure called group of blocks (GOB) to flexibly share available spaces of the blocks in the same GOB. | 10-04-2012 |
Geng-Shing Jou, Taoyuan County TW
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20090245152 | POWER MANAGING METHOD APPLIED TO A WIRELESS NETWORK APPARATUS AND POWER MANAGEMENT THEREOF - A power managing method applied to a wireless network apparatus includes the steps of periodically detecting whether the wireless network apparatus is operated in a non-link status to determine whether to enter a first power-saving mode when the wireless network apparatus powered on; and determining the wireless network apparatus whether to enter a second power-saving mode according to an information of a beacon received by the wireless network apparatus when the wireless network apparatus is operated in a link status. When the wireless network apparatus is detected to be operated in the non-link status, control the wireless network apparatus to enter the first power-saving mode by a power mode controlling circuit. The first power-saving mode is an inactive power-saving mode, and the second power-saving mode is a linked power-saving mode. | 10-01-2009 |
I-Ming Jou, Tainan TW
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20140370015 | USE OF IL-20 ANTAGONISTS FOR ALLEVIATING SPINAL CORD INJURY - Alleviating neural injury, such as spinal cord injury, in a subject (e.g., a human subject) in need of the treatment using an IL-20 antagonist, which can be an antibody that blocks a signaling pathway mediated by IL-20. Such antibodies include anti-IL-20 antibodies and anti-IL-20R antibodies that specifically block the IL-20 signaling pathway. | 12-18-2014 |
I-Ming Jou, Tainan City TW
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20140128984 | ARTIFICIAL IMPLANT FOR CARPOMETACARPAL JOINT - An artificial implant for a carpometacarpal (CMC) joint used for replacing a CMC joint surface of the first metacarpal bone is provided and includes: an insert portion having an inserting end for inserting into a bone marrow cavity exposed from an incision of the first metacarpal bone, and a front end; an articular replacement portion connected to the front end of the inserting portion and disposed outside the incision of the first metacarpal bone, and having an articular profile surface to replace the CMC joint surface of the first metacarpal bone; and an attached flange protruded from a peripheral of the articular replacement portion, attached to an outer bone surface of the first metacarpal bone adjacent to the incision, and having at least one suture hole, through which at least one suture passes for assisting to fix an abductor pollicis longus (APL) to the outer bone surface. | 05-08-2014 |
20150297355 | ARTIFICIAL IMPLANT FOR CARPOMETACARPAL JOINT - An artificial implant for a carpometacarpal (CMC) joint used for replacing a CMC joint surface of the first metacarpal bone is provided and has: an insert portion having an inserting end for inserting into a bone marrow cavity exposed from an incision of the first metacarpal bone, and a front end; an articular replacement portion connected to the front end of the inserting portion and disposed outside the incision of the first metacarpal bone, and having an articular profile surface to replace the CMC joint surface of the first metacarpal bone; and an attached flange protruded from a peripheral of the articular replacement portion, attached to an outer bone surface of the first metacarpal bone adjacent to the incision, and having at least one suture hole, through which at least one suture passes for assisting to fix an abductor pollicis longus (APL) to the outer bone surface. | 10-22-2015 |
20160100848 | AUXILIARY JIG FOR TRAPEZIOMETACARPAL JOINT ARTHROPLASTY - An auxiliary jig for a trapeziometacarpal joint arthroplasty is disclosed. The jig has a body, two grip portions, and a positioning portion. The positioning portion has a plurality of positioning holes so that pins can be fixed on the first metacarpal bone through the positioning holes. The jig can provide accurate positioning operations for cutting and drilling during a trapeziometacarpal joint arthroplasty. | 04-14-2016 |
20160106545 | ARTIFICIAL IMPLANT FOR TRAPEZIOMETACARPAL JOINT - An artificial implant for a trapeziometacarpal joint is provided. The artificial implant has a joint replacement portion and at least two insertion rods. The insertion rods of the artificial implant can help to decrease the wound area during the implantation of the artificial implant in order to accelerate the speed of tendon reattachment after implanting and to enhance the ability of anti-rotation. | 04-21-2016 |
Jau-Ji Jou, Taipei City TW
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20100322624 | BIDIRECTIONAL TRANSMISSION NETWORK APPARATUS BASED ON TUNABLE RARE-EARTH-DOPED FIBER LASER - The present invention discloses a bidirectional transmission network apparatus based on a tunable rare-earth-doped fiber laser source. It is useful in wavelength-division-multiplexing access networks. The fiber ring laser not only generates downstream data traffic but also serves as the wavelength-selecting injection light source for the Fabry-Pérot lasers (or vertical cavity surface emitting lasers) located at the subscriber site. The fiber laser is constructed based on optical filtering, polarization control and noise suppression techniques. | 12-23-2010 |
Jia-Guei Jou, Taipei City TW
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20130239072 | MASK MAKING WITH ERROR RECOGNITION - A method of making a mask includes receiving an IC design layout from a designer, applying an logic operation (LOP) correction, performing an OPC correction, fracturing the modified data into a plurality of main features in an electron beam format, and sending the electron beam format data to a mask writer for a mask fabrication. An XOR operation is implemented into the method to check and verify if a pattern is lost during OPC modification and/or data fracture. A BACKBONE XOR operation is also implemented into the method for a plurality of main features with a critical dimension (CD) size smaller than the max OPC correction to check and verify if a small pattern feature is lost during OPC modification and/or data fracture for 45 nm and beyond semiconductor technologies. | 09-12-2013 |
Jia-Guei Jou, New Taipei City TW
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20130042210 | CYCLE TIME REDUCTION IN DATA PREPARATION - The present disclosure provides for methods of reducing cycle time in data preparation. In one embodiment, a method includes receiving an initial integrated circuit (IC) design layout and an optical proximity correction (OPC)-processed initial IC design layout, and receiving a revised IC design layout. The method further includes comparing the revised IC design layout to the initial IC design layout to identify a difference region of the revised IC design layout from the initial IC design layout, performing an OPC on the difference region of the revised IC design layout, and merging the OPC-processed difference region of the revised IC design layout with the OPC-processed initial IC design layout. | 02-14-2013 |
20130268901 | Structure and Method for E-Beam Writing - The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a main feature; performing an optical proximity correction (OPC) process to the design layout; and thereafter, performing a jog reduction process to the design layout such that jog features of the design layout are reduced. | 10-10-2013 |
20150040082 | LAYOUT DECOMPOSITION METHOD - A method of assigning layout patterns includes identifying a first set of layout patterns of a current layout design that is new or has been modified in comparison with a reference layout design. A second set of layout patterns of the current layout design is identified. A member of the second set of layout patterns that is not a member of the first set of layout patterns has a distance, less than a predetermined threshold distance, to at least another member of the second set of layout patterns. A third set of layout patterns is not modified in comparison with the reference layout design. The third set of layout patterns is assigned to a plurality of masks according to the reference pattern-assigning result. | 02-05-2015 |
20160070843 | APPARATUS AND METHOD FOR E-BEAM WRITING - A method of preparing mask data, the method begins with performing a logic operation to a design layout, and an optical proximity correction (OPC) is performed to the design layout to form an OPC feature. The OPC feature has a first jog and a second jog on a line, and the first jog is larger than the second jog in width. The OPC feature is resized to form a resized first jog and a resized second jog on the line if a width ratio of the first jog to the second jog being smaller than a predetermined value. | 03-10-2016 |
Jing-Yang Jou, Hsinchu City TW
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20110153709 | DELAY OPTIMAL COMPRESSOR TREE SYNTHESIS FOR LUT-BASED FPGAS - A compressor tree synthesis algorithm, named DOCT, which guarantees the delay optimal implementation in LUT-based FPGAs. Given a targeted K-input LUT architecture, DOCT firstly derives a finite set of prime patterns as essential building blocks. Then, it shows that a delay optimal compressor tree can always be constructed by those derived prime patterns via integer linear programming (ILP). Without loss of delay optimality, a post-processing procedure is invoked to reduce the number of demanded LUTs for the generated compressor tree design. DOCT has been evaluated over a broad set of benchmark circuits. The DOCT reduces the depth of the compressor tree and the number of LUTs based on the modern 8-input LUT-based FPGA architecture. | 06-23-2011 |
Jing-Yang Jou, Hsin-Chu City TW
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20080209093 | Fine-grained bandwidth control arbiter and the method thereof - A fine-grained bandwidth control arbiter manages the shared bus usage of the requests of the masters which have real-time and/or bandwidth requirements, moreover, the masters are preset a ticket respectively. The arbiter consists of three components, a real-time handler, a bandwidth regulator, and a lottery manager with tuned weight. The real-time handler grants the most urgent request. The bandwidth regulator handles the bandwidth allocation and blocks the requests of masters that have met the bandwidth requirement. The lottery manager with tuned weight stochastically grants one of the contending masters according to the ticket assignment. | 08-28-2008 |
Jin-Long Jou, Kaohsiung City TW
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20110160841 | MEDICAL APPLIANCE AND SURFACE TREATMENT METHOD THEREOF - A surface treatment method for a medical appliance is provided. The surface treatment method includes providing a metal layer; forming an intermediate layer on a surface of the metal layer, in which a thickness of the intermediate layer is greater than a thickness of a native oxide layer of the metal surface; and grafting a functional polymer on the intermediate layer through an electrodeposition process. | 06-30-2011 |
20120076847 | MEDICAL INSTRUMENT AND METHOD OF MANUFACTURING THE SAME - A medical instrument and a manufacturing method thereof are provided. The medical instrument includes a biomedical metal layer and a polymer film. The polymer film is a biodegradable polymer material. The manufacturing method includes the following steps: providing the biomedical metal layer, immersing the biomedical metal layer in a polymer solution, performing a baking process on the biomedical metal layer coated with a polymer film, forming the biomedical metal layer coated with the polymer film, taking out the biomedical metal layer coated with the polymer film to fabricate the medical instrument. The biodegradable polymer film and the biomedical metal layer are combined into the medical instrument, so that a physician performs a surgery more easily. In addition, decomposition time of the polymer film can be preset, so as to achieve efficacy of blocking soft tissue cells having a higher growth rate. | 03-29-2012 |
20120083882 | SPINAL IMPLANT STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A spinal implant structure includes a hollow cylinder and a biodegradable polymer membrane. The hollow cylinder is implanted in a bone damaged part of human vertebra. The biodegradable polymer membrane is formed to a part of a surface of the hollow cylinder. Thus, the biodegradable polymer membrane blocks invasion of soft tissues, and then the bone fillers integrated with vertebra are maintained without loss. | 04-05-2012 |
Jiun-Ying Jou, Taipei City TW
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20110286390 | WIRELESS IMAGE TRANSMITTING APPARATUS AND METHOD FOR TRANSMITTING DATA THEREOF - A wireless image transmitting apparatus includes an image processing unit, a wireless bridging module, and a wireless local area network module. The wireless bridging module includes a network switch and a network port. The network switch is in signal communication with the network port and the image processing unit. The WLAN module is in signal communication with the network switch. The WLAN module uses a first type of packet and a first band to transmit a signal from the image processing unit and uses a second type of packet and a second band to transmit a signal from the network port. A method for transmitting data in a wireless image transmitting apparatus is also disclosed. | 11-24-2011 |
Jong-Dao Jou, Taipei TW
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20100026565 | METHOD FOR GENERATING A REPRESENTATION OF AN ATMOSPHERIC VORTEX KINEMATIC STRUCTURE - A method for generating a representation of a kinematic structure of an atmospheric vortex is provided. The method comprises receiving a plurality of signals from a Doppler radar. The signals are reflected at a plurality of pulse volumes. The method also comprises measuring a plurality of Doppler velocities based on the received signals. A plurality of scaled Doppler velocities are calculated representing the plurality of measured Doppler velocities, the radial distance between the Doppler radar and the pulse volume where the Doppler velocity is measured, and the distance between the radar and a first estimated atmospheric vortex center. The method also comprises generating a representation of the kinematic structure of the atmospheric vortex using the plurality of scaled Doppler wind velocity values. | 02-04-2010 |
20150212207 | METHOD AND SYSTEM FOR GENERATING A DISTANCE VELOCITY AZIMUTH DISPLAY - A method for determining a kinematic structure of a two-dimensional wind field and a system determining the same are provided. The method comprises receiving a plurality of Doppler velocities and a plurality of distances between a Doppler radar and a gate. Each Doppler velocity of the plurality of Doppler velocities corresponds to a respective distance of the plurality of distances between the Doppler radar and the gate. The method further comprises calculating a plurality of distance Doppler velocity values. The distance Doppler velocity values represent the plurality of measured Doppler velocities and the distance between the Doppler radar and the gate. The method further comprises estimating the kinematic structure of the 2D wind field using the plurality of distance Doppler wind velocity values. | 07-30-2015 |
Jwo-Huei Jou, Taipei City TW
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20120008326 | Lighting Device Capable of Reducing the Phenomenon of Melatonin Suppression - According to research, it found that blue light may cause significant effects on suppressing melatonin. For this reason, a lighting device capable of reducing the phenomenon of melatonin suppression is disclosed in the present invention, the lighting device comprises: a light-emitting device being able to emit a visible light; and a light-filtering device being close to the light-emitting device, wherein when the light-emitting device emits the visible light, the light-filtering device is able to filter a blue light component of the visible light, so as to reduce the blue light component within the visible light emitted by the light-emitting device, then the effects on suppressing the melatonin caused by the visible light are reduced. | 01-12-2012 |
20120235121 | ORGANIC LIGHT EMITTING DEVICE AND METHOD FOR FORMING THE SAME - According to an embodiment of the disclosure, an organic light emitting device is provided, which includes: an inflexible tube comprising an external surface and an internal surface; a transparent conductive layer on the internal surface of the inflexible tube; an organic light emitting layer disposed in the inflexible tube and on the transparent conductive layer; and a conductive layer disposed in the inflexible tube and on the organic light emitting layer. According to an embodiment of the disclosure, a method for forming an organic light emitting device is also provided. | 09-20-2012 |
Jwo-Huei Jou, Taipei TW
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20100300520 | PHOTOVOLTAIC CELL HAVING NANODOTS AND METHOD FOR FORMING THE SAME - The present invention provides a photovoltaic cell comprising a photovoltaic conversion layer and a pair of electrodes. The photovoltaic conversion layer, being capable of converting incident light into a plurality hole-electron pairs, comprises a hole transport layer including a plurality of nanodots mixed therein for transporting the holes generated from the photovoltaic effect. The pair of electrodes are coupled respectively to two sides of the photovoltaic conversion layer for conducting holes and electrons. In another embodiment, the present invention further provides a method for forming the photovoltaic cell, wherein the nanodots are mixed in a solution formed of a hole transport material and then a hole transport layer having the nanodots is formed on a conductive substrate. In the photovoltaic cell having nanodots of the present invention, the hole mobility is enhanced so as to improve the efficiency of the photovoltaic cell. | 12-02-2010 |
20110316443 | ILLUMINATING APPARATUS AND ILLUMINATING METHOD THEREOF - The present invention discloses an illuminating apparatus and an illuminating method thereof. The illuminating apparatus comprises a first electrode, a first organic light emitting diode, a second electrode, a second organic light emitting diode and a third electrode. The first and second organic light emitting diodes emit lights with a first chromaticity and a second chromaticity respectively. The illuminating apparatus further comprises a control module, and the control module can supply a first voltage, a second voltage and a third voltage to the first, second and third electrodes so as to emit a sun-like light and adjust the color temperature or the brightness of the light. | 12-29-2011 |
20120299491 | Lighting Device with Color Temperature Adjusting Functionality - The present invention relates to a lighting device with color temperature adjusting functionality, comprising: a light-emitting device array module, a first driving unit, a second driving unit, a third driving unit, a fourth driving unit, a main controlling unit, and a power management unit, wherein the first driving unit, the second driving unit, the third driving unit, the fourth driving unit are used for respectively driving a first high color temperature light-emitting device array, a first low color temperature light-emitting device array, a second low color temperature light-emitting device array, and a second high color temperature light-emitting device array of the light-emitting device array module, so as to selectively drive a plurality of first high color temperature light-emitting devices, a plurality of first low color temperature light-emitting devices, a plurality of second low color temperature light-emitting devices, and a plurality of second high color temperature light-emitting devices to emit a color light with a specific color temperature. | 11-29-2012 |
20120303282 | Melatonin Suppression Extent Measuring Device - The present invention relates to a melatonin suppression extent measuring device, comprising: a light receiving unit, a first processing unit, a first memory unit, a second processing unit, a second memory unit, a display unit, and a power management unit, wherein the light receiving unit is able to receive a light signal and transmit the light signal to the first processing unit; The first processing unit can process the light signal to a spectral data, and furthermore, the second processing unit can process the spectral data to a percent value of melatonin suppression and show the percent value of melatonin suppression in the display unit, so that human can exactly know how many melatonin suppression extent are caused by the light environment which is exposing himself body. | 11-29-2012 |
20120319593 | Lighting Device with Switchable Day/Night Illumination Mode - The present invention relates to a lighting device with switchable day/night illumination mode, comprising: a main controlling unit, a driving unit, a lighting unit, a light filtering unit, an illumination mode switching unit, and a power management unit, wherein the lighting unit is coupled to the driving unit and has a plurality of light-emitting devices, moreover, the main controlling unit is used for controlling the driving unit, so as to drive the lighting unit output a visible light; In addition, the illumination mode switching unit is used for controlling the light filtering unit to show and cover the light-emitting surface of the lighting unit, so as to filter the visible light and make the visible light become a visible light with a specific wavelength; wherein the visible light with specific wavelength causes the smallest excitation to human sympathetic; Thus, using the visible light with specific wavelength as illumination light when night can not only assist users in reading, but also avoid from exciting users' sympathetic and causing melatonin suppression. | 12-20-2012 |
20130299466 | Method for Forming Superior Local Conductivity in Self-Organized Nanodots of Transparent Conductive Film by Femtosecond Laser - A simple method is developed in the present invention for fabricating periodic ripple microstructures on the surface of an ITO film by using single-beam femtosecond laser pulses. The periodic ripple microstructures composed of self-organized nanodots can be directly fabricated through the irradiation of the femtosecond laser, without scanning. The ripple spacing of ˜800 nm, ˜400 nm and ˜200 nm observed in the periodic ripple microstructures can be attributed to the interference between the incident light and the scattering light of the femtosecond laser from the surface of the ITO film. In the present invention, the self-organized dots are formed by the constructive interference formed in the surface of the ITO film, where includes higher energy to break the In—O and Sn—O bonds and then form the In—In bonds. Therefore, the dots have higher surface current greater than other disconstructive regions of the ITO film. | 11-14-2013 |
Jwo-Huei Jou, Hsinchu TW
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20100051997 | Organic light emitting diode and method of fabricating the same - The present invention discloses an organic light emitting diode and a method of fabricating the organic light emitting diode. The OLED device includes one or more light emitting layers, and the light emitting layer is composed of one or more light emitting materials and one or more subject materials, and the subject material has a molecular polarity different from the molecular polarity of the light emitting material, such that the light emitting molecules can be self dispersed to emit a darker blue light color or a light color of a longer wavelength. | 03-04-2010 |
20100051998 | Organic light emitting diode and method of fabricating the same - The present invention discloses an organic light emitting diode and a method of fabricating the organic light emitting diode. The OLED device includes one or more light emitting layers, and the light emitting layer is composed of one or more light emitting materials and one or more subject materials, and the subject material has a molecular polarity different from the molecular polarity of the light emitting material, such that the light emitting molecules can be self dispersed to emit a more reddish light color or a light color of a longer wavelength. | 03-04-2010 |
20110111552 | Method for forming organic layers of electronic devices by contact printing - A method for forming organic layers of electronic devices by contact printing is disclosed, which comprises: (A) providing a substrate, which has an electrode formed thereon; (B) coating an organic material ink onto a mold; (C) applying the ink-coated mold onto the substrate, to transfer the organic material ink onto the electrode of the substrate and then to form an organic layer; and (D) forming another electrode on the organic layer. In addition, after the step (C) is completed, the steps (B) to (C) can be repeated once or several times to form series of organic layers, if needed. | 05-12-2011 |
20110240963 | ORGANIC LIGHT-EMITTING DIODE WITH HIGH COLOR RENDERING - An organic light-emitting diode with high color rendering is provided, which comprises: a substrate with a first electrode formed thereon; a first light-emitting region disposed over the first electrode, wherein the first light-emitting region comprises at least one layer of a first light-emitting layer, and the first light-emitting layer comprises at least one first dye respectively; a spacer disposed on the first light-emitting region; a second light-emitting region disposed on the organic spacer, wherein the second light-emitting region comprises at least one layer of a second light-emitting layer, and the second light-emitting layer comprises at least one second dye respectively; and a second electrode disposed over the second light-emitting region. | 10-06-2011 |
20110254033 | Organic Light-Emitting Diode Device with High Color Rendering - The present invention discloses an organic light-emitting diode (OLED) device with high color rendering comprising a base plate, a first conductive layer, a plurality of white light emitting layers, and a second conductive layer, wherein the spectra of the white light emitting layers possess characteristics of complementarities so as to enhance the color rendering of the emitted white light, and at least one carrier regulating layer is selectively disposed between every two white light emitting layers so as to increase the emitting efficiency and color rendering. | 10-20-2011 |
20110303902 | ORGANIC LIGHT-EMITTING DIODE WITH HIGH COLOR RENDERING - An organic light-emitting diode with high color rendering is provided, which includes: a substrate; a first electrode disposed over the substrate; a light-emitting region disposed over the first electrode, in which the light-emitting region includes a plurality of light-emitting layers and at least one spacer, the spacer being disposed between any two of the light-emitting layers and each of the light-emitting layers individually including a dye; and a second electrode disposed over the light-emitting region. Accordingly, the organic light-emitting diode according to the present invention can exhibit high color rendering and high illumination efficiency. | 12-15-2011 |
20120032153 | Organic Light-Emitting Diode Device - The present invention relates to an improved organic light-emitting diode (OLED) device which comprises a first conductive layer, a first light-emitting material layer, a second light-emitting material layer, a second conductive layer, and at least one third light-emitting material layer, wherein the first conductive layer is adapted for being an anode substrate, moreover, by way of evaporation process, the first light-emitting material layer, the third light-emitting material layer, the second light-emitting material layer, and the second conductive layer are formed on the anode substrate in turns. Besides, the phenomenon of efficiency roll-off occurring in a high luminance region of the OLED device may be improved by adding the third light-emitting material layer between the first light-emitting material layer and the second light-emitting material layer. | 02-09-2012 |
20120156817 | Method for Manufacturing High-quality Organic Light-emitting Diode - The present invention discloses a method for manufacturing a high-quality organic light-emitting diode (OLED), and the method comprises the steps of: providing a substrate; providing at least one template engraved with a pattern; putting at least one organic light-emitting material onto the pattern of the template by an inking process; transferring the organic light-emitting material from the pattern of the template to the substrate by a contact printing process; forming at least one organic light-emitting layer on the substrate, wherein the organic light-emitting layer comprises a plurality of pixels which are arranged in a side by side manner with a complementary emission spectrum, so that the OLED possesses the property of high color rendering, color temperature tunable, or the combination thereof. | 06-21-2012 |
20140084255 | Organic Light-Emitting Diode Using Bandgap Matching Dye as Co-Host - The present invention relates to an organic light-emitting diode using an bandgap matching dye as a co-host, comprising: a first conductive layer, a hole injection layer, a hole transport layer, a host light-emitting layer, a first dye, a second dye, an electronic transport layer, an electronic injection layer, and a second conductive layer; wherein the host energy gap of the host light-emitting layer is greater than the energy gap of the first dye, and the energy gap of the first dye is greater than the energy gap of the second dye; therefore the first dye can be a co-host light-emitting layer opposite to the host light-emitting layer, and the energy of the first dye can be effectively conducted to the second dye, such that the luminous efficiency of the light emitted by the second dye through the host light-emitting layer is largely enhanced. | 03-27-2014 |
20140252320 | FULL-BAND AND HIGH-CRI ORGANIC LIGHT-EMITTING DIODE - The present invention relates to a full-band and high-CRI organic light-emitting diode, comprising: a first conductive layer, at least one first carrier transition layer, a plurality of light-emitting layers, at least one second carrier transition layer, and a second conductive layer. In the present invention, a plurality of dyes are doped in the light-emitting layers, so as to make the light-emitting layers emit a plurality of blackbody radiation complementary lights, wherein the chromaticity coordinates of the blackbody radiation complementary lights surround to a specific area on 1931 CIE (Commission International de'Eclairage) Chromaticity Diagram, moreover, the specific area fully encloses the Planck's locus on 1931 CIE Chromaticity Diagram, such that the blackbody radiation complementary lights mix to each other and then become a full-band and high-CRI light. | 09-11-2014 |
20140313512 | Light Source Quality Evaluating Method by Using Spectral Resemblance With Respect to the Blackbody Radiation - The present invention relates to a light source quality evaluating method by using spectral resemblance with respect to the blackbody radiation, which mainly comprises 5 method steps. This method is used for evaluating the quality of light based on physiological perception of human. In evaluating operation, the method firstly transfers a power spectrum of a light source to a luminance spectrum of light source through a luminosity function. Next, the method compares the luminance spectrum of light source with a luminance spectrum of the blackbody radiation thereof. Therefore, an index of spectral resemblance with respect to the black body radiation (SR | 10-23-2014 |
20150070701 | Light Quality Evaluating Device - The present invention relates to a light quality evaluating device, comprising a light receiving unit, first processing unit, a memory unit, a second processing unit, a display unit, and a power management unit, and being used for evaluating the light quality light based on physiological perception of human. In evaluating operation, it transfers a power spectrum of the light emitted from a light source to a luminance spectrum of light through a luminosity function. Next, the method compares the luminance spectrum of light with a corresponding luminance spectrum of blackbody radiation thereof. Therefore, an index of spectral resemblance with respect to the black body radiation (SR | 03-12-2015 |
20160028013 | CARRIER TRANSPORT MATERIAL - The present invention provides a carrier transport material formed by completing a reaction process of at least one aromatic compound and at least one polycyclic aromatic hydrocarbons (PAHs), wherein a cross linking reaction can be activated in the molecular compound through heating or ultraviolet irradiation because the molecular compound has at least one cross-linkable functional group. Therefore, when the carrier transport material is applied in an OLED, the carrier transport material would not be dissolved by the solvent included in the next coated material because the carrier transport material has been cured after the cross linking reaction is carried out. Moreover, because the carrier transport material would simultaneously perform an electron confining functionality when being used as a hole transport layer, the device efficiency of the OLED having the carrier transport material is obviously enhanced during the high-brightness operation especially. | 01-28-2016 |
20160056385 | NOVEL LIGHT-EMITTING MATERIAL - The present invention provides a novel light-emitting material, which is a blue fluorescent material performs a high quantum yield of ˜86%, and can be doped into a host light-emitting layer of an organic light emitting diode (OLED) for being a guest light-emitting material, so as to increase the external quantum efficiency, the power efficiency and the current efficiency of the OLED. Most importantly, a variety of experiment results have proved that the OLED having the novel light-emitting material can emit a deep blue light with CIE coordinates of (0.156, 0.055). Moreover, the experiment results also proved that the novel light-emitting material can be applied in fabricating OLED through dry process and/or wet process; so that, the novel light-emitting material is helpful to the low-cost mass production of OLEDs. | 02-25-2016 |
20160111648 | Spirally Configured Cis-Stilbene/Fluorene Hybrid Materials for Organic Light-Emitting Diode - The present invention provides a series of spirally configured cis-stilbene/fluorene hybrid materials, which are spirally-configured cis-stilbene/fluorene derivatives having glass transition temperatures ranged from 105° C. to 130° C., decomposition temperatures ranged from 385° C. to 415° C., reversible electron transport property, and balanced charges motilities. Moreover, a variety of experimental data have proved that the yellow fluorescent, the green phosphorescent, the yellow phosphorescent, and the red phosphorescent OLEDs using this spirally configured cis-stilbene/fluorene derivatives as the electron transport layers having hole blocking functions can indeed show excellent EQE, current efficiency, power efficiency, maximum luminance, and device lifetime performances much better than the conventional or commercial yellow fluorescent, green phosphorescent, yellow phosphorescent, and red phosphorescent OLEDs. | 04-21-2016 |
20160115127 | Electro-fluorescent emitter for ultra-violet OLED - The present invention demonstrates a newly designed and synthesized carbazole scaffold based electro-fluorescent emitter, 9-butyl-2,7-(2-(4-methoxyphenyl)ethynyl)-9H-carbazole (Cz(APhOMe) | 04-28-2016 |
Jwo-Huei Jou, Hsinchu City TW
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20110183454 | Method for preparing OLED by imprinting process - A method for preparing an OLED by an imprinting process is disclosed, which comprises the following steps: (A) providing a substrate, and a first electrode is formed thereon; (B) coating a mold with a first organic material ink; (C) pressing the mold coated with the first organic material ink on the substrate to transfer the first organic material ink onto the first electrode of the substrate, to obtain a first light-emitting array; (D) baking the substrate having the first light-emitting array formed thereon; and (E) forming a second electrode on the first light-emitting array. | 07-28-2011 |
20130100981 | SYSTEM AND METHOD OF DETECTING SUBLIMATION POINT - The present invention provides a system and a method of detecting a sublimation point, preferably applied to organic molecules. The system of detecting a sublimation point comprises: a heater, a capillary device, a vacuum pump, an ultraviolet light source, a photography device, a digital vacuum meter and a needle valve. The system of detecting a sublimation point is suitable for detecting the sublimation point of an organic light emitting molecule such as tris(8-hydroxyquinolinato) aluminum (Alq | 04-25-2013 |
20160111649 | SPIRALLY CONFIGURED CIS-STILBENE/FLUORENE HYBRID MATERIALS AS HOLE-BLOCKING TYPE ELECTRON-TRANSPORTERS FOR OLED - An OLED (organic light emitting diode) comprises a series of spirally configured cis-stilbene/fluorene hybrid materials. The spirally configured cis-stilbene/fluorene hybrid materials are spirally-configured cis-stilbene/fluorene derivatives having the functions to block holes and constructed by at least one cis-Stilbene based component and at least one fluorene based component. | 04-21-2016 |
Jwo-Ming Jou, Kaohsiung City TW
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20100073787 | PIEZOELECTRIC-DRIVING OPTICAL LENS - A piezoelectric-driving optical lens is disclosed, which comprises: a lens, having a barrel with a friction ring annularly mounted on the outer wall of the barrel as the outer diameter of the friction ring is larger than that of the barrel; a plurality of piezoelectric stators, arranged surrounding the lens and abutted against the friction ring, for providing a rotation driving force to the lens for focusing or zooming function; and a seat, for receiving the lens and the plural piezoelectric stators; wherein, the plural piezoelectric stators can actuate simultaneously to output a maximum driving torque. | 03-25-2010 |
Leng-Long Jou, Sanchong City TW
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20100152374 | FLAME-RETARDANT WATERBORNE POLYURETHANE DISPERSION - The invention provides a flame-retardant waterborne polyurethane dispersion. The dispersion includes: 1 to 15 parts by weight of a phosphorus flame retardant containing active hydrogen; 10 to 40 parts by weight of a diisocyanate; 30 to 80 parts by weight of a polyol; and 1 to 15 parts by weight of an active hydrogen-containing compound, which is capable of forming a hydrophilic group. | 06-17-2010 |
Li-Pin Jou, Hsinchu TW
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20100029035 | METHOD OF MANUFACTURING A PHOTOELECTRONIC DEVICE - This application discloses a method of manufacturing a photoelectronic device comprising steps of providing a semiconductor stack layer, forming at least one metal adhesive on the semiconductor stack layer by a printing technology, forming an electrode by heating the metal adhesive to remove the solvent in the metal adhesive, wherein an ohmic contact is formed between the electrode and the semiconductor stack layer. | 02-04-2010 |
Li-Ping Jou, Hsinchu TW
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20110227120 | LIGHT-EMITTING DEVICE - A light-emitting device comprises a substrate, an epitaxial structure formed on the substrate including a first semiconductor layer, a second semiconductor layer, and a light-emitting layer formed between the first semiconductor layer and the second semiconductor layer. A trench is formed in the epitaxial structure to expose a part of side surface of the epitaxial structure and a part of surface of the first semiconductor layer, so that a first conductive structure is formed on the part of surface of the first semiconductor layer in the trench, and a second conductive structure is formed on the second semiconductor layer. The first conductive structure includes a first electrode and a first pad electrically contacted with each other. The second conductive structure includes a second electrode and a second pad electrically contacted with each other. Furthermore, the area of at least one of the first pad and the second pad is between 1.5×10 | 09-22-2011 |
20140084324 | LIGHT-EMITTING DEVICES - A light-emitting device of an embodiment of the present application comprises a semiconductor layer sequence provided with a first main side, a second main side, and an active layer; a beveled trench formed in the semiconductor layer sequence, having a top end close to the second main side, a bottom end, and an inner sidewall connecting the top end and the bottom end. In the embodiment, the inner sidewall is an inclined surface. The light-emitting device further comprises a dielectric layer disposed on the inner sidewall of the beveled trench and the second main side; a first metal layer formed on the dielectric layer; a carrier substrate; and a first connection layer connecting the carrier substrate and the semiconductor layer sequence. | 03-27-2014 |
20150236208 | LIGHT-EMITTING DEVICES - A light-emitting device comprises a semiconductor layer sequence comprising a first semiconductor layer having a first electrical conductivity, a second semiconductor layer having a second electrical conductivity, and an active layer interposed between the first semiconductor layer and the second semiconductor layer; a plurality of protruding structures; a plurality of beveled trenches in the semiconductor layer sequence and respectively accommodating the plurality of protruding structures; a dielectric layer on the second semiconductor layer and an inner sidewall of the plurality of beveled trenches, wherein the dielectric layer comprises a surface perpendicular to a thickness direction of the semiconductor layer sequence; a metal layer formed along the inner sidewall of the plurality of beveled trenches and extending to the surface of the dielectric layer, wherein the metal layer is insulated from the second semiconductor layer by the dielectric layer; and a first electrode formed on the plurality of protruding structures. | 08-20-2015 |
Li-Ping Jou, Kaohsiung City TW
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20120241783 | LED ARRAY - An LED array having N light-emitting diode units (N≧3) comprises a permanent substrate, a bonding layer on the permanent substrate, a second conductive layer on the bonding layer, a second isolation layer on the second conductive layer, a crossover metal layer on the second isolation layer, a first isolation layer on the crossover metal layer, a conductive connecting layer on the first isolation layer, an epitaxial structure on the conductive connecting layer, and a first electrode layer on the epitaxial structure. The light-emitting diode units are electrically connected with each other by the crossover metal layer. | 09-27-2012 |
20140054631 | LED ARRAY - An LED array having N light-emitting diode units (N≧3) comprises a permanent substrate, a bonding layer on the permanent substrate, a second conductive layer on the bonding layer, a second isolation layer on the second conductive layer, a crossover metal layer on the second isolation layer, a first isolation layer on the crossover metal layer, a conductive connecting layer on the first isolation layer, an epitaxial structure on the conductive connecting layer, and a first electrode layer on the epitaxial structure. The light-emitting diode units are electrically connected with each other by the crossover metal layer. | 02-27-2014 |
20140319574 | LED ARRAY - An LED array having N light-emitting diode units (N≧3) comprises a permanent substrate, a bonding layer on the permanent substrate, a second conductive layer on the bonding layer, a second isolation layer on the second conductive layer, a crossover metal layer on the second isolation layer, a first isolation layer on the crossover metal layer, a conductive connecting layer on the first isolation layer, an epitaxial structure on the conductive connecting layer, and a first electrode layer on the epitaxial structure. The light-emitting diode units are electrically connected with each other by the crossover metal layer. | 10-30-2014 |
20160104744 | LED ARRAY - An LED array having N light-emitting diode units (N≧3) comprises a permanent substrate, a bonding layer on the permanent substrate, a second conductive layer on the bonding layer, a second isolation layer on the second conductive layer, a crossover metal layer on the second isolation layer, a first isolation layer on the crossover metal layer, a conductive connecting layer on the first isolation layer, an epitaxial structure on the conductive connecting layer, and a first electrode layer on the epitaxial structure. The light-emitting diode units are electrically connected with each other by the crossover metal layer. | 04-14-2016 |
Ming-Jiunn Jou, Hsinchu TW
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20110220873 | LIGHT EMITTING DIODE HAVING A TRANSPARENT SUBSTRATE - A light emitting diode having a transparent substrate and a method for manufacturing the same. The light emitting diode is formed by creating two semiconductor multilayers and bonding them. The first semiconductor multilayer is formed on a non-transparent substrate. The second semiconductor multilayer is created by forming an amorphous interface layer on a transparent substrate. The two semiconductor multilayers are bonded and the non-transparent substrate is removed, leaving a semiconductor multilayer with a transparent substrate. | 09-15-2011 |
20130115725 | LIGHT EMITTING DIODE HAVING A TRANSPARENT SUBSTRATE - A light emitting diode having a transparent substrate and a method for manufacturing the same. The light emitting diode is formed by creating two semiconductor multilayers and bonding them. The first semiconductor multilayer is formed on a non-transparent substrate. The second semiconductor multilayer is created by forming an amorphous interface layer on a transparent substrate. The two semiconductor multilayers are bonded and the non-transparent substrate is removed, leaving a semiconductor multilayer with a transparent substrate. | 05-09-2013 |
20150123151 | LIGHT EMITTING DEVICE - A light-emitting structure includes a transparent substrate; a first transparent conductive layer formed on the transparent substrate and having a first top surface and a second top surface substantially coplanar with the first top surface; a first light-emitting stack formed on the first top surface; and a first electrode directly formed on the second top surface. | 05-07-2015 |
Ming-Jong Jou, Tainan City TW
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20130002406 | ELECTRONIC LABEL SYSTEM AND OPERATION METHOD THEREOF - An electronic label system and an operation method thereof are provided. The electronic label system includes a control unit and a plurality of electronic label units. The control unit is used for sending display information. The electronic label units are coupled to the control unit to receive the display information and display according to the corresponding display information, respectively. The electronic label units respectively output a plurality of state information to the control unit so that the control unit can monitor operation states of the electronic label units according to the state information. | 01-03-2013 |
Ming-Jong Jou, Hsinchu TW
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20090102764 | Liquid Crystal Display and Driving Method Therefor - A liquid crystal display is provided. The liquid crystal display includes a substrate, a plurality of data lines, a plurality of gate lines, a gate driving circuit, and a source driving circuit. The substrate includes a pixel array including a plurality of pixels arranged as a matrix. The data lines are electrically connected to the pixel array. The gate lines are electrically connected to the pixel array and include a plurality of odd-numbered gate lines and a plurality of even-numbered gate lines, wherein one of the odd-numbered gate lines and one of the even-numbered gate lines are electrically connected to the pixels located in the same row. The gate driving circuit includes a first gate driving circuit and a second gate driving circuit, wherein the first gate driving circuit is electrically connected to the odd-numbered gate lines and the second gate driving circuit is electrically connected to the even-numbered gate lines. The source driving circuit is electrically connected to the data lines. | 04-23-2009 |
20100039405 | Projective Capacitive Touch Apparatus, and Method for Identifying Distinctive Positions - A projective capacitive touch apparatus and a method for identifying multi-touched positions are provided. The multi-touched positions are touched on a projective capacitive touch panel. The method comprises the following steps: generating a first set of reference values according to the first touch position; generating a plurality of second sets of reference values according to a second touch position, and filtering out at least one ghost second set of reference values from the second sets of reference values. Furthermore, the plurality of second sets of reference values comprise a real second set of reference value and at least one ghost second set of reference values, while the ghost second set of reference values comprises parts of the first set of reference values. | 02-18-2010 |
Ming-Jong Jou, Hsinchu City TW
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20130176288 | ELECTRONIC LABEL SYSTEM - An electronic label system, which includes a control unit, a first net unit, a second net unit and a plurality of electronic label units is provided. The control unit is configured for sending out a display information. The first net unit is coupled to the control unit for converting the display information into a wireless display signal. The second net unit is coupled to the first net unit for receiving the wireless display signal and outputting a display control signal. The electronic label units are coupled in series to the second net unit to receive the display control signal and to respectively display according to the corresponding display control signal. In this way, the cost of the electronic label system is reduced. | 07-11-2013 |
20130221112 | ELECTRONIC CARD - An electronic card including a function indication area and a content display area is provided. The function indication area indicates an operational function of the electronic card. The content display area displays the content corresponding to the operational function. Accordingly, the user can comprehend the operational function of the electronic card through the function indication area. | 08-29-2013 |
20130249782 | ELECTROPHORETIC DISPLAY MODULE AND OPERATING METHOD THEREOF AND ELECTROPHORETIC DISPLAY SYSTEM USING THE SAME - An electrophoretic display module and an operating method thereof and an electrophoretic display system using the same are provided. The electrophoretic display system includes an electronic device and the electrophoretic display module. The electronic device is configured to transmit a data wireless signal and a power wireless signal, wherein a frequency of the power wireless signal is smaller than a frequency of the data wireless signal. The electrophoretic display module is configured to receive the data wireless signal and the power wireless signal, transform the power wireless signal into an operating power, and perform a predetermined operation according to the data wireless signal. | 09-26-2013 |
20140062391 | ELECTRONIC CARD - An electronic card including an antenna, a chip, a charging circuit and a battery is provided. The antenna receives an external electric signal, and the chip is coupled to the antenna, so as to receive the external electric signal and provide a demodulated electric signal. The charging circuit is coupled to the chip, receives the demodulated electric signal and converts the demodulated electric signal to generate a charging power. The battery is coupled to the charging circuit, wherein, the charging circuit provides the charging power to the battery according to a residual electricity of the battery, so as to charge the battery. | 03-06-2014 |
Rong-Yuan Jou, Da Li City TW
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20090175006 | HONEYCOMB HEAT DISSIPATING APPARATUS - A honeycomb heat dissipating apparatus made of a composite metal material includes honeycomb cells that are integrally formed by vacuum die casting, and continuous convex and concave distal surfaces disposed around the periphery of the heat dissipating apparatus, and an adjacent surface of each cell is a thin surface, and the heat dissipating apparatus can be in a standalone mode, or combined with other heat dissipating apparatuses. One or more honeycomb heat dissipating apparatuses can be installed on a circuit board or an electronic component of a lamp or an electric appliance, such that the heat dissipating apparatus can dissipate heat quickly by the honeycomb cells without occupying much space. The invention can increase the heat dissipating area for a faster heat dissipating effect and change the stylish appearance to achieve the aesthetic effect. | 07-09-2009 |
Ruwen Jou, Taipei City TW
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20080261221 | AUTOMATED VNTR GENOTYPING METHOD - The invention provides an automated VNTR genotyping method using multiple variable-number tandem repeats (VNTRs) loci based on mycobacterial interspersed repetitive units (MIRU) undergoing multiplex PGR and high throughput MEGABACE® capillary electrophoresis system. The method uses fluorescent dyes of 6-carboxytetramethylrhodamine(TAMRA), 6-carboxy fluorescein (FAM) and 6-carboxy-2′, 4, 4′, 5′, 7, 7′-hexachlorofluorescein (HEX) labeling PGR primers. The method results in an efficient VNTR genotyping with low cost, less labor-requirement and less reaction time. The method is applicable in organism analyses by VNTR genotyping, such as microorganisms, parasites, animals or plants. | 10-23-2008 |
Sheng-Jian Jou, Huwei Township TW
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20140035097 | SEMICONDUCTOR PACKAGE HAVING AN ANTENNA AND MANUFACTURING METHOD THEREOF - A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first substrate, a second substrate, an interposer substrate, a semiconductor chip, a package body and a first antenna layer. The first substrate comprises a grounding segment. The interposer substrate is disposed between the second substrate and the first substrate. The semiconductor chip is disposed on the second substrate. The package body encapsulates the second substrate, the semiconductor chip and the interposer substrate, and has a lateral surface and an upper surface. The first antenna layer is formed on the lateral surface and the upper surface of the package body, and electrically connected to the grounding segment. | 02-06-2014 |
Shin-Hung Jou, Changhua County TW
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20090282177 | APPARATUS AND METHOD FOR SIGNAL TRANSMISSION IN EMBEDDED SYSTEM - An apparatus and a method for signal transmission in an embedded system. The apparatus comprises: a master control chip, embedded in the embedded system and comprising a controller and a plurality of I/O pins; a plurality of slave chips; and a bus having one end coupled to the plurality of I/O pins and the other end coupled to one of the plurality of slave chips; wherein data or signals are bi-directionally transmitted. The method comprises steps of: transmitting a control signal from a master control chip to a slave chip; starting an operation by the slave chip after receiving the control signal; transmitting a data signal and a command signal to the master control chip from the slave chip; processing the data signal according to the command signal by the master control chip; and transmitting another control signal from the master control chip to the slave chip to terminate the operation. | 11-12-2009 |
Shyan-Kay Jou, Taipei City TW
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20090087567 | METHOD OF FABRICATING ONE-DIMENSIONAL METALLIC NANOSTRUCTURE - A method of fabricating one-dimensional metallic nanostructure is provided. First, a mixing layer including a first oxide and a second oxide is provided. The first oxide is a metallic oxide, and the first oxide and the second oxide are immiscible. Next, a reducing gas is introduced and a thermal process is performed on the mixing layer so as to reduce the metal of the first oxide to form one-dimensional metallic nanostructure. | 04-02-2009 |
Shyan-Kay Jou, Taipei County TW
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20110132745 | METHOD OF FABRICATING VARIABLE RESISTANCE LAYER FOR RESISTANCE MEMORY - A method of fabricating a variable resistance layer of a resistance memory is disclosed. The method includes placing a substrate in a sputtering chamber that has a copper target and a silicon oxide (SiO | 06-09-2011 |
Shyh-Jye Jou, Baoshan Township TW
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20110235444 | SRAM WRITING SYSTEM AND RELATED APPARATUS - SRAM writing system and related apparatus are provided. The writing system of the invention has a dummy replica writing circuit, a negative pulse controller and at least a normal writing circuit; each normal writing circuit includes a write driver and a negative pulse supplier. While writing, the dummy replica writing circuit drives a dummy replica bit-line, such that the negative pulse controller generates a negative pulse control signal according to level of the dummy replica bit-line. In each writing circuit, when the write driver conducts to connect an associated bit-line to a bias end for driving a level transition, the negative pulse supplier switches the bias end from an operation voltage to a different negative pulse voltage according to the received negative pulse control signal. | 09-29-2011 |
Shyh-Jye Jou, Hsinchu City TW
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20130194861 | SINGLE-ENDED SRAM WITH CROSS-POINT DATA-AWARE WRITE OPERATION - A single-ended SRAM including at least one memory cell and a third switch is provided. The memory cell includes a data-latching unit, a first switch, a second switch and a data-transferring unit. The data-latching unit is configured for latching the received input data and provides a storage data and the inverse data of the storage data. The first switch transfers a reference data to the data-latching unit according to a first word-line signal. The second switch transfers the reference data to the data-latching unit according to a second word-line signal. The data-transferring unit decides whether or not to transfer the reference data to the bit-line according to the storage data and a control signal. The third switch receives the reference data and the control signal and transfers the reference data to the first switch, the second switch and the data-transferring unit according to the control signal. | 08-01-2013 |
20160065180 | SAMPLING CIRCUIT AND MASTER-SLAVE FLIP-FLOP - A sampling circuit includes a first latch, a second latch and a signal transition detector. The first latch is disposed on an upstream side of a logic circuit. The second latch is disposed on a downstream side of the logic circuit. The first latch and the second latch respectively switch to opposite states of an opaque state or a transparent state according to trigger signals generated by a reference clock and a control clock. The signal transition detector is configured for detecting whether the signal outputted by the logic circuit is in error or not and outputting a corresponding control clock. The above-mentioned sampling circuit can delay switching the second latch to the opaque state and switching the first latch to the transparent state to correct sampling when a timing error occurs. | 03-03-2016 |
Shyh-Jye Jou, Hsinchu County TW
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20110128796 | DISTURB-FREE STATIC RANDOM ACCESS MEMORY CELL - A disturb-free static random access memory cell includes: a latch circuit having a first access terminal and a second access terminal; a first switching circuit having a first bit transferring terminal coupled to the first access terminal, a first control terminal coupled to a first write word line, and a second bit transferring terminal; a second switching circuit having a third bit transferring terminal coupled to the second access terminal, a second control terminal coupled to a second write word line, and a fourth bit transferring terminal coupled to the second bit transferring terminal; a third switching circuit having a fifth bit transferring terminal coupled to the fourth bit transferring terminal, a third control terminal coupled to a word line, and a sixth bit transferring terminal coupled to a bit line; and a sensing amplifier coupled to the bit line, for determining a bit value appearing at the bit line. | 06-02-2011 |
20120008377 | STATIC RANDOM ACCESS MEMORY WITH DATA CONTROLLED POWER SUPPLY - A static random access memory with data controlled power supply, which comprises a memory cell circuit and at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit. | 01-12-2012 |
20120057399 | ASYMMETRIC VIRTUAL-GROUND SINGLE-ENDED SRAM AND SYSTEM THEREOF - The present invention discloses an asymmetric virtual-ground single-ended SRAM and a system thereof, wherein a first inverter is coupled to a high potential and a virtual ground, and wherein the first inverter and a second inverter form a latch loop, and wherein a third inverter is electrically connected with the second inverter, and wherein the third inverter and the second inverter are jointly coupled to the high potential and a ground. A write word line and a read word line control an access transistor and a pass transistor to undertake writing and reading of signals. A plurality of asymmetric virtual-ground single-ended SRAMs forms a memory system. | 03-08-2012 |
20130222071 | Oscillator based on a 6T SRAM for measuring the Bias Temperature Instability - The present invention provides an oscillator which is based on a 6T SRAM for measuring the Bias Temperature Instability. The oscillator includes a first control unit, a first inverter, a second control unit, and a second inverter. The first control unit is coupled with the first inverter. The second control unit is coupled with the second inverter. The first control unit and the second control unit is used to control the first inverter and the second inverter being selected, biased, and connected respectively, so that the NBTI and the PBTI of the SRAM can be measured separately, and the real time stability of the SRAM can be monitored immediately. | 08-29-2013 |
20130223136 | SRAM based on 6 transistor structure including a first inverter, a second inverter, a first pass-gate transistor, and a second pass-gate transistor - The present invention provides a 6T SRAM including a first inverter, a second inverter, a first pass-gate transistor, and a second pass-gate transistor. The first inverter zs a first pull-up transistor and a first pull-down transistor. The second inverter includes a second pull-up transistor and a second pull-down transistor. The gate of the second pull-up transistor is coupled with the gate of the second pull-down transistor, and the drain of the second pull-up transistor is coupled with the drain of the second pull-down transistor. The SRAM can measure the trip voltage, the read disturb voltage, and the write margin by controlling the first bit line, the second bit line, the GND, the first word line, and the voltage source without changing of the physic parameter of the SRAM. | 08-29-2013 |
20130301343 | THRESHOLD VOLTAGE MEASUREMENT DEVICE - A threshold voltage measurement device is disclosed. The device is coupled to a 6T SRAM. The SRAM comprises two inverters each coupled to a FET. Power terminals of one inverter are in a floating state; the drain and source of the FET coupled to the inverter are short-circuited. Two voltage selectors, a resistor, an amplifier and the SRAM are connected in a negative feedback way. Different bias voltages are applied to the SRAM for measuring threshold voltages of two FETs of the other inverter and the FET coupled to the other inverter. The present invention uses a single circuit to measure the threshold voltages of the three FETs without changing the physical structure of the SRAM. Thereby is accelerated the measurement and decreased the cost of the fabrication process and measurement instruments. | 11-14-2013 |
20140078818 | STATIC RANDOM ACCESS MEMORY WITH RIPPLE BIT LINES/SEARCH LINES FOR IMROVING CURRENT LEAKAGE/VARIATION TOLERANCE AND DENSITY/PERFORMANCE - A static random access memory includes a pre-charger, a first cell column array/peripheral circuit, and a first ripple buffer. The pre-charger is connected to a first local bit line in order to pre-charge the first local bit line. The first cell column array/peripheral circuit is connected to the first local bit line and has a plurality of cells for temporarily storing data. The cells are connected to the first local bit line. The first ripple buffer is connected to the first local bit line and a second local bit line in order to send the data from the first local bit line to the second local bit line. | 03-20-2014 |
20150162077 | STATIC MEMORY CELL - A static memory cell is provided. The static memory cell includes a data latch circuit and a voltage provider. The data latch circuit is configured to store a bit data. The data latch circuit has a first inverter and a second inverter, and the first inverter and the second inverter are coupled to each other. The first inverter and the second inverter respectively receive a first voltage and a second voltage as power voltages. The voltage provider provides the first voltage and the second voltage to the data latch circuit. When the bit data is written to the data latch circuit, the voltage provider adjusts a voltage value of one of the first and second voltages according to the bit data. | 06-11-2015 |
Wan-Chen Jou, Banciao City TW
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20090025125 | Diving goggles with defogging device - A diving goggles with defogging device, including a flexible frame provided with an adjustable fastening strap that is used to secure the diving goggles to the face of a user; an exterior lens used to seal off sea water from flowing into the flexible frame is fixed to the extreme exterior of the flexible frame; an internal lens which forms an airtight interlayer with the exterior lens is fixed to an inner side of the flexible frame; and a heating element used to maintain temperature of the internal lens is disposed on the internal lens. Accordingly, the present invention is able to effectively prevent fogging from occurring because of the temperature difference between body heat from the user and the lenses of the goggles. | 01-29-2009 |
Wen-Hann Jou, Taipei County TW
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20090105112 | Nono-clay composite and composition for fabricating the same - The present invention relates to a nano-clay composite and a composition for fabricating the same. The nano-clay composite of the invention is formed by compounding a composition comprising a polymer, a surfactant, a polymer modification component, and micro/nano powders. The nano-clay composite is flexible to completely adhere to cleaning surfaces to remove unwanted materials via the release of surfactant, as well as the scrubbing effect produced by the friction between micro/nano powders and the surface. | 04-23-2009 |
Wern-Shiarng Jou, Kaohsiung TW
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20100275393 | METHOD OF MAKING A LASTED SKATE BOOT - A method of making a lasted skate boot comprising: (a) providing a male-female mold having male and female sections for defining a mold cavity therebetween, the male section having sides, a rear portion and a bottom portion for defining a three dimensional shape corresponding to the external three dimensional shape of the foot, the female section defining a recess for receiving the male section, the male section comprising a plurality of inner channels for admitting liquid plastic material in the mold cavity; (b) providing a pre-cut sheet made of cloth material laminated to a support made of non-woven fabric; (c) placing the sheet on the male section of the mold such that the non-woven fabric contacts the sides and rear portion of the male section of the mold; (d) closing the male and female sections of the mold; (e) injecting liquid plastic material in the inner channels such that the liquid plastic material spreads on the sheet, pushes the sheet against the recess of the female section of the mold, fills the mold cavity and fuses with the non-woven fabric to form, after cooling, an outer shell comprising a heel portion for surrounding the heel, an ankle portion for surrounding the ankle, and medial and lateral side portions for enclosing the medial and lateral sides of the foot respectively; (f) opening the male and female sections of the mold; and (g) removing the outer shell from the mold. | 11-04-2010 |
Wuu-Cheau Jou, Dali City TW
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20080276480 | RACK FOR DRIERS - A rack for driers includes a support with a Y-axis tube set connected thereto and an inlet unit is mounted to the Y-axis tube set so that two connection members are respectively connected thereto. A Z-axis tube is connected to a vertical sleeve unit on the Y-axis tube set and an X-axis tube is connected to a horizontal sleeve unit on the Z-axis tube. Two driers are connected to two drier bases on the X-axis tube. The two driers are connected to the two connection members by hoses. The positions of the driers are adjusted in three directions and the inlet unit is rotated about the Y-axis tube set. | 11-13-2008 |
Wuu-Cheau Jou, Taichung Hsien TW
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20080230626 | SIPHON DRYING GUN - A siphon type of drying gun includes an arc diverter disposed between an inner end surface in an accommodation space in a body of the gun and a flared hole. A rear cover having a flange is screwed into the body. An exhaustion gap is defined between the flange of the rear cover and the arc diverter. A front tapered hole in the rear cover corresponding to the arc diverter to guide the compressed air admitted into the exhaustion gap to flow by following the arc diverter and taking a turn into the flared hole so to produce siphon effects against ambient air to reduce noise level. | 09-25-2008 |
20080283699 | STAND FOR A DRYING GUN SUPPORTING FRAME - A stand for a drying gun supporting frame includes a body and a socket at 90 degrees to the body. A spherical valve is disposed in the body, and a connecting unit is provided at the top of the body. The socket has a threaded hole at one side to receive a manual screw therein so as to secure a balancing pipe thereat. The spherical valve disposed in the body comprises a ball, washers, a cap and a linking rod. The altitude of the spherical valve is lower than the center of the balancing pipe, which lowers the outlet of the drying gun and provides a steady operation of the drying gun. | 11-20-2008 |
Yeh-Ning Jou, Linkou Township TW
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20120193718 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An ESD protection structure is disclosed. A substrate comprises a first conductive type. A first diffusion region is formed in the substrate. A first doped region is formed in the first diffusion region. A second doped region is formed in the first diffusion region. A third doped region is formed in the substrate. A first isolation region is formed in the substrate, covers a portion of the first diffusion region and is located between the second and the third doped regions. A fourth doped region is formed in the substrate. When the first doped region is coupled to a first power line and the third and the fourth doped regions are coupled to a second power line, an ESD current can be released to the second power line from the first power line. During the release of the ESD current, the second doped region is not electrically connected to the first power line. | 08-02-2012 |
Yeh-Ning Jou, New Taipei City TW
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20140054707 | ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE - An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes an epitaxy layer disposed on a semiconductor substrate. An isolation pattern is disposed on the epitaxy layer to define a first active region and a second active region, which are surrounded by a first well region. A gate is disposed on the isolation pattern. A first doped region and a second doped region are disposed in the first active region and the second active region, respectively. A drain doped region is disposed in the first doped region. A source doped region and a first pick-up doped region are disposed in the second doped region. A source contact plug having an extended portion connects to the source doped region. A ratio of an area of the extended portion covering the first pick-up doped region to an area of first pick-up doped region is between zero and one. | 02-27-2014 |
Yeh-Ning Jou, Taipei County TW
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20090135532 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUITS - An electrostatic discharge (ESD) protection circuit is provided. A transistor is coupled between a node and a ground, and has a gate coupled to the ground. A diode chain is coupled between the node and a pad, and comprises a plurality of first diodes connected in series, wherein the first diode is coupled in a forward conduction direction from the pad to the node. A second diode is coupled between the node and the pad, and the second diode is coupled in a forward conduction direction from the node to the pad. | 05-28-2009 |
20090140370 | SEMICONDUCTOR DEVICE - A semiconductor device is described. The semiconductor device comprises a protected device in a protected device area of a substrate. An electrostatic discharge power clamp device comprising an outer first guard ring and an inner second guard ring is in a guard ring area of the substrate, enclosing the protected device. The first guard ring comprises a first well region having a first conductive type. A first doped region having the first conductive type and a second doped region having a second conductive type are in the first well region. The second guard ring comprises a second well region having a second conductive type. A third doped region has the second conductive type in the second well region. An input/output device is in a periphery device area, coupled to the electrostatic discharge power clamp device. | 06-04-2009 |
20090261417 | TRIG MODULATION ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICES - Trig modulation electrostatic discharge (ESD) protection devices are presented. An ESD protection device includes a semiconductor substrate. A high voltage N-well (HVNW) region is formed in the semiconductor substrate. An NDD region, a first P-body region and a second P-body region are formed in the HVNW region, wherein the first P-body region is separated from the second P-body region with a predetermined distance, and wherein the NDD region is isolated from the first P-body region with an isolation region. An N | 10-22-2009 |
20100187566 | INSULATED GATE BIPOLAR TRANSISTOR (IGBT) ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICES - Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P | 07-29-2010 |
20100208398 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT AND INTEFRATED CIRCUIT UTILIZING THE SAME - An ESD protection circuit coupled between a first power line and a second power line to avoid damage to an integrated circuit by an ESD event is disclosed. The ESD protection circuit includes a detection unit, a trigger unit, and a discharging unit. The detection unit asserts a detection signal when the ESD event occurs. The trigger unit asserts a first trigger signal and a second trigger signal when the detection is asserted. The discharging unit provides a discharge path to release an ESD current caused by the ESD event when the first and the second trigger signals are asserted. | 08-19-2010 |
20110012204 | TRIG MODULATION ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICES - Trig modulation electrostatic discharge (ESD) protection devices are presented. An ESD protection device includes a semiconductor substrate. A high voltage N-well (HVNW) region is formed in the semiconductor substrate. An NDD region, a first P-body region and a second P-body region are formed in the HVNW region, wherein the first P-body region is separated from the second P-body region with a predetermined distance, and wherein the NDD region is isolated from the first P-body region with an isolation region. An N | 01-20-2011 |
20120001225 | INSULATED GATE BIPOLAR TRANSISTOR (IGBT) ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICES - Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P | 01-05-2012 |
20120056239 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge protection device is coupled between a first power line and a second power line and comprises a P-type well, a first N-type doped region, a first P-type doped region, a second P-type doped region and a second N-type doped region. The first N-type doped region is formed in the P-type well. The first P-type doped region is formed in the first N-type doped region. The second P-type doped region comprises a first portion and a second portion. The first portion of the second P-type doped region is formed in the first N-type doped region. The second portion of the second P-type doped region is formed outside of the first N-type doped region. The second N-type doped region is formed in the first portion of the second P-type doped region. The first P-type doped region, the first N-type doped region, the second P-type doped region and the second N-type doped region constitute an insulated gate bipolar transistor (IGBT). | 03-08-2012 |
20120146151 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge (ESD) protection device including a substrate, a first doped region, a second doped region, and a third doped region, a gate and a plurality of contacts is disclosed. The substrate includes a first conductive type. The first doped region is formed in the substrate and includes a second conductive type. The second doped region is formed in the substrate and includes the second conductive type. The third doped region is formed in the substrate, includes the first conductive type and is located between the first and the second doped regions. The gate is formed on the substrate, located between the first and the second doped regions and comprises a first through hole. The contacts pass through the first through hole to contact with the third doped region. | 06-14-2012 |
Yen-Pong Jou, Taoyuan County TW
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20100161509 | INTELLECTUAL PROPERTY MANAGEMENT METHOD AND INTELLECTUAL PROPERTY BANK SYSTEM - An intellectual property management method and an intellectual property bank system are provided. The intellectual property management method includes raising funds to set up a fund company by a plurality of members to purchase intellectual properties. The intellectual property management method also includes setting up an intellectual property management company to assist purchasing and managing the purchased intellectual properties of the fund company. The intellectual property management method further includes selling the intellectual properties to the members when a special event occurs to the members such that the members can own the intellectual properties to deal with the special event. Therefore, the intellectual property management method can provide the members with powerful protection with fewer resources and lower costs. | 06-24-2010 |
Yow-Jen Jou, Hsinchu City TW
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20100161204 | Method for identification of traffic lane boundary - The invention provides a method for identification of traffic lane boundary. Firstly the microwave signal is received, and the noise reduction is treated for the microwave signal. Then the frequency domain information is employed to calculate the legal set of closed interval, in order to form the frequency span information. Finally, the probability density function model is employed to calculate the frequency span information in order to identify the traffic lane boundary. | 06-24-2010 |
Y-S Jou, Taipei TW
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20130239239 | LMCD1 CANCER MARKERS AND METHODS FOR THEIR USE - The present invention provides LMCD1 cancer markers, and methods, compositions, and kits for their use. The invention also provides expression vectors, host cells, and transgenic animals comprising one or more LMCD1 mutations, and methods for their use in characterizing, diagnosing, and treating cancers, and for identifying potential therapeutics. The invention also provides cancer therapeutics. | 09-12-2013 |
Yuh-Shan Jou, Taipei TW
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20120129869 | PHOSPHORYLATION AND MUTATIONS OF ANAPLASTIC LYMPHOMA KINASE AS A DIAGNOSTIC AND THERAPEUTIC TARGET IN LUNG CANCER - The invention related to the use of high-density loss of heterozygosity (LOH) mapping in lung adenocarcinoma to identify intragenic LOH and driver mutations in different domains of ALK resulted in enhanced tumor growth in xenografted mouse. Mutant (H694R and E1384K) ALKs showed activation of Y1604 ALK and downstream AKT, STAT3 and ERK signaling pathways. Increases of oncogenic signalings resulted in enhanced cell proliferation, colony-formation, cell-migration and tumor-growth in xenografted mouse. Western blot and immunohistochemistry analysis using antibody against phospho-Y1604 ALK on 11 lung cancer cell-lines and 263 cancer specimens indicated ALK activation in all lung cancers regardless of tumor stages. Treating mutant-bearing mice with ALK inhibitor WHI-P 154 resulted in tumor shrinkage, metastasis suppression, and improved survival. Hyperphosphorylation of Y1604 ALK occurred early and continuously throughout tumor progression and could be used as a biomarker to detect lung cancer. Oncogenic ALK point mutations could be treatment targets for lung cancer. | 05-24-2012 |
Yung-Cheng Jou, Hsinchu TW
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20140084255 | Organic Light-Emitting Diode Using Bandgap Matching Dye as Co-Host - The present invention relates to an organic light-emitting diode using an bandgap matching dye as a co-host, comprising: a first conductive layer, a hole injection layer, a hole transport layer, a host light-emitting layer, a first dye, a second dye, an electronic transport layer, an electronic injection layer, and a second conductive layer; wherein the host energy gap of the host light-emitting layer is greater than the energy gap of the first dye, and the energy gap of the first dye is greater than the energy gap of the second dye; therefore the first dye can be a co-host light-emitting layer opposite to the host light-emitting layer, and the energy of the first dye can be effectively conducted to the second dye, such that the luminous efficiency of the light emitted by the second dye through the host light-emitting layer is largely enhanced. | 03-27-2014 |
Yung-Tsan Jou, Taoyuan County TW
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20100320261 | DUAL-PURPOSE FOOD CONTAINER - A dual-purpose food container includes a first bowl body, a second bowl body, and a tear portion. The first bowl body has a first opening, is made of a first heat-insulating material, and is used for accommodating contents. The second bowl body has a second opening and is made of a second heat-insulating material, in which the second opening faces the first opening such that the second bowl body covers the first bowl body and the second bowl body is connected to the first bowl body. The tear portion is located at a connection position between the first bowl body and the second bowl body, and the tear portion is torn to separate the first bowl body from the second bowl body, so that the first bowl body and the second bowl body are respectively used to serve food and soup, thereby achieving a dual purpose. | 12-23-2010 |
20110049225 | FOOD CONTAINER - A food container includes a bowl body, a first cover, a first tear portion, and an eating utensil. The bowl body has a first opening, is made of a first heat-insulating material, and is used for accommodating contents. The first cover is made of a second heat-insulating material, and covers the bowl body, in which the first cover is connected to the bowl body, and includes a sealing portion for placing an additive into the bowl body. The first tear portion is located at a connection position between the bowl body and the first cover, and the first tear portion is torn to separate the bowl body from the first cover. The eating utensil is located at the first cover. | 03-03-2011 |
Yu-Tang Jou, Sanchung TW
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20100122433 | Rotating mechanism for an electronic device and an electronic device with the same - A rotating mechanism for an electronic device has a stationary seat with a limiting recess, a limiting ring mounted through the stationary seat with inner and outer limits, a shaft mounted through the stationary seat and the limiting ring with a limiting protrusion. With the limiting protrusion pushing the inner limit and the outer limit sliding in the limiting recess, the shaft achieves two stages of rotation to enhance the rotating angle in both directions. Moreover, with the adjusting of the sizes of the components, the rotating mechanism may provide rotating angle by 360 to 700 degrees. | 05-20-2010 |
Zuei-Chown Jou, Taipei City TW
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20090153273 | ENERGY TRANSFERRING SYSTEM AND METHOD THEREOF - An energy transferring system including a source-side resonator, an intermediate resonant module, and a device-side resonator is provided. The three resonators substantially have the same resonant frequency for generating resonance. The energy on the source-side resonator is coupled to the intermediate resonant module, such that non-radiative energy transfer is performed between the source-side resonator and the intermediate resonant module. The energy coupled to the intermediate resonant module is further coupled to the device-side resonator, such that non-radiative energy transfer is performed between the intermediate resonant module and the device-side resonator to achieve energy transfer between the source-side resonator and the device-side resonator. The coupling coefficient between the intermediate resonant module and its two adjacent resonators is larger than the coupling coefficient between the source-side resonator and the device-side resonator. The invention has the advantages of high transmission efficiency, small volume, low cost. | 06-18-2009 |
Zuei-Chown Jou, Taoyuan TW
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20130126323 | KEYSWITCH - A keyswitch includes a casing, a key cap and a support device rotatably disposed between the key cap and the casing. One of the casing and the key cap has a first magnetic area and the support device has a second magnetic area corresponding to the first magnetic area. When the key cap is not pressed, a magnetic attraction force between the first and second magnetic areas keeps the key cap at a non-pressed position. When the key cap is pressed by an external force such that the second magnetic area moves away from the first magnetic area, the key cap moves from the non-pressed position toward the pressed position. When the external force is removed, the second magnetic area moves toward the first magnetic area due to the magnetic attraction force such that the key cap moves from the pressed position toward the non-pressed position. | 05-23-2013 |
20140231234 | KEYSWITCH AND KEYBOARD THEREOF - A keyswitch includes a cap, a board, first and second support members rotatably connected to the cap and the board, a seesaw member, and a magnetic member. The seesaw member movably supports at least one of the cap and the first and second support members. The magnetic member is disposed on the board corresponding to the seesaw member. When the cap is pressed, the at least one of the cap and the first and second support members drives the seesaw member to raise and the cap moves from a non-pressed position to a pressed position. When the cap is released, a magnetic attraction force between the magnetic member and the seesaw member drives the seesaw member to raise for lifting the at least one of the cap and the first and second support members, so as to move the cap back to the non-pressed position. | 08-21-2014 |
20140339061 | KEYSWITCH - A keyswitch includes a casing, a key cap and a support device rotatably disposed between the key cap and the casing. One of the casing and the key cap has a first magnetic area and the support device has a second magnetic area corresponding to the first magnetic area. When the key cap is not pressed, a magnetic attraction force between the first and second magnetic areas keeps the key cap at a non-pressed position. When the key cap is pressed by an external force such that the second magnetic area moves away from the first magnetic area, the key cap moves from the non-pressed position toward the pressed position. When the external force is removed, the second magnetic area moves toward the first magnetic area due to the magnetic attraction force such that the key cap moves from the pressed position toward the non-pressed position. | 11-20-2014 |
20150083562 | KEYSWITCH STRUCTURE - A keyswitch structure includes a base, a keycap, at least one lift mechanism, a link, and a restoration mechanism. The lift mechanism is connected to and between the base and the keycap. The link is moveably on the base. The restoration mechanism is disposed on the link and the base and can generate a restoration force. When the keycap is pressed down by a user to move toward the base, a sliding portion of the lift mechanism slides on the base to drive the link to move relative to the base. Further, when the pressing on the keycap by the user is eliminated, the restoration force urges the link to move to drive the sliding portion to slide reversely, so that the keycap moves away from the base. | 03-26-2015 |