Patent application number | Description | Published |
20080251903 | SEMICONDUCTOR MODULE - A module having a semiconductor chip with a first contact element on a first main surface and a second contact element on a second main surface is disclosed. The semiconductor chip is arranged on a carrier. An insulating layer and a wiring layer cover the second main surface and the carrier. | 10-16-2008 |
20090026601 | SEMICONDUCTOR MODULE - A semiconductor module is disclosed. One embodiment provides a first semiconductor chip having a first contact pad on a first main surface and a second contact pad on a second main surface, a first electrically conductive layer applied to the first main surface, a second electrically conductive layer applied to the second main surface, and an electrically insulating material covering the first electrically conductive layer, wherein a surface of the second electrically conductive layer forms an external contact pad and the second electrically conductive layer has a thickness of less than 200 μm. | 01-29-2009 |
20090042337 | Method of Manufacturing an Integrated Circuit Module - A method includes providing an integral array of first carriers, arranging first semiconductor chips on the first carriers, and arranging an integral array of second carriers over the semiconductor chips. | 02-12-2009 |
20090093090 | METHOD FOR PRODUCING A POWER SEMICONDUCTOR MODULE COMPRISING SURFACE-MOUNTABLE FLAT EXTERNAL CONTACTS - A method for producing a power semiconductor module having surface mountable flat external contact areas is disclosed. At least one power semiconductor chip is fixed by its rear side on a drain external contact. An insulation layer covers the top side over the side edges of the semiconductor chip as far as the inner housing plane was a leaving free the source and gate contact areas on the top side of the semiconductor chip and also was partly leaving free the top sides of the corresponding external contacts. | 04-09-2009 |
20090108460 | DEVICE INCLUDING A SEMICONDUCTOR CHIP HAVING A PLURALITY OF ELECTRODES - A device, including a semiconductor chip having a plurality of first electrodes is disclosed. A plurality of second electrodes is arranged on a first surface of the semiconductor chip. A first electrically conductive layer is applied over a first section of the first surface and electrically coupled to the first electrodes arranged within the first section. A second electrically conductive layer is applied over the first electrically conductive layer and electrically coupled to the second electrodes arranged within the first section. | 04-30-2009 |
20090160046 | ELECTRONIC DEVICE AND METHOD - An electronic device and method is disclosed. In one embodiment, a method includes providing an electrically insulating substrate. A first electrically conductive layer is applied over the electrically insulating substrate. A first semiconductor chip is placed over the first electrically conductive layer. An electrically insulating layer is applied over the first electrically conductive layer. A second electrically conductive layer is applied over the electrically insulating layer. | 06-25-2009 |
20090174056 | SEMICONDUCTOR MODULE - A semiconductor module is disclosed. One embodiment provides a first semiconductor chip having a first contact pad on a first main surface and a second contact pad on a second main surface, a first electrically conductive layer applied to the first main surface, a second electrically conductive layer applied to the second main surface, and an electrically insulating material covering the first electrically conductive layer, wherein a surface of the second electrically conductive layer forms an external contact pad and the second electrically conductive layer has a thickness of less than 200 μm. | 07-09-2009 |
20090236749 | ELECTRONIC DEVICE AND MANUFACTURING THEREOF - One aspect is a method including providing a carrier having a first conducting layer, a first insulating layer over the first conducting layer, and at least one through-connection from a first face of the first insulating layer to a second face of the first insulating layer; attaching at least two semiconductor chips to the carrier; applying a second insulating layer over the carrier; opening the second insulating layer until the carrier is exposed; depositing a metal layer over the opened second insulating layer; and separating the at least two semiconductor chips after depositing the metal layer. | 09-24-2009 |
20090283879 | SEMICONDUCTOR DEVICE AND METHOD - A chip carrier includes first, second and third layers with the second layer situated between the first and third layers. The first and third layers are formed of a first material and the second layer is formed of a second material. The second layer has a plurality of holes extending therethrough and the first material fills the holes. | 11-19-2009 |
20100019381 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device and method of manufacturing a semiconductor device. One embodiment provides an electrically conductive carrier. A semiconductor chip is placed over the carrier. An electrically insulating layer is applied over the carrier and the semiconductor chip. The electrically insulating layer has a first face facing the carrier and a second face opposite to the first face. A first through-hole is in the electrically insulating layer. Solder material is deposited in the first through-hole and on the second face of the electrically insulating layer. | 01-28-2010 |
20100295171 | ELECTRONIC DEVICE AND METHOD - An electronic device and method is disclosed. In one embodiment, a method includes providing an electrically insulating substrate. A first electrically conductive layer is applied over the electrically insulating substrate. A first semiconductor chip is placed over the first electrically conductive layer. An electrically insulating layer is applied over the first electrically conductive layer. A second electrically conductive layer is applied over the electrically insulating layer. | 11-25-2010 |
20120112105 | HIGH PRESSURE CONTROL VALVE - High-pressure regulating valve ( | 05-10-2012 |
20130252382 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes providing an electrically conductive carrier and placing a semiconductor chip over the carrier. The method includes applying an electrically insulating layer over the carrier and the semiconductor chip. The electrically insulating layer has a first face facing the carrier and a second face opposite to the first face. The method includes selectively removing the electrically insulating layer and applying solder material where the electrically insulating layer is removed and on the second face of the electrically insulating layer. | 09-26-2013 |
20130328213 | ELECTRONIC DEVICE INCLUDING A CARRIER AND A SEMICONDUCTOR CHIP ATTACHED TO THE CARRIER AND MANUFACTURING THEREOF - One aspect is a device including a carrier comprising a first conducting layer, a first insulating layer over the first conducting layer, and at least one first through-connection from a first face of the first insulating layer to a second face of the first insulating layer. A semiconductor chip is attached to the carrier and a second insulating layer is over the carrier and the semiconductor chip. A metal layer is over the second insulating layer. A second through-connection is through the second insulating layer electrically coupling the semiconductor chip to the metal layer. A third through-connection is through the second insulating layer electrically coupling the carrier to the metal layer. | 12-12-2013 |
20140001480 | Lead Frame Packages and Methods of Formation Thereof | 01-02-2014 |
20140001615 | Package-In-Packages and Methods of Formation Thereof | 01-02-2014 |
20140008702 | Semiconductor Packages Having Multiple Lead Frames and Methods of Formation Thereof - In accordance with an embodiment of the present invention, a semiconductor package includes a first lead frame having a first die paddle, and a second lead frame, which has a second die paddle and a plurality of leads. The second die paddle is disposed over the first die paddle. A semiconductor chip is disposed over the second die paddle. The semiconductor chip has a plurality of contact regions on a first side facing the second lead frame. The plurality of contact regions is coupled to the plurality of leads. | 01-09-2014 |
20140110828 | Semiconductor Packages and Methods of Formation Thereof - In accordance with an embodiment of the present invention, a semiconductor device includes a lead frame having a die paddle and a lead. A chip is disposed over the die paddle of the lead frame. The semiconductor device further includes a clip, which is disposed over the chip. The clip couples a pad on the chip to the lead of the lead frame. The clip also includes a heat sink. | 04-24-2014 |
20140138803 | CHIP ARRANGEMENTS AND METHODS FOR MANUFACTURING A CHIP ARRANGEMENT - A chip arrangement is provided, the chip arrangement including: a carrier; a chip disposed over the carrier, the chip including one or more contact pads, wherein a first contact pad of the one or more contact pads is electrically contacted to the carrier; a first encapsulation material at least partially surrounding the chip; and a second encapsulation material at least partially surrounding the first encapsulation material. | 05-22-2014 |
20140145318 | Semiconductor Packages and Methods of Formation Thereof - In accordance with an embodiment of the present invention, a semiconductor package includes a die paddle, and an encapsulant disposed around the die paddle. The semiconductor package has a first sidewall and a second sidewall. The second sidewall is perpendicular to the first sidewall. The first sidewall and the second sidewall define a corner region. A tie bar is disposed within the encapsulant. The tie bar couples the die paddle and extends away from the die paddle. A dummy lead is disposed in the corner region. The dummy lead is not electrically coupled to another electrically conductive component within the semiconductor package. The distance between the dummy lead and the tie bar is less than a shortest distance between the tie bar and other leads or other tie bars in the semiconductor package. | 05-29-2014 |
20140151856 | Chip Module, an Insulation Material and a Method for Fabricating a Chip Module - The chip module includes a carrier, a semiconductor chip arranged on or embedded inside the carrier, and an insulation layer that at least partly covers a face of the carrier. The dielectric constant ∈ | 06-05-2014 |
20140210061 | CHIP ARRANGEMENT AND CHIP PACKAGE - Various embodiments provide a chip arrangement. The chip arrangement may include a first chip including a first contact and a second contact; a second chip; a leadframe including a first leadframe portion and a second leadframe portion electrically insulated from the first leadframe portion; and a plurality of pins coupled to the leadframe. At least one first pin is coupled to the first leadframe portion and at least one second pin is coupled to the second leadframe portion. The first contact of the first chip is electrically coupled to the first leadframe portion and the second contact of the first chip is coupled to the second leadframe portion. A contact of the second chip is electrically coupled to the second leadframe portion. | 07-31-2014 |
20140217596 | POWER TRANSISTOR ARRANGEMENT AND METHOD FOR MANUFACTURING THE SAME - Various embodiments provide a power transistor arrangement. The power transistor arrangement may include a carrier; a first power transistor having a control electrode and a first power electrode and a second power electrode; and a second power transistor having a control electrode and a first power electrode and a second power electrode. The first power transistor and the second power transistor may be arranged next to each other on the carrier such that the control electrode of the first power transistor and the control electrode of the second power transistor are facing the carrier. | 08-07-2014 |
20140252537 | PACKAGE ARRANGEMENT AND A METHOD OF MANUFACTURING A PACKAGE ARRANGEMENT - In various embodiments, a package arrangement is provided. The package arrangement may include a first package. The package arrangement may further include a through hole package including at least one contact terminal. The first package may include at least one hole in an encapsulant to receive the at least one contact terminal of the through hole package. The received at least one contact terminal may provide a solder contact. | 09-11-2014 |
20140252577 | CHIP CARRIER STRUCTURE, CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - Various embodiments provide a chip carrier structure. The chip carrier structure may include a structured metallic chip carrier; encapsulating material at least partially filling the structure; wherein the main surfaces of the metallic chip carrier are free from the encapsulating material. | 09-11-2014 |
20140291849 | Multi-Level Semiconductor Package - A semiconductor package includes a semiconductor die having a first electrode at a first side and a second electrode at a second side opposing the first side, a first lead under the semiconductor die and connected to the first electrode at a first level of the package, and a second lead having a height greater than the first lead and terminating at a second level in the package above the first level, the second level corresponding to a height of the semiconductor die. A connector of a single continuous planar construction over the semiconductor die and the second lead is connected to both the second electrode and the second lead at the same second level of the package. | 10-02-2014 |
20140301039 | PACKAGE AND A METHOD OF MANUFACTURING THE SAME - In various embodiments, a package may be provided. The package may include a chip carrier. The package may further include a chip arranged over the chip carrier. The package may also include encapsulation material encapsulating the chip and partially the chip carrier. A coolant receiving recess may be provided over the chip in the encapsulation material, wherein the coolant receiving recess is configured to receive coolant. | 10-09-2014 |
20140306331 | CHIP AND CHIP ARRANGEMENT - Various embodiments provide a chip. The chip may include a body having two main surfaces and a plurality of side surfaces; a first power electrode extending over at least one main surface and at least one side surface of the body; and a second power electrode extending over at least one main surface and at least one side surface of the body. | 10-16-2014 |
20140312360 | Semiconductor Power Device Having a Heat Sink - A semiconductor device includes an electrically conducting carrier having a mounting surface. The semiconductor device further includes a metal block having a first surface facing the electrically conducting carrier and a second surface facing away from the electrically conducting carrier. A semiconductor power chip is disposed over the second surface of the metal block. | 10-23-2014 |
20140374913 | CIRCUIT ARRANGEMENT AND METHOD FOR MANUFACTURING THE SAME - Various embodiments may provide a circuit arrangement. The circuit arrangement may include a carrier having at least one electrically conductive line; a plurality of discrete encapsulated integrated circuits arranged on the carrier; wherein a first integrated circuit of the plurality of integrated circuits is in electrical contact with a second integrated circuit of the plurality of integrated circuits to form a first current path bypassing the carrier; and wherein the first integrated circuit of the plurality of integrated circuits is in electrical contact with the second integrated circuit of the plurality of integrated circuits to form a second current path via the at least one electrically conductive line. | 12-25-2014 |
20150041967 | Molded Semiconductor Package with Backside Die Metallization - A semiconductor package is manufactured by providing a semiconductor die with a terminal at a first side of the die, providing a material coupled to the die at an opposing second side of the die and embedding the die in a molding compound so that the die is covered by the molding compound on all sides except the first side. The molding compound is thinned at a side of the molding compound adjacent the second side of the die, to expose the material at the second side of the die without exposing the second side of the die. An electrical connection is formed to the terminal at the first side of the die. In the case of a transistor die, the terminal can be a source terminal and the transistor die can be attached source-down to a metal block such as a die paddle of a lead frame. | 02-12-2015 |
20150041984 | Electronic Component and Method - An electronic component includes a high-voltage depletion-mode transistor, a low-voltage enhancement-mode transistor arranged adjacent and spaced apart from the high-voltage depletion-mode transistor, and an electrically conductive member electrically coupling a first current electrode of the high-voltage depletion-mode transistor to a first current electrode of the low-voltage enhancement-mode transistor. The electrically conductive member has a sheet-like form. | 02-12-2015 |
20150060878 | Semiconductor Packages Having Multiple Lead Frames and Methods of Formation Thereof - In accordance with an embodiment of the present invention, a semiconductor package includes a first lead frame having a first die paddle, and a second lead frame, which has a second die paddle and a plurality of leads. The second die paddle is disposed over the first die paddle. A semiconductor chip is disposed over the second die paddle. The semiconductor chip has a plurality of contact regions on a first side facing the second lead frame. The plurality of contact regions is coupled to the plurality of leads. | 03-05-2015 |